code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ts_buf (
in,
out,
en
);
//standard parametrized width tristate buffer
parameter WIDTH = 1;
input [WIDTH-1:0] in;
input en;
output [WIDTH-1:0] out;
tri [WIDTH-1:0] out;
assign out = (en) ? in : {(WIDTH) {1'bz}};
endmodule
| 7.372543 |
module ts_ci_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [8:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [8:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RE... | 6.827383 |
module ts_ci_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [8:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [8:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RE... | 6.827383 |
module ts_ci_sync (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RE... | 7.136378 |
module ts_ci_sync (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RE... | 7.136378 |
module name - ts_clock_control
// Version: COC_V1.0.0_20211202
// Created:
// by - fenglin
// at - 12.2021
////////////////////////////////////////////////////////////////////////////
// Description:
// ts_clock_control
///////////////////////////////////////////////////////////////////////////... | 7.199993 |
module TS_CONTROL #(
parameter word_size = 8
) (
input [word_size-1 : 0] TS_IN_in,
DIN_in,
input CLK,
SYNC,
RESET,
CLK_W,
EN,
output [word_size-1 : 0] TS_OUT
);
reg [word_size-1 : 0] out;
assign TS_OUT = out;
reg [word_size-1 : 0] TS_IN, DIN;
always @(posedge CLK) TS_IN <= TS... | 6.951506 |
module ts_gen128 (
rst,
clk,
ts_sync,
ts_valid,
ts_eop,
ts_data
);
parameter U_DLY = 1;
parameter PKT_INTERVAL = 125000000;
parameter ADAPT_FIELD_CTRL = 2'b01; //only payload
parameter ADAPT_FIELD_LEN = 8'h10;
input rst;
input clk;
output ts_sync;
output ts_valid;
output ts... | 7.212648 |
module ts_gen32 (
rst,
clk,
ts_sync,
ts_valid,
ts_eop,
ts_data
);
parameter U_DLY = 1;
parameter PKT_INTERVAL = 125000000;
parameter ADAPT_FIELD_CTRL = 2'b01; //only payload
parameter ADAPT_FIELD_LEN = 8'h10;
input rst;
input clk;
output ts_sync;
output ts_valid;
output ts_... | 7.3663 |
module ts_gen8 (
rst,
clk,
ts_sync,
ts_valid,
ts_eop,
ts_data
);
parameter U_DLY = 1;
parameter PKT_INTERVAL = 125000000;
parameter ADAPT_FIELD_CTRL = 2'b01; //only payload
parameter ADAPT_FIELD_LEN = 8'h10;
input rst;
input clk;
output ts_sync;
output ts_valid;
output ts_e... | 7.748277 |
module ts_i2c (
input clk,
input rst_n,
input scl,
input sda,
output clk_o,
output rst_n_o,
output scl_o,
output sdi,
output start,
output stop,
output [3:0] i2c_state,
output [3:0] cnt
);
wire sdi;
wire sdo;
assign clk_o = clk;
assign rst_n_o = r... | 7.828939 |
module name - ts_injection_schedule
// Version: TIS_V1.0
// Created:
// by - fenglin
// at - 10.2020
////////////////////////////////////////////////////////////////////////////
// Description:
// injection schedule of time-sensitive packet
// - parse command;
// - use ... | 7.593113 |
module ts_j83_buf (
rst,
clk,
clk_x2,
ts_rd_valid,
ts_i_valid,
ts_i_data,
ts_o_data
);
parameter RAM_WIDTH = 8;
parameter RAM_DEPTH_BIT = 10;
input rst;
input clk;
input clk_x2;
input ts_rd_valid;
input ts_i_valid;
input [7:0] ts_i_data;
output [7:0] ts_o_data;
wire... | 7.320353 |
module ts_j83_sdpram (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
input clkb;
input [9 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_2 #(
.C_ADDRA_WIDTH(10),
... | 6.7988 |
module ts_j83_sdpram (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [7 : 0] doutb;
// WARNING: This file provides a module declaration only, it does not support
... | 6.7988 |
module ts_mike_fsm (
in,
clock,
out
);
input [3:0] in;
input clock;
output [9:0] out;
reg [9:0] out;
reg [2:0] current_state;
reg [2:0] next_state;
// Input patterns
parameter pattern_X = 4'b0000, pattern_Y = 4'b0101, pattern_Z = 4'b1111, pattern_W = 4'b0011;
// Output patterns
paramet... | 7.159496 |
module ts_radian (
input clk,
input rst_n,
input touch,
output [7:0] sin_o,
output clk_o,
output rst_n_o,
output touch_o,
output [3:0] cnt_o
);
reg [31:0] angle;
reg [ 3:0] cnt;
wire [31:0] sin;
assign clk_o = clk;
assign rst_n = rst_n_o;
assign touch_o = touch;
assign... | 7.907954 |
module name - ts_submit_schedule
// Version: TSS_V1.0
// Created:
// by - fenglin
// at - 10.2020
////////////////////////////////////////////////////////////////////////////
// Description:
// submit schedule of time-sensitive packet
// - parse command;
// - use a true... | 9.018172 |
module Instruction_reg (
clk,
Read_Addr,
instruction,
reset
);
input clk, reset;
input [7:0] Read_Addr;
output [31:0] instruction;
wire instruction;
endmodule
| 6.692892 |
module CU (
instruction,
busy_wait,
OUT1addr,
OUT2addr,
INaddr,
Imm,
Select,
addSubMUX,
imValueMUX,
dmMUX,
read,
write,
address
);
input [31:0] instruction;
input busy_wait;
output [2:0] OUT1addr;
output [2:0] OUT2addr;
output [2:0] Select;
output [2:0] IN... | 7.054686 |
module TwosComplement (
OUTPUT,
INPUT
);
input [7:0] INPUT;
output [7:0] OUTPUT;
assign OUTPUT[7:0] = -INPUT[7:0];
endmodule
| 8.45255 |
module ALU (
RESULT,
DATA1,
DATA2,
SELECT
);
input [7:0] DATA1, DATA2; //Source 1 & 2
input [2:0] SELECT;
output [7:0] RESULT;
reg [7:0] Res;
assign RESULT = Res;
always @(DATA1, DATA2, SELECT) begin
case (SELECT)
0: Res = DATA1; //Forward ( loadi, mov )
1: Res = DATA1 +... | 7.336322 |
module data_mem (
clk,
rst,
read,
write,
address,
write_data,
read_data,
busy_wait
);
input clk;
input rst;
input read;
input write;
input [6:0] address;
input [15:0] write_data;
output [15:0] read_data;
output busy_wait;
reg busy_wait = 1'b0;
reg [15:0] read_data;
... | 7.214114 |
module Comparator (
Out,
Input1,
Input2
);
input [3:0] Input1;
input [3:0] Input2;
output Out;
wire out1, out2, out3, out4;
xnor xnor1 (out1, Input1[0], Input2[0]);
xnor xnor2 (out2, Input1[1], Input2[1]);
xnor xnor3 (out3, Input1[2], Input2[2]);
xnor xnor4 (out4, Input1[3], Input2[3]);
... | 8.939213 |
module tt800 (
input clk, // timespec 3.0 ns
input en,
input init,
input [31:0] initv,
output [31:0] y
);
wire [31:0] tap1, tap2;
wire [31:0] x = tap1 ^ (tap2 >> 1) ^ ({32{tap2[0]}} & 32'h8ebfd028);
wire [31:0] newv = init ? initv : x;
reg_delay #(
.dw (32),
.len(18)
) d1 (
... | 6.724634 |
module tta16_tile_tb;
`define IO_DECODE_BITS 20:18
`define IO_FLUSH 3'b1_10__
`define IO_DMA 3'b1_00__
`define IO_CRTC 3'b0_00__
`define IO_SPROM 3'b0_01__
`define IO_LEDS 3'b0_10__
reg wb_clk = 1;
reg cpu_clk = 1;
reg reset = 0;
reg cache_reset = 0;
always #15 wb_clk = ~wb_clk;
always #5 cpu... | 8.257891 |
module tta_stream4to4_async #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1
) (
input enable_i,
input [1:0] src_i,
input [1:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
output reg [ 3:0] srcsels_o,
output reg [... | 8.849374 |
module tta_stream4to4_sync #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1,
parameter ENCLR = 1
) (
input clock_i,
input enable_i,
input [1:0] src_i,
input [1:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
out... | 8.849374 |
module tta_stream4to8_async #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1
) (
input enable_i,
input [1:0] src_i,
input [2:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
output reg [ 3:0] srcsels_o,
output reg [... | 8.849374 |
module tta_stream4to8_sync #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1,
parameter ENCLR = 1
) (
input clock_i,
input enable_i,
input [1:0] src_i,
input [2:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
out... | 8.849374 |
module tta_stream8to8_async #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1,
parameter ENCLR = 1
) (
input enable_i,
input [2:0] src_i,
input [2:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
input [MSB:0] data4_i,... | 8.429529 |
module tta_stream8to8_sync #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1,
parameter ENCLR = 1
) (
input clock_i,
input enable_i,
input [2:0] src_i,
input [2:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
inpu... | 8.429529 |
module: timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ttb;
// Inputs
reg clk;
reg reset;
reg [3:2] PrAddr;
reg Wr_en;
reg [31:0] Data_in;
// Outputs
wire IRQ;
wire... | 7.287821 |
module ttc_count_rst_lite (
//inputs
n_p_reset,
pclk,
pwdata,
clk_ctrl_reg_sel,
restart,
//outputs
count_en_out,
clk_ctrl_reg_out
);
//-----------------------------------------------------------------------------
// PORT DECLARATIONS
//-------------------------------------... | 7.404301 |
module ls74 (
input n_pre1,
n_pre2,
input n_clr1,
n_clr2,
input clk1,
clk2,
input d1,
d2,
output reg q1,
q2,
output n_q1,
n_q2
);
always @(posedge clk1 or negedge n_pre1 or negedge n_clr1) begin
if (!n_pre1) q1 <= 1;
else if (!n_clr1) q1 <= 0;
else q1 <= d1... | 6.902507 |
module ls161 //asynchronous reset/clear
(
input n_clr,
input clk,
input [3:0] din,
input enp,
ent,
input n_load,
output [3:0] q,
output rco
);
reg [3:0] data = 4'b0;
always @(posedge clk or negedge n_clr) begin
if (!n_clr) data <= 4'd0;
e... | 7.406391 |
module ls273 (
input [7:0] d,
input clk,
input res,
output reg [7:0] q
);
always @(posedge clk or negedge res) begin
if (!res) q <= 8'h00;
else q <= d;
end
endmodule
| 6.811434 |
module ls166 (
input clk,
input load,
input [7:0] in,
output out
);
reg [7:0] tmp;
always @(posedge clk) begin
if (!load) tmp <= in;
else tmp <= {tmp[6:0], 1'b0};
end
assign out = tmp[7];
endmodule
| 6.876022 |
module ls174 (
input [5:0] d,
input clk,
input mr,
output reg [5:0] q
);
always @(posedge clk or negedge mr) begin
if (!mr) q <= 6'b000000;
else q <= d;
end
endmodule
| 7.110512 |
module ls157 (
input [3:0] i0,
input [3:0] i1,
input n_e,
input s,
output [3:0] z
);
assign z = (!n_e && !s) ? i0 : (!n_e && s) ? i1 : 4'b0000;
endmodule
| 7.048406 |
module TTL74148_RTL (
nS,
nIN,
Y,
Ys,
Yex
);
input nS;
input [7:0] nIN;
output reg [2:0] Y;
output reg Ys;
output reg Yex;
always @(nS, nIN) begin
if (nS) begin
Y <= 3'b111;
Yex <= 1'b1;
Ys <= 1'b1;
end else if (nIN == 8'b11111111) begin
Y <= 3'b111;... | 6.669471 |
module
//
`timescale 1ns/10ps
module TTL_7400 (
input A1, B1, // Unit A
output Y1,
input A2, B2, // Unit B
output Y2,
input A3, B3, // Unit C
output Y3,
input A4, B4, // Unit D
output Y4
);
not #(0:9:15, 0:10:15) (Y1, A1 & B1);
not #(0:9:15, 0:10:15) (Y2, A2 & B2);... | 6.662614 |
module
//
`timescale 1ns/10ps
module TTL_7402 (
input A1, B1, // Unit A
output Y1,
input A2, B2, // Unit B
output Y2,
input A3, B3, // Unit C
output Y3,
input A4, B4, // Unit D
output Y4
);
not #(0:10:15, 0:10:15) (Y1, A1 | B1);
not #(0:10:15, 0:10:15) (Y2, A2 | B2... | 6.662614 |
module
//
`timescale 1ns/10ps
module TTL_7404 (
input A1, // Unit A
output Y1,
input A2, // Unit B
output Y2,
input A3, // Unit C
output Y3,
input A4, // Unit D
output Y4,
input A5, // Unit E
output Y5,
input A6, // Unit F
output Y6
);
not #(0:9:15, 0:... | 6.662614 |
module
//
`timescale 1ns/10ps
module TTL_7408 (
input A1, B1, // Unit A
output Y1,
input A2, B2, // Unit B
output Y2,
input A3, B3, // Unit C
output Y3,
input A4, B4, // Unit D
output Y4
);
and #(0:8:15, 0:10:20) (Y1, A1, B1);
and #(0:8:15, 0:10:20) (Y2, A2, B2);
... | 6.662614 |
module ttl_74107a_AsyncClr #(
parameter BLOCKS = 2
) (
input wire [BLOCKS-1:0] CLRn,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] K,
input wire [BLOCKS-1:0] Clk,
input wire [BLOCKS-1:0] Cen,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Qn
);
//----------------------... | 6.908183 |
module ttl_74107a_sync #(
parameter BLOCKS = 2
) (
input wire [BLOCKS-1:0] Reset_n,
input wire [BLOCKS-1:0] CLRn,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] K,
input wire [BLOCKS-1:0] Clk,
input wire [BLOCKS-1:0] Cen,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0]... | 6.668561 |
module ttl_74109_cl #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Clear_bar,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] Kn,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Q_bar
);
//--------------... | 6.623586 |
module ttl_74109_pre #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Preset_bar,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] Kn,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Q_bar
);
//------------... | 6.629015 |
module ttl_74112 #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Preset_bar,
input wire [BLOCKS-1:0] Clear_bar,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] K,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLO... | 6.837249 |
module ttl_74112_sync #(
parameter BLOCKS = 2
) (
input wire [BLOCKS-1:0] PREn,
input wire [BLOCKS-1:0] CLRn,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] K,
input wire [BLOCKS-1:0] Clk,
input wire [BLOCKS-1:0] Cen,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Qn
... | 7.543154 |
module ttl_74138 #(
parameter WIDTH_OUT = 8,
WIDTH_IN = $clog2(WIDTH_OUT),
DELAY_RISE = 15,
DELAY_FALL = 15
) (
input wire Enable1_bar, //4 G2An
input wire Enable2_bar, //5 G2Bn
input wire Enable3, //6 G1
input wire [WIDTH_IN-1:0] A, //3,2,1 C,B,A
output wire [WIDTH_OUT-1:0] Y /... | 7.370719 |
module ttl_74138_nodly #(
parameter WIDTH_OUT = 8,
WIDTH_IN = $clog2(WIDTH_OUT)
) (
input wire Enable1_bar, //4 G2An
input wire Enable2_bar, //5 G2Bn
input wire Enable3, //6 G1
input wire [WIDTH_IN-1:0] A, //3,2,1 C,B,A
output wire [WIDTH_OUT-1:0] Y //7,9,10,11,12,13,14,15 Y[7:0]
);
... | 7.559387 |
module ttl_74139 #(
parameter DELAY = 15
) (
input wire Enable_bar,
input wire [1:0] A_2D,
output wire [3:0] Y_2D
);
assign #DELAY Y_2D[0] = ~(~Enable_bar & ~A_2D[1] & ~A_2D[0]);
assign #DELAY Y_2D[1] = ~(~Enable_bar & ~A_2D[1] & A_2D[0]);
assign #DELAY Y_2D[2] = ~(~Enable_bar & A_2D[1] & ~A_2D[0]... | 7.83375 |
module ttl_74139_nodly (
input wire Enable_bar,
input wire [1:0] A_2D,
output wire [3:0] Y_2D
);
assign Y_2D[0] = ~(~Enable_bar & ~A_2D[1] & ~A_2D[0]);
assign Y_2D[1] = ~(~Enable_bar & ~A_2D[1] & A_2D[0]);
assign Y_2D[2] = ~(~Enable_bar & A_2D[1] & ~A_2D[0]);
assign Y_2D[3] = ~(~Enable_bar & A_2D[1]... | 7.289595 |
module ttl_74153 #(
parameter BLOCKS = 2,
WIDTH_IN = 4,
WIDTH_SELECT = $clog2(WIDTH_IN),
DELAY_RISE = 12,
DELAY_FALL = 15
) (
input wire [BLOCKS-1:0] Enable_bar,
input wire [WIDTH_SELECT-1:0] Select,
input wire [BLOCKS*WIDTH_IN-1:0] A_2D,
output wire [BLOCKS-1:0] Y
);
//----------... | 7.33142 |
module ttl_74155 #(parameter BLOCKS_DIFFERENT = 2, BLOCK0 = 0, BLOCK1 = 1, WIDTH_OUT = 4,
WIDTH_IN = $clog2(WIDTH_OUT), DELAY_RISE = 13, DELAY_FALL = 18)
(
input Enable1C,
input Enable1G_bar,
input Enable2C_bar,
input Enable2G_bar,
input [WIDTH_IN-1:0] A,
output [BLOCKS_DIFFERENT*WIDTH_OU... | 6.865215 |
module ttl_74157 #(
parameter BLOCKS = 4,
WIDTH_IN = 2,
WIDTH_SELECT = $clog2(WIDTH_IN),
DELAY_RISE = 12,
DELAY_FALL = 13
) (
input wire Enable_bar,
input wire [WIDTH_SELECT-1:0] Select,
input wire [BLOCKS*WIDTH_IN-1:0] A_2D,
output wire [BLOCKS-1:0] Y
);
//-----------------------... | 7.859778 |
module ttl_74161 #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire Clear_bar,
input wire Load_bar,
input wire ENT,
input wire ENP,
input wire [WIDTH-1:0] D,
input wire Clk,
output wire RCO,
output wire [WIDTH-1:0] Q
);
//--------------------------------... | 7.566493 |
module ttl_74161a #(
parameter WIDTH = 4,
DELAY_RISE = 15,
DELAY_FALL = 15
) (
input wire Clear_bar, //1
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
input wire Clk, //2
output wire RCO, //15
output wi... | 7.226543 |
module ttl_74161a_sync #(
parameter WIDTH = 4
) (
input wire Clk,
input wire Cen,
input wire Clear_bar, //1
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
output wire RCO, //15
output wire [WIDTH-1:0] Q //QD... | 8.145892 |
module ttl_74161_sync #(
parameter WIDTH = 4
) (
input wire Clk, //2
input wire Clear_bar, //1 ASYNCHRONOUS
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
input wire Cen, //Clock enable signal and trigger
outpu... | 7.692636 |
module ttl_74163a #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire Clear_bar, //1
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
input wire Clk, //2
output wire RCO, //15
output wire... | 7.111494 |
module ttl_74163a_sync #(
parameter WIDTH = 4
) (
input wire Clk, //2
input wire Clear_bar, //1 SYNCHRONOUS
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
input wire Cen, //Clock enable signal and trigger
outpu... | 7.550143 |
module ttl_74164_sync (
input wire A,
B, //serial input data
input wire Reset_n,
input wire clk,
//(*direct_enable*) input wire Cen,
input wire Cen,
input wire MRn, //Master Reset (async)
output reg Q0,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7
);
wire serdata;
assign ... | 6.503079 |
module ttl_74169_sync (
input wire Reset_n,
input wire clk,
input wire cen,
input wire direction, // 1 = Up, 0 = Down
input wire load_n, // 1 = Count, 0 = Load
input wire ent_n,
input wire enp_n,
input wire [3:0] P,
output wire rco_n, // Ripple Carry-out (RCO)
output wire [3:... | 7.384956 |
module ttl_74174 #(
parameter DELAY_RISE = 20,
DELAY_FALL = 21
) (
input wire Clk,
input wire RESETn,
input wire [5:0] D,
output wire [5:0] Q
);
//------------------------------------------------//
reg [5:0] Q_current; // = 6'h00;
//initial Q_current = 6'h00; //supposition
always @(pos... | 6.677053 |
module ttl_74174_sync #(
parameter BLOCKS = 6
) (
input wire Clk,
//(*direct_enable*) input wire Cen,
input wire Cen,
input wire Clr_n,
input wire [BLOCKS-1:0] D,
output wire [BLOCKS-1:0] Q
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
reg last_cen... | 6.699463 |
module ttl_74175_sync (
input wire Reset_n,
input wire Clk,
//(*direct_enable*) input wire Cen,
input wire Cen,
input wire Clr_n,
input wire [3:0] D,
output wire [3:0] Q,
output wire [3:0] Q_bar
);
//------------------------------------------------//
reg [3:0] Q_current;
reg last_c... | 6.840748 |
module ttl_74194 #(
parameter DELAY_RISE = 12,
DELAY_FALL = 15
) (
input wire CR_n,
input wire CP,
input wire S0,
S1,
input wire Dsl,
Dsr,
input wire D0,
D1,
D2,
D3,
output wire Q0,
Q1,
Q2,
Q3
);
reg [0:3] q_reg = 4'b0000;
wire [1:0] s_reg;
as... | 7.591104 |
module ttl_74194_sync (
input wire clk,
input wire cen, //CP
input wire CR_n,
input wire S0,
S1,
input wire Dsl,
Dsr,
input wire D0,
D1,
D2,
D3,
output wire Q0,
Q1,
Q2,
Q3
);
reg [3:0] q_reg;
wire [1:0] s_reg;
reg last_cen;
initial q_reg = 4'... | 7.141089 |
module
//
`timescale 1ns/10ps
module TTL_7421 (
input A1, B1, C1, D1, // Unit A
output Y1,
input A2, B2, C2, D2, // Unit B
output Y2
);
assign #(0:8:15, 0:10:20) Y1 = A1 & B1 & C1 & D1;
assign #(0:8:15, 0:10:20) Y2 = A2 & B2 & C2 & D2;
endmodule
| 6.662614 |
module ttl_74245 #(parameter DELAY_RISE = 12, DELAY_FALL = 12)
module ttl_74244 #(parameter DELAY_RISE = 12, DELAY_FALL = 12)
(
input wire G1n,
input wire G2n,
input wire [3:0] A1,
input wire [3:0] A2,
output wire [3:0] Y1,
output wire [3:0] Y2
);
assign #(DELAY_RISE, DELAY_FALL) Y1 = (!G1n)... | 7.13794 |
module ttl_74245 #(
parameter DELAY_RISE = 12,
DELAY_FALL = 12
) (
input wire DIR,
input wire Enable_bar,
inout wire [7:0] A,
inout wire [7:0] B
);
assign #(DELAY_RISE, DELAY_FALL) A = (Enable_bar || DIR) ? 8'hzz : B; //B->A
assign #(DELAY_RISE, DELAY_FALL) B = (Enable_bar || !DIR) ? 8'hzz ... | 7.462193 |
module ttl_74245_2dly #(
parameter DELAY_AB = 12,
DELAY_BA = 12
) (
input wire DIR,
input wire Enable_bar,
inout wire [7:0] A,
inout wire [7:0] B
);
assign #DELAY_BA A = (Enable_bar || DIR) ? 8'hzz : B; //B->A
assign #DELAY_AB B = (Enable_bar || !DIR) ? 8'hzz : A; //A->B
endmodule
| 7.03738 |
module ttl_74257 #(
parameter BLOCKS = 4,
WIDTH_IN = 2,
WIDTH_SELECT = $clog2(WIDTH_IN),
DELAY_RISE = 12,
DELAY_FALL = 13
) (
input wire Enable_bar, //0 enable logic output, 1 hi-Z output
input wire [WIDTH_SELECT-1:0] Select, //0 select A, 1 select B
input wire [BLOCKS*WIDTH_IN-1:0] A_... | 7.827827 |
module ttl_74257_noHiZout #(
parameter BLOCKS = 4,
WIDTH_IN = 2,
WIDTH_SELECT = $clog2(WIDTH_IN)
) (
input wire Enable_bar, //0 enable logic output, 1 hi-Z output
input wire [WIDTH_SELECT-1:0] Select, //0 select A, 1 select B
input wire [BLOCKS*WIDTH_IN-1:0] A_2D,
output wire [BLOCKS-1:0] ... | 8.288341 |
module ttl_74273 #(
parameter DELAY_RISE = 12,
DELAY_FALL = 13
) (
input wire Clk,
input wire RESETn,
input wire [7:0] D,
output wire [7:0] Q
);
//------------------------------------------------//
reg [7:0] Q_current;
// initial begin
// Q_current <= 8'h00;
// end//supposition
a... | 6.554858 |
module ttl_74283 #(
parameter WIDTH = 4
) (
input wire [WIDTH-1:0] A,
input wire [WIDTH-1:0] B,
input wire C_in,
output wire [WIDTH-1:0] Sum,
output wire C_out
);
//------------------------------------------------//
reg [WIDTH-1:0] Sum_computed;
reg C_computed;
always @(*) begin
{C... | 7.398786 |
module ttl_74283_nodly #(
parameter WIDTH = 4
) (
input wire [WIDTH-1:0] A,
input wire [WIDTH-1:0] B,
input wire C_in,
output wire [WIDTH-1:0] Sum,
output wire C_out
);
//------------------------------------------------//
reg [WIDTH-1:0] Sum_computed;
reg C_computed;
always @(*) begin
... | 8.052166 |
module ttl_74298 (
input wire WS,
input wire clk,
input wire [3:0] A,
input wire [3:0] B,
output wire [3:0] Q
);
wire WSn;
wire WSnn;
wire clkn;
assign WSn = ~WS;
assign WSnn = ~WSn;
assign clkn = ~clk;
wire [3:0] andA;
wire [3:0] andB;
wire [3:0] norAB;
wire [3:0] not_norAB;
... | 6.789049 |
module SR_FF #(
parameter DELAY = 18
) (
input wire S,
input wire R,
input wire clk,
output wire Q,
output wire Qn
);
reg Qr;
always @(posedge clk) begin
case ({
S, R
})
2'b00: Qr <= Qr;
2'b01: Qr <= 1'b0;
2'b10: Qr <= 1'b1;
2'b11: Qr <= 1'bx;
en... | 6.914922 |
module ttl_74298_sync (
input wire VIDEO_RSTn,
input wire clk,
input wire Cen,
input wire WS,
input wire [3:0] A,
input wire [3:0] B,
output wire [3:0] Q
);
wire WSn;
wire WSnn;
assign WSn = ~WS;
assign WSnn = ~WSn;
wire [3:0] andA;
wire [3:0] andB;
wire [3:0] norAB;
wire ... | 7.557154 |
module SR_FF_sync //detects falling edge of Cen
(
input wire VIDEO_RSTn,
input wire clk,
input wire Cen,
input wire S,
input wire R,
output wire Q,
output wire Qn
);
reg Qr;
reg last_cen;
always @(posedge clk) begin
if (!VIDEO_RSTn) begin
Qr <= 1'b0;
last_cen <= 1'b1... | 7.59203 |
module
//
`timescale 1ns/10ps
module TTL_7430 (
input A, B, C, D, E, F, G, H, // Unit A
output Y
);
not #(0:13:22, 0:8:15) (Y, A & B & C & D & E & F & G & H);
endmodule
| 6.662614 |
module
//
`timescale 1ns/10ps
module TTL_7432 (
input A1, B1, // Unit A
output Y1,
input A2, B2, // Unit B
output Y2,
input A3, B3, // Unit C
output Y3,
input A4, B4, // Unit D
output Y4
);
or #(0:14:22, 0:14:22) (Y1, A1, B1);
or #(0:14:22, 0:14:22) (Y2, A2, B2);
... | 6.662614 |
module ttl_7474 #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Clear_bar,
input wire [BLOCKS-1:0] Preset_bar,
input wire [BLOCKS-1:0] D,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Q_bar
);
//----------... | 6.930349 |
module ttl_7474_pre #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Preset_bar,
input wire [BLOCKS-1:0] D,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Q_bar
);
//----------------------------------------------... | 6.64138 |
module
//
`timescale 1ns/10ps
// #(0:13:22, 0:8:15)
module jkff(input preset, input clear, input clk, input j, input k, output reg q, output qnot);
// #(0:16:25, 0:25:40)
assign qnot = ~q;
always @(clear or preset) begin
if (!clear) begin
q <= #40 1'b0;
end else if (!preset) begin
... | 6.662614 |
module dff (
input d,
input preset,
input clear,
input clk,
output q
);
reg q;
initial q = 0;
always @(posedge clk or posedge clear or posedge preset) begin
if (preset) #7 q <= 1;
else if (clear) #7 q <= 0;
else #6 q <= d;
end
endmodule
| 7.174483 |
module TTL_74LS244 (
input _G1,
input [3:0] A1,
output [3:0] Y1,
input _G2,
input [3:0] A2,
output [3:0] Y2,
input VCC,
input GND
);
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : BUFF
TTL_74LS244_buff buff1 (
._g(_G1),
.a (A1[i]),
... | 7.429127 |
module TTL_74LS373_DFF (
input d,
input _oe,
input le,
output o
);
reg o_hold;
bufif0 (o, o_hold, _oe);
always @(d) if (le) #10 o_hold <= d;
endmodule
| 6.786794 |
module TTL_74LS373 (
input _OE,
output [7:0] O,
input [7:0] I,
input LE,
input VCC,
input GND
);
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : DFF
TTL_74LS373_DFF dff (
.d (I[i]),
._oe(_OE),
.le (LE),
.o (O[i])
);
end... | 8.690078 |
module TTL_74LS93_toggle (
input _t,
input _r,
output o
);
reg o;
always @(negedge _r or negedge _t)
if (_r == 0) o <= 1'b0;
else if (_t == 0) begin
if (o == 1'b0) o <= 1'b1;
else o <= 1'b0;
end
endmodule
| 6.835885 |
module ls74 //not used
(
input n_pre1,
n_pre2,
input n_clr1,
n_clr2,
input clk1,
clk2,
input d1,
d2,
output reg q1,
q2,
output n_q1,
n_q2
);
always @(posedge clk1 or negedge n_pre1 or negedge n_clr1) begin
if (!n_pre1) q1 <= 1;
else if (!n_clr1) q1 <= 0;
e... | 7.057074 |
module ls139 //used
(
input a,
input b,
input n_g,
output [3:0] y
);
assign y = (!n_g && !a && !b) ? 4'b1110:
(!n_g && a && !b) ? 4'b1101:
(!n_g && !a && b) ? 4'b1011:
(!n_g && a && b) ? 4'b0111:
4'b1111;
endmodule
| 6.504395 |
module ttl_74283 #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) //used
(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input c_in,
output [WIDTH-1:0] sum,
output c_out
);
//------------------------------------------------//
reg [WIDTH-1:0] Sum_computed;
reg C_computed;
a... | 7.398786 |
module ls138x ( //used
input [2:0] A,
input nE1,
input nE2,
input E3,
output [7:0] Y
);
reg [7:0] Q;
wire trigger;
assign trigger = !nE1 & !nE2 & E3;
always @(*) begin
if (trigger) begin
case (A)
3'b000: Q[7:0] = 8'b11111110;
3'b001: Q[7:0] = 8'b11111101;
... | 7.281695 |
module ttl_7474 #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [BLOCKS-1:0] n_pre,
input [BLOCKS-1:0] n_clr,
input [BLOCKS-1:0] d,
input [BLOCKS-1:0] clk,
output [BLOCKS-1:0] q,
output [BLOCKS-1:0] n_q
);
//------------------------------------------------//
... | 6.930349 |
module mux4_1 (
input EN_n,
input A,
B,
input D0,
D1,
D2,
D3,
output Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg Y_reg;
assign S = {B, A};
always @(*) begin
if (EN_n) Y_reg = 1'bz;
else
case (S)
2'b00: Y_reg <= D0;
2'b01: Y_reg <= D1;
... | 7.631991 |
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