code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux4_1n (
input EN_n,
input A,
B,
input D0,
D1,
D2,
D3,
output Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg Y_reg;
assign S = {B, A};
always @(*) begin
if (EN_n) Y_reg <= 1'b0;
else
case (S)
2'b00: Y_reg <= D0;
2'b01: Y_reg <= D1... | 7.589537 |
module mux4_2n (
input EN_n,
input A,
B,
input [1:0] D0,
D1,
D2,
D3,
output [1:0] Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg [1:0] Y_reg;
assign S = {B, A};
always @(*) begin
if (EN_n) Y_reg <= 2'b00;
else
case (S)
2'b00: Y_reg <= D0;
2... | 7.911073 |
module mux4_4n (
input EN_n,
input A,
B,
input [3:0] D0,
D1,
D2,
D3,
output [3:0] Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg [3:0] Y_reg;
assign S = {B, A};
always @(*) begin
if (EN_n) Y_reg <= 4'b0000;
else
case (S)
2'b00: Y_reg <= D0;
... | 8.012155 |
module mux4_1x (
input EN_n,
input DIS_n,
input A,
B,
input D0,
D1,
D2,
D3,
output Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg Y_reg;
reg active;
always @(EN_n, DIS_n) begin
if (!EN_n & DIS_n) active = 1;
else if (!DIS_n) active = 0;
end
assign S... | 7.362619 |
module TTT_Decoder (
input [3:0] POS_SW,
input ENABLE,
output wire [8:0] P_EN
);
reg [8:0] temp;
assign P_EN = (ENABLE == 1'b1) ? temp : 9'b0;
always @(*) begin
case (POS_SW)
4'd1: temp <= 9'b000000001; // 0001
4'd2: temp <= 9'b000000010; // 0010
4'd3: temp <= 9'b000000100; /... | 7.141617 |
module TTT_Decoder_TB;
reg [3:0] POS_SW;
reg ENABLE;
wire [8:0] P_EN;
TTT_Decoder UUT (
POS_SW,
ENABLE,
P_EN
);
initial begin
#500 $finish;
end
initial begin
ENABLE = 0;
POS_SW = 0;
#10 POS_SW = 4'd1;
#10 POS_SW = 4'd2;
#10 POS_SW = 4'd3;
#10 POS_SW = 4'... | 6.593233 |
module main; //: root_module
wire w4; //: /sn:0 {0}(161,113)(176,113){1}
wire [7:0] w3; //: /sn:0 {0}(#:161,96)(176,96){1}
wire [7:0] w0; //: /sn:0 {0}(#:161,88)(176,88){1}
wire w1; //: /sn:0 {0}(161,121)(176,121){1}
wire w2; //: /sn:0 {0}(161,105)(176,105){1}
wire w5; //: /sn:0 {0}(161,129)(176,129)... | 6.5859 |
module TTY (
TD,
RD,
RTS,
CTS,
DSR,
DTR
);
input CTS, DSR;
input [7:0] RD;
output [7:0] TD;
output RTS, DTR;
reg _RTS, _DTR;
reg [7:0] data;
initial begin
_RTS = 0;
data = 0;
_DTR = 0;
end
initial $tkg$post("TTY", "%m");
always begin
_DTR = 1'b0;
@(pose... | 7.477042 |
module tt_formal;
// Signals
// -------
// DUT signals
wire [37:0] io_in;
wire [37:0] io_out;
wire [37:0] io_oeb;
wire user_clock2;
wire k_zero;
wire k_one;
// DUT
// ---
tt_top #(
.N_PADS(38),
.G_X (16),
.G_Y (24),
.N_IO (8),
.N_O (... | 6.601277 |
module tt_pg_vdd_2 (
`ifdef USE_POWER_PINS
input wire VGND,
input wire VPWR,
output wire GPWR,
`endif
input wire ctrl
);
endmodule
| 7.231902 |
module tt_prim_buf #(
parameter integer HIGH_DRIVE = 0
) (
input wire a,
output wire z
);
generate
if (HIGH_DRIVE) begin
sky130_fd_sc_hd__buf_8 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b0),
`endif
.A(a),
... | 6.998011 |
module tt_prim_inv #(
parameter integer HIGH_DRIVE = 0
) (
input wire a,
output wire z
);
generate
if (HIGH_DRIVE) begin
sky130_fd_sc_hd__bufinv_8 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b0),
`endif
.A(a),
... | 7.01895 |
module tt_prim_tbuf #(
parameter integer HIGH_DRIVE = 0
) (
input wire a,
input wire tx,
output wire z
);
generate
if (HIGH_DRIVE) begin
sky130_fd_sc_hd__ebufn_8 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB (1'b1),
.VNB (1'b0),
`endif
... | 6.580779 |
module tt_prim_zbuf #(
parameter integer HIGH_DRIVE = 0
) (
input wire a,
input wire e,
output wire z
);
generate
if (HIGH_DRIVE) begin
wire l;
sky130_fd_sc_hd__and2_2 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b... | 6.519112 |
module tt_top_tb;
localparam integer MUX_ID = 12;
localparam integer BLK_ID = 0;
// Signals
// -------
// DUT signals
wire [37:0] io_in;
wire [37:0] io_out;
wire [37:0] io_oeb;
wire user_clock2;
wire k_zero;
wire k_one;
// Control
wire ctrl_sel_rst_n;
reg ... | 6.822897 |
module
*
* Copyright (c) 2023 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_example (
`ifdef TT_WITH_ANALOG
inout wire [7:0] ua, // Analog
`endif
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input w... | 7.306032 |
module for formal connectivity proof
*
* Copyright (c) 2023 Matt Venn <matt@mattvenn.net>
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_formal (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path... | 8.361297 |
module used for DEF template generation
* (can't be fully empty of yosys doesn't generate anything ...)
*
* Copyright (c) 2023 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
(* noblackbox *)
module tt_um_template (
`ifdef TT_WITH_ANALOG
inout wire [7:0] ua, // A... | 6.554276 |
module
*
* Copyright (c) 2023 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_test (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, /... | 7.306032 |
module TubeROM (
input wire [3:0] value,
input wire auxValue,
output reg [6:0] segments
);
always @(*) begin
if (auxValue) begin
case (value)
4'h0: segments = 7'h00; // Empty
4'h1: segments = 7'h73; // P
4'h2: segments = 7'h78; // T
4'h3: segments = 7'h50; //... | 6.804894 |
module is the top module.
* Modification: Simplify memory management.
*
* To AoTuman, my dear cat, thanks for your company.
*/
`timescale 1 ns / 1 ps
module TuMan32_top(
input clk,
input resetn,
// interface for configuring itcm
input conf_r... | 7.105525 |
module */
/* this module contains everything that has to deal with
drawing pixels on the VGA display*/
module tumbler_vga(
clock, // On Board 50 MHz
// Your inputs and outputs here
colour_in,
draw_full,
draw,
x_in,
y_in,
resetn,
// The ports below are for the VGA output. Do not... | 8.02433 |
module TUNE_ADDER (
input clk,
input rst,
input en,
input [31:0] FTW,
input signed [31:0] ACTION,
output [31:0] TUNED_FTW
);
reg [31:0] reg_FTW;
assign TUNED_FTW = reg_FTW;
always @(posedge clk or posedge rst) begin
if (rst) reg_FTW <= 0;
else begin
if (en) reg_FTW <= FTW ... | 7.157137 |
module tuozhan (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out[15:0] = in;
assign out[31:16] = in[15] ? 16'hffff : 16'h0000;
endmodule
| 6.611472 |
module tuple_empty_attr (
output [7:0] out,
output [7:0] out2
);
assign out = 40;
assign out2 = 3;
endmodule
| 7.514762 |
module tuple_packet_analyzer #(
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter NETWORK_PROTOCOL_COMBINATIONS = 4,
parameter MAX_HDR_WORDS = 6,
parameter DIVISION_FACTOR = 2,
parameter PRTCL_ID_WIDTH ... | 7.13646 |
module turbosound (
input wire clk,
input wire clkay,
input wire reset_n,
input wire disable_ay,
input wire disable_turboay,
input wire bdir,
input wire bc1,
input wire [7:0] din,
output wire [7:0] dout,
output wire oe_n,
output wire [7:0] audio_out_ay1,
output wire [7:0]... | 6.882167 |
module ture_dp_sram ( /*autoarg*/
// Outputs
douta,
doutb,
// Inputs
clka,
clkb,
csen_n,
dina,
addra,
wrena_n,
rdena_n,
dinb,
addrb,
wrenb_n,
rdenb_n
);
parameter ADDR_WIDTH = 4;
parameter DATA_WIDTH = 8;
input clka;
input clkb;
input csen_n;
//Po... | 7.104508 |
module BUF(A, Y);
input A;
output Y = A;
endmodule
| 6.918193 |
module NOT(A, Y);
input A;
output Y = ~A;
endmodule
| 7.323172 |
module NAND(A, B, Y);
input A, B;
output Y = ~(A & B);
endmodule
| 7.167084 |
module AND3(A, B, C, Y);
input A, B, C;
output Y = A & B & C;
endmodule
| 6.909346 |
module NOR(A, B, Y);
input A, B;
output Y = ~(A | B);
endmodule
| 7.436332 |
module OR(A, B, Y);
input A, B;
output Y = A | B;
endmodule
| 7.133681 |
module OR3(A, B, C, Y);
input A, B, C;
output Y = A | B | C;
endmodule
| 7.609427 |
module XOR(A, B, Y);
input A, B;
output Y = A ^ B;
endmodule
| 7.44551 |
module XNOR(A, B, Y);
input A, B;
output Y = ~(A ^ B);
endmodule
| 7.191694 |
module FA(A, B, CI, CO, Y);
input A, B, CI;
output CO = (A & B)|(B & CI)|(CI & A);
output Y = A^B^CI;
endmodule
| 6.565544 |
module DFF (
C,
D,
Q
);
input C, E, D;
output reg Q;
always @(posedge C) Q <= D;
endmodule
| 7.813248 |
module turn7seg (
input en,
input [3:0] num,
output reg [6:0] seg
);
always @*
if (en) begin
case (num)
4'd0: seg = 7'b1000000;
4'd1: seg = 7'b1111001;
4'd2: seg = 7'b0100100;
4'd3: seg = 7'b0110000;
4'd4: seg = 7'b0011001;
4'd5: seg = 7'b0010010;
... | 6.75735 |
module TURNER_LL #(
parameter BITS = 4
) (
input [BITS-1:0] IN,
input Com,
output [BITS-1:0] OUT
);
wire [BITS-1:0] bus_in, bus_out;
assign bus_in = ~IN;
ADDER_LL_CLA#(
.BITS(BITS)
) (
.A(bus_in), .B(1'b1), .S(bus_out)
);
assign OUT = Com ? bus_out : IN;
assign Min = IN[B... | 7.636508 |
module has inputs a clock, a left push button and a right
// push button. Its outputs are eight LED signals. Initially,
// all LEDs are off. When the left button is strobed, one LED
// walks from right to left (LSB to MSB) and then all LEDs go
// off and stay off. When the right button is strobed, one LED
// walks... | 6.684547 |
module turn_around_move (
clk,
rst,
output_speed,
random_angle,
motion_command,
enable,
done_spin
);
//
//Inputs
//
input clk;
input rst;
input enable;
input done_spin;
input [9:0] random_angle;
//
//...
//Outputs
//
output [2:0] output_speed;
output [9:0] motion_... | 9.209262 |
module spiral_move_tb;
reg clk, rst;
reg enable;
reg done_spin;
reg [9:0] random_angle;
wire [2:0] output_speed;
wire [9:0] motion_command;
turn_around_move TA (
.clk(clk),
.rst(rst),
.enable(enable),
.random_angle(random_angle),
.done_spin(done_spin),
.output_spee... | 6.797452 |
module turn_lights_control (
input clk,
input reset,
input Left,
input Right,
input Hazard,
output reg [0:7] LED
);
wire slow_clk;
clkdiv c1 (
clk,
slow_clk
);
parameter IDLE = 8'b00000000,
L4 = 8'b11110000,
L3 = 8'b01110000,
L2 = 8'b00110000,
... | 6.696489 |
module clkdiv (
clk,
clk_out
);
input clk;
output clk_out;
reg [22:0] COUNT;
assign clk_out = COUNT[22];
always @(posedge clk) begin
COUNT = COUNT + 1;
end
endmodule
| 7.689254 |
module turning_sim ();
reg l_sim, r_sim, e_sim, clk_sim, rst_sim;
wire l1, l2, l3, r1, r2, r3;
Turning a1 (
l1,
l2,
l3,
r1,
r2,
r3,
l_sim,
r_sim,
e_sim,
clk_sim,
rst_sim
);
always begin
clk_sim <= 0;
#20;
clk_sim <= 1;
#20;
... | 7.126294 |
module turn_tracker (
enable,
reset,
q
);
input enable, reset;
output reg [1:0] q = 2'b01;
always @(posedge enable or posedge reset) begin
if (reset) q <= 2'b01;
else if (q == 2'b01) q <= 2'b10;
else if (q == 2'b10) q <= 2'b01;
end
endmodule
| 7.155752 |
module Turtle(
input clk,
input clk_walk_anim,
input rstn,
input initial_show,
input collapsion_impulse,
input press_impulse,
output reg [5:0] id,
output reg oriental, // 0: right; 1: left
output [10:0] w,
output [10:0] h,
output reg shell,
output reg shell_anim
);
parameter turtlel1 = 32;
... | 7.722957 |
module tuser_m3_for_arty_a7_axis_broadcaster_0_0 #(
parameter C_S_AXIS_TUSER_WIDTH = 8,
parameter C_M_AXIS_TUSER_WIDTH = 8
) (
input wire [C_S_AXIS_TUSER_WIDTH-1:0] tuser,
output wire [C_M_AXIS_TUSER_WIDTH-1:0] tuser_out
);
assign tuser_out = {tuser[0:0], tuser[0:0]};
endmodule
| 7.711162 |
module tuser_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TUSER_WIDTH = 1,
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TUSER_WIDTH = 1
) (
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER... | 7.711162 |
module tuser_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TUSER_WIDTH = 1,
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TUSER_WIDTH = 1
) (
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER... | 7.711162 |
module source ( /*AUTOARG*/
// Outputs
flit,
valid,
// Inputs
clk,
rst,
ready
);
parameter FLIT_DATA_WIDTH = 32;
localparam FLIT_TYPE_WIDTH = 2;
localparam FLIT_WIDTH = FLIT_DATA_WIDTH + FLIT_TYPE_WIDTH;
input clk;
input rst;
output reg [FLIT_WIDTH-1:0] flit;
output reg val... | 7.81398 |
module sink ( /*AUTOARG*/
// Outputs
ready,
// Inputs
clk,
rst,
flit,
valid
);
parameter FLIT_DATA_WIDTH = 32;
localparam FLIT_TYPE_WIDTH = 2;
localparam FLIT_WIDTH = FLIT_DATA_WIDTH + FLIT_TYPE_WIDTH;
input clk;
input rst;
input [FLIT_WIDTH-1:0] flit;
input valid;
output... | 7.280857 |
modules
module tutorial_01(input clk, input rst);
localparam FLIT_WIDTH = 34;
wire [FLIT_WIDTH:0] flit;
wire valid;
wire ready;
source
u_source(/*AUTOINST*/
// Outputs
.flit (flit[FLIT_WIDTH-1:0]),
.valid ... | 7.473142 |
module source ( /*AUTOARG*/
// Outputs
flit,
valid,
// Inputs
clk,
rst,
ready
);
parameter FLIT_DATA_WIDTH = 32;
localparam FLIT_TYPE_WIDTH = 2;
localparam FLIT_WIDTH = FLIT_DATA_WIDTH + FLIT_TYPE_WIDTH;
parameter VCHANNELS = 2;
input clk;
input rst;
output reg [FLIT_WIDTH... | 7.81398 |
module sink ( /*AUTOARG*/
// Outputs
ready,
// Inputs
clk,
rst,
flit,
valid
);
parameter FLIT_DATA_WIDTH = 32;
localparam FLIT_TYPE_WIDTH = 2;
localparam FLIT_WIDTH = FLIT_DATA_WIDTH + FLIT_TYPE_WIDTH;
parameter VCHANNELS = 2;
input clk;
input rst;
input [FLIT_WIDTH-1:0] f... | 7.280857 |
modules
module tutorial_02(input clk, input rst);
localparam FLIT_WIDTH = 34;
localparam VCHANNELS = 2;
wire [FLIT_WIDTH:0] flit;
wire [VCHANNELS-1:0] valid;
wire [VCHANNELS-1:0] ready;
source
u_source(/*AUTOINST*/
// Outputs
.flit (flit[FLIT_WI... | 7.473142 |
module two_bit_pred(
input clock, reset, taken, transition,
output prediction);
logic [1:0] state;
loggic [1:0] next_state;
assign prediction = state[1];
always_comb begin
case(state)
2'b01, 2'b10 : next_state = taken ? 2'b11 : 2'b00;
2'b00 : next_state = ... | 6.84792 |
module two_bit_pred(
input clock, reset, taken, transition,
output prediction);
logic loop1, loop2;
logic [1:0] state;
logic [1:0] next_state;
assign prediction = state[1];
assign loop1 = (taken & loop2) ? 0 : 1;
assign loop2 = (taken & loop1) ? 1 : 0;
always_comb begi... | 6.84792 |
module testbench;
logic clock, reset, taken, transition;
logic [15:0] bigsignal;
logic prediction;
two_bit_pred tbp(.clock(clock), .reset(reset), .taken(taekn),
.transition(transition), .prediction(prediction));
always begin
#5;
clock=~clock;
end
init... | 7.015571 |
module gates (
a,
b,
q,
r
);
input a, b;
output q, r;
assign q = a & b;
assign r = a | b;
endmodule
| 7.748371 |
module mfa (
P,
Q,
R,
C,
S
);
input P;
input Q;
input R;
output C;
output S;
assign S = (P & Q & R) | (~P & ~Q & R) | (~P & Q & ~R) | (P & ~Q & ~R);
assign C = (P & Q) | (P & R) | (Q & R);
endmodule
| 7.242357 |
module tv80_reg ( /*AUTOARG*/
// Outputs
DOBH,
DOAL,
DOCL,
DOBL,
DOCH,
DOAH,
// Inputs
AddrC,
AddrA,
AddrB,
DIH,
DIL,
clk,
CEN,
WEH,
WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output... | 6.903785 |
module tvmix_calc (
clk,
palentry,
cc_i,
cc_q
);
//initial begin
input clk;
input reg [32-1:0] palentry;
input reg signed [16-1:0] cc_i;
input reg signed [16-1:0] cc_q;
always @(posedge clk) begin
reg [16-1:0] pal_luma;
reg signed [8-1:0] pal_imix;
reg signed [8-1:0] pal_qmix;
... | 6.822592 |
module TV_FYP (
///////////// CLOCK /////////////
input CLOCK_50,
///////////// HDMI //////////////
inout HDMI_I2C_SCL,
inout HDMI_I2C_SDA,
inout HDMI_I2S,
inout HDMI_LRCLK,
inout HDMI_MCLK,
inout HDMI_SCLK,
output HDMI_TX_C... | 6.602318 |
module tv_gen (
clk,
rst,
in0,
in1
); //Testvector Generator, Top Module
input clk; //CLOCK
input rst; //Reset Signal
output reg in0, in1; //INPUT SIGNALS for ""Test_Unit""
//STATES begin
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
//STA... | 7.530758 |
module clk_counter (
clk,
rst,
step,
out
); //clk divider, Sub Module
input clk, rst;
input [9:0] step; //Clock Delay Parameter
output reg out; //New Clock OUTPUT
reg [9:0] counter;
always @(posedge clk, negedge rst) begin
if (!rst) begin
//RESET Condition
counter <= 8'b1;... | 7.09339 |
module twelve (
MR,
EN,
CLK,
Q,
CO
);
input wire MR, CLK, EN;
output reg [3:0] Q;
output CO;
always @(posedge CLK or negedge MR) begin
if (~MR) Q <= 4'b0000;
else if (EN) begin
if (Q == 4'b0000) Q <= 4'b1001;
else Q <= Q - 1'b1;
end
end
assign CO = (~Q[0]) & (~Q[1... | 7.128572 |
module twenty_to_eight #(
parameter WORD_LEN = 66
) (
input clk,
arst,
input [20*WORD_LEN-1:0] din,
input din_valid,
output din_ready,
output reg [8*WORD_LEN-1:0] dout,
input dout_ready,
output reg dout_valid
);
// Possible states :
// 0: holding 0, accept 20, 8 out
// 1... | 7.24617 |
module twenty_to_five #(
parameter WORD_LEN = 66
) (
input clk,
arst,
input [20*WORD_LEN-1:0] din,
input din_valid,
output din_ready,
output [5*WORD_LEN-1:0] dout,
input dout_ready,
output dout_valid
);
reg [2:0] holding; // holding 0..4 blocks of 5 words
reg [20*WORD_LEN-1:0... | 7.075203 |
module twiddle_rom (
clk,
rst,
addr,
data_read,
rd_en
);
parameter ADDR_WIDTH = 2;
parameter ROM_WIDTH = 81; //3*8+6*9
input clk, rst, rd_en;
input [ADDR_WIDTH-1:0] addr;
output reg [ROM_WIDTH-1:0] data_read;
reg [ROM_WIDTH-1:0] rom[3:0];
always @(posedge clk) begin
if (rst) da... | 7.090187 |
module twiddle64_0 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.511271 |
module twiddle64_1 #(
parameter DATA_WIDTH = 14
) (
input signed [DATA_WIDTH-1:0] din_real,
input signed [DATA_WIDTH-1:0] din_imag,
output signed [DATA_WIDTH-1:0] dout_rere,
output signed [DATA_WIDTH-1:0] dout_imim,
output signed [DATA_WIDTH-1:0] dout_reim,
output signed [DATA_WIDTH-1:0] d... | 6.918234 |
module twiddle64_2 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.168156 |
module twiddle64_3 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.472133 |
module twiddle64_4 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.362297 |
module twiddle64_5 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.181315 |
module twiddle64_6 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 6.972645 |
module twiddle64_7 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.309479 |
module twiddle64_8 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 6.980159 |
module twiddle8_multiplier #(
parameter DATA_WIDTH_IN = 10,
parameter DATA_WIDTH_OUT = DATA_WIDTH_IN + 1,
parameter TWIDDLE_RANK = 8
) (
input wire [ 1:0] twiddle,
input wire signed [ DATA_WIDTH_IN-1:0] din_real,
input wire signed [ DATA_WIDTH_IN-1:0] din_imag,
out... | 6.6709 |
module twiddle_45degree #(
parameter DATA_WIDTH = 10
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_real,
output wire signed [DATA_WIDTH-1:0] dout_imag
);
wire signed [DATA_WIDTH-1:0] tmp1_real;
wire signe... | 7.408505 |
module TwiddleConvert4 #(
parameter LOG_N = 6, // Address Bit Length
parameter WIDTH = 16, // Data Bit Length
parameter TW_FF = 1, // Use Twiddle Output Register
parameter TC_FF = 1 // Use Output Register
) (
input clock, // Master Clock
input [LOG_N-1:0] tw_addr, ... | 6.684026 |
module TwiddleConvert8 #(
parameter LOG_N = 6, // Address Bit Length
parameter WIDTH = 16, // Data Bit Length
parameter TW_FF = 1, // Use Twiddle Output Register
parameter TC_FF = 1 // Use Output Register
) (
input clock, // Master Clock
input [LOG_N-1:0] tw_addr, ... | 6.684026 |
module twiddlefactors (
input wire clk,
input wire [ 3:0] addr,
input wire addr_nd,
output reg signed [23:0] tf_out
);
always @(posedge clk) begin
if (addr_nd) begin
case (addr)
4'd0: tf_out <= {12'sd1024, -12'sd0};
4'd1: tf_out <= {12'sd... | 7.097069 |
module Twiddlegen #(
parameter length = 32,
parameter R = 5,
parameter N = 32,
parameter TWIDDLEFILE = "TWIDDLE.txt"
) (
input i_clk,
input i_rst,
input [R-2:0] i_twiddle_exponent,
output reg [length-1:0] o_twiddle_cos,
output reg [length-1:0] o_twiddle_sin
);
reg [2*length-1:0] TW... | 8.545007 |
module twiddleROM #(
parameter N = 32,
word_size = 16,
memory_file = "/home/saviour/study/fft_hdl/data/out.real"
) (
input wire [ $clog2(N)-1:0] read_address,
output wire [word_size*2-1:0] twiddle
// output reg [word_size-1: 0] twiddle_im
);
//CALLING THEM TWIDDLE FACTORS IS NOT ACCURATE
... | 7.230195 |
module twiddle_LUT (
input clk,
input rst,
input [3:0] twiddle_num,
output reg [15:0] twiddle_val_real,
output reg [15:0] twiddle_val_imag
);
always @(posedge clk, posedge rst) begin
if (rst) begin
twiddle_val_real <= 16'b0;
twiddle_val_imag <= 16'b0;
end else begin
case... | 6.840287 |
module twiddle_mod #(
parameter division = 16,
parameter fft_length = 16,
parameter ff_in_en = 0,
parameter ff_out_en = 0,
parameter dsp_ff_num = 0
) (
input sys_clk,
input sys_nrst,
input sys_en,
output [16 : 0] tw_fac_r,
output [16 : 0] tw_fac_i,
output cordi... | 8.792314 |
module twiddle_rom #(
parameter FILE_REAL = "hdl/twiddle_real.list",
parameter FILE_IMAJ = "hdl/twiddle_imag.list",
parameter addr_w = 7,
parameter data_w = 8
) (
input wire clk,
input wire [addr_w-1:0] addr,
output reg [data_w-1:0] dout_real,
output reg [data_w-1:... | 8.00741 |
module twiddle_rom_imag #(
parameter N = 16
) (
input clk,
input rst,
output reg [N-1:0] reg0_i,
output reg [N-1:0] reg1_i,
output reg [N-1:0] reg2_i,
output reg [N-1:0] reg3_i,
output reg [N-1:0] reg4_i,
output reg [N-1:0] reg5_i,
output reg [N-1:0] reg6_i,
output reg ... | 8.290644 |
module twiddle_rom_real #(
parameter N = 16
) (
input clk,
input rst,
output reg [N-1:0] reg0_r,
output reg [N-1:0] reg1_r,
output reg [N-1:0] reg2_r,
output reg [N-1:0] reg3_r,
output reg [N-1:0] reg4_r,
output reg [N-1:0] reg5_r,
output reg [N-1:0] reg... | 7.793548 |
module: twiddle_LUT
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module twiddle_tb;
// Inputs
reg clk;
reg rst;
reg [3:0] twiddle_num;
// Outputs
wire [15:0] twiddle_val_real;
w... | 7.806959 |
module twi_core (
input clk,
input rst,
input wr, //we
input [7:0] data_in, //dat1
input [7:0] wr_addr, //adr1
output [7:0] i2cr,
output [7:0] i2rd,
output twi_scl_o,
input twi_sda_i,
output twi_sda_oen
);
parameter T... | 7.255932 |
module twmux (
i0,
i1,
out,
s
);
parameter n = 16;
input [n-1:0] i0, i1;
input s;
output reg [n-1:0] out;
always @(s) begin
out = s ? i1 : i0;
end
endmodule
| 7.277553 |
module game (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // ... | 8.621551 |
module control (
input clk,
resetn,
go,
output reg ld_top,
ld_bottom,
ld_left,
ld_right,
writeEn,
ld_color,
enable,
output hold
);
wire delay_enable;
delay_counter dc0 (
.clk(clk),
.resetn(resetn),
.enable(writeEn),
.delay_enable(delay_enable)
)... | 7.715617 |
module border_datapath (
input clk,
enable,
resetn,
ld_top,
ld_bottom,
ld_left,
ld_right,
input [2:0] color_in,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
reg [7:0] x;
reg [6:0] y;
reg [2:0] color;
always @(posedge clk) begin
if (!resetn)... | 6.538823 |
module delay_counter (
input clk,
resetn,
enable,
output delay_enable
);
reg [19:0] count;
always @(posedge clk) begin
if (!resetn) count <= 20'd833334;
else if (enable) begin
if (count == 20'd0) count <= 20'd833334;
else count <= count - 1'b1;
end
end
assign delay_enab... | 6.853164 |
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