code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TLWidthWidget_boom (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 3:0] auto_in_a_bits_size,
input [ 4:0] auto_in_a_bits_source,
input [27:0] auto_in_a_bits_address,
input [ 7:0] a... | 6.593259 |
module FixedClockBroadcast_2_boom (
input auto_in_clock,
input auto_in_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_... | 6.914809 |
module FixedClockBroadcast_3_boom (
input auto_in_clock,
input auto_in_reset,
output auto_out_4_clock,
output auto_out_4_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_4_clock = auto_in_clock; // @[Nodes.s... | 6.914809 |
module TLWidthWidget_5_boom (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 2:0] auto_in_a_bits_size,
input [ 4:0] auto_in_a_bits_source,
input [26:0] auto_in_a_bits_address,
input [ 7:0]... | 6.593259 |
module FixedClockBroadcast_5_boom (
input auto_in_clock,
input auto_in_reset,
output auto_out_clock,
output auto_out_reset
);
assign auto_out_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala ... | 6.914809 |
module SourceE_boom (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [2:0] io_req_bits_sink,
output io_e_valid,
output [2:0] io_e_bits_sink
);
wire io_e_q_clock; // @[Decoupled.scala 296:21]
wire io_e_q_reset; // @[Decoupled.s... | 6.509711 |
module SourceX_boom (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input io_x_ready,
output io_x_valid
);
wire io_x_q_clock; // @[Decoupled.scala 296:21]
wire io_x_q_reset; // @[Decoupled.scala 296:21]
wire io_x_q_io_enq_ready; // @[Decoupled.scala 296:21]
wi... | 6.636411 |
module SinkE_boom (
output io_resp_valid,
output [2:0] io_resp_bits_sink,
input io_e_valid,
input [2:0] io_e_bits_sink
);
assign io_resp_valid = io_e_valid; // @[SinkE.scala 44:19]
assign io_resp_bits_sink = io_e_bits_sink; // @[SinkE.scala 45:23]
endmodule
| 7.460346 |
module TLWidthWidget_9_boom (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_size,
input [ 3:0] auto_in_a_bits_source,
input [31:0] auto_in_a_bits_address,
input [ 7:0] auto_in_a_bits_mask,
input [63:0] ... | 6.593259 |
module BundleBridgeNexus_6_boom (
input auto_in,
output auto_out
);
assign auto_out = auto_in; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.861693 |
module BundleBridgeNexus_13_boom (
input auto_in_0_valid,
input [39:0] auto_in_0_iaddr,
input [31:0] auto_in_0_insn,
input [ 2:0] auto_in_0_priv,
input auto_in_0_exception,
input auto_in_0_interrupt,
input [63:0] auto_in_0_cause,
input [39:0] auto_in_0_tval,
... | 6.861693 |
module Arbiter_3_boom (
output io_in_0_ready,
input io_in_0_valid,
input [ 5:0] io_in_0_bits_idx,
input [ 3:0] io_in_0_bits_way_en,
input [19:0] io_in_0_bits_tag,
output io_in_1_ready,
input io_in_1_valid,
input [ 5:0] io_in_1_bits_idx,
input [ 3:0]... | 6.688126 |
module Arbiter_4_boom (
output io_in_0_ready,
input io_in_0_valid,
input [19:0] io_in_0_bits_tag,
input [ 5:0] io_in_0_bits_idx,
input [ 2:0] io_in_0_bits_param,
input [ 3:0] io_in_0_bits_way_en,
input io_in_0_bits_voluntary,
output io_in_1_ready,
in... | 6.582466 |
module Arbiter_14_boom (
output io_in_0_ready,
input io_in_0_valid,
input [31:0] io_in_0_bits_address,
output io_in_1_ready,
input io_in_1_valid,
input [31:0] io_in_1_bits_address,
input io_out_ready,
output io_out_valid,
output [31:0] i... | 7.091367 |
module AMOALU_boom (
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 65:33]
wire add = io_cmd ==... | 8.245739 |
module OptimizationBarrier_boom (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae,
input io_x_sx,
input io_x_px,
output [19:0] io_y_ppn,
output io_y_u,
output io_y_ae,
output io_y_sx,
output io_y_px
);
assign io_y_... | 7.587549 |
module RoundRawFNToRecFN_boom (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output ... | 6.992477 |
module FMADecoder_boom (
input [6:0] io_uopc,
output [1:0] io_cmd
);
wire [6:0] _decoder_T = io_uopc & 7'h27; // @[Decode.scala 14:65]
wire _decoder_T_1 = _decoder_T == 7'h0; // @[Decode.scala 14:121]
wire [6:0] _decoder_T_2 = io_uopc & 7'h12; // @[Decode.scala 14:65]
wire _decoder_T_3 = _decoder_T_... | 7.083706 |
module RoundRawFNToRecFN_1_boom (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
outpu... | 6.992477 |
module CompareRecFN_boom (
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [ 4:0] io_exceptionFlags
);
wire [11:0] rawA_exp = io_a[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawA_isZero = rawA_exp[11:9] == 3'h0; // ... | 6.945474 |
module UOPCodeFDivDecoder_boom (
input [6:0] io_uopc,
output [1:0] io_sigs_typeTagIn,
output io_sigs_div,
output io_sigs_sqrt
);
wire [6:0] _decoder_T_2 = io_uopc & 7'ha; // @[Decode.scala 14:65]
wire _decoder_T_3 = _decoder_T_2 == 7'h0; // @[Decode.scala 14:121]
wire [6:0] _decoder... | 7.175893 |
module RoundAnyRawFNToRecFN_5_boom (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [24:0] io_in_sig,
output [64:0] io_out
);
wire [11:0] _GEN_0 = {{2{io_in_sExp[9... | 7.169444 |
module RoundRawFNToRecFN_2_boom (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
... | 6.992477 |
module OptimizationBarrier_39_boom (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_pr,
input io_x_pal,
input io_x_paa,
input ... | 7.587549 |
module OptimizationBarrier_60_boom (
input [2:0] io_x,
output [2:0] io_y
);
assign io_y = io_x; // @[package.scala 263:12]
endmodule
| 7.587549 |
module OptimizationBarrier_61_boom (
input [53:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [53:0] io_y_ppn,
output i... | 7.587549 |
module HellaCacheArbiter_boom (
output io_requestor_0_req_ready,
input io_requestor_0_req_valid,
input [39:0] io_requestor_0_req_bits_addr,
input io_requestor_0_s1_kill,
output io_requestor_0_s2_nack,
output io_requestor_0_resp_valid,
output [63:0] io_re... | 6.932065 |
module SynchronizerShiftReg_w1_d3_boom (
input clock,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
NonSyncResetSynchronizerPrimitiveShiftReg_d3_boom output_cha... | 6.820992 |
module IntSyncAsyncCrossingSink_1_boom (
input clock,
input auto_in_sync_0,
output auto_out_0
);
wire chain_clock; // @[ShiftReg.scala 45:23]
wire chain_io_d; // @[ShiftReg.scala 45:23]
wire chain_io_q; // @[ShiftReg.scala 45:23]
SynchronizerShiftReg_w1_d3_boom chain ( // @[ShiftReg.scala 45:2... | 6.70996 |
module AsyncResetRegVec_w1_i0_boom (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedg... | 6.68936 |
module IntSyncCrossingSource_1_boom (
input clock,
input reset,
input auto_in_0,
output auto_out_sync_0
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire reg__io_d; // @[AsyncResetReg.scala 89:21]
wire reg__io_q; // @[AsyncResetReg.s... | 6.689384 |
module IntSyncCrossingSource_4_boom (
input auto_in_0,
output auto_out_sync_0
);
assign auto_out_sync_0 = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.689384 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_boom (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sync_1; //... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_boom (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // ... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1_boom (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; /... | 6.605499 |
module AsyncValidSync_boom (
input io_in,
output io_out,
input clock,
input reset
);
wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
wire io_out_source_vali... | 6.70336 |
module BundleBridgeNexus_16_boom (
output auto_out
);
wire outputs_0 = 1'h0; // @[HasTiles.scala 162:32]
assign auto_out = outputs_0; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
endmodule
| 6.861693 |
module AsyncResetRegVec_w2_i0_boom (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
al... | 6.68936 |
module IntSyncCrossingSource_5_boom (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
output auto_out_sync_0,
output auto_out_sync_1
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_d; // @[AsyncReset... | 6.689384 |
module AsyncResetRegVec_w8_i0_boom (
input clock,
input reset,
input [7:0] io_d,
output [7:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [7:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
al... | 6.68936 |
module IntSyncCrossingSource_8_boom (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
input auto_in_2,
input auto_in_3,
input auto_in_4,
input auto_in_5,
input auto_in_6,
input auto_in_7,
output auto_out_sync_0,
output auto_out_sync_1,
output aut... | 6.689384 |
module AsyncResetRegVec_w1_i0_6_boom (
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(pos... | 6.68936 |
module ghist_0_boom (
input [ 4:0] R0_addr,
input R0_clk,
output [63:0] R0_data_old_history,
output R0_data_current_saw_branch_not_taken,
output R0_data_new_saw_branch_not_taken,
output R0_data_new_saw_branch_taken,
output [ 4:0] R0_data_ras_idx,
input [ 4:... | 6.959468 |
module IntXbar (
input auto_int_in_0,
output auto_int_out_0
);
assign auto_int_out_0 = auto_int_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.794458 |
module FixedClockBroadcast (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 12... | 6.914809 |
module TLWidthWidget (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 3:0] auto_in_a_bits_size,
input [ 1:0] auto_in_a_bits_source,
input [30:0] auto_in_a_bits_address,
input [ 7:0] auto_i... | 6.593259 |
module TLBuffer_4 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 2:0] auto_in_a_bits_size,
input [ 2:0] auto_in_a_bits_source,
input [20:0] auto_in_a_bits_address,
input [ 7:0] auto_in_a... | 6.588838 |
module FixedClockBroadcast_2 (
input auto_in_clock,
input auto_in_reset,
output auto_out_clock,
output auto_out_reset
);
assign auto_out_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:1... | 6.914809 |
module TLWidthWidget_4 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 2:0] auto_in_a_bits_size,
input [ 2:0] auto_in_a_bits_source,
input [30:0] auto_in_a_bits_address,
input [ 7:0] auto... | 6.593259 |
module TLWidthWidget_7 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 2:0] auto_in_a_bits_size,
input [ 3:0] auto_in_a_bits_source,
input [31:0] auto_in_a_bits_address,
input [ 3:0] auto... | 6.593259 |
module BroadcastFilter (
output io_request_ready,
input io_request_valid,
input [ 1:0] io_request_bits_mshr,
input [31:0] io_request_bits_address,
input io_request_bits_allocOH,
input io_request_bits_needT,
input io_response_ready,
output i... | 9.561359 |
module BundleBridgeNexus_6 (
input auto_in,
output auto_out
);
assign auto_out = auto_in; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.861693 |
module OptimizationBarrier (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_px,
input io_x_pr,
input io_x_ppp,
input io... | 7.587549 |
module AMOALU (
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 65:33]
wire add = io_cmd == 5'h8... | 8.467919 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0... | 6.992477 |
module CompareRecFN (
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [ 4:0] io_exceptionFlags
);
wire [11:0] rawA_exp = io_a[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawA_isZero = rawA_exp[11:9] == 3'h0; // @[raw... | 6.787862 |
module RecFNToRecFN (
input [64:0] io_in,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRec... | 6.761906 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4... | 6.992477 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module RoundRawFNToRecFN_3 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module OptimizationBarrier_117 (
input [2:0] io_x,
output [2:0] io_y
);
assign io_y = io_x; // @[package.scala 263:12]
endmodule
| 7.587549 |
module OptimizationBarrier_118 (
input [53:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [53:0] io_y_ppn,
output io_y_... | 7.587549 |
module BreakpointUnit (
input io_status_debug,
input [ 1:0] io_status_prv,
input io_bp_0_control_action,
input [ 1:0] io_bp_0_control_tmatch,
input io_bp_0_control_m,
input io_bp_0_control_s,
input io_bp_0_control_u,
input io_bp_0_control... | 8.021329 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge res... | 6.68936 |
module IntSyncCrossingSource_1 (
input clock,
input reset,
input auto_in_0,
output auto_out_sync_0
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire reg__io_d; // @[AsyncResetReg.scala 89:21]
wire reg__io_q; // @[AsyncResetReg.scala ... | 6.689384 |
module PLICFanIn (
input io_prio_0,
input io_ip,
output io_dev,
output io_max
);
wire [1:0] effectivePriority_1 = {io_ip, io_prio_0}; // @[Cat.scala 30:58]
wire _T = 2'h2 >= effectivePriority_1; // @[Plic.scala 345:20]
wire [1:0] maxPri = _T ? 2'h2 : effectivePriority_1; // @[Misc.scala 34:9]... | 8.419901 |
module BundleBridgeNexus_15 (
output auto_out
);
wire outputs_0 = 1'h0; // @[HasTiles.scala 162:32]
assign auto_out = outputs_0; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
endmodule
| 6.861693 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always ... | 6.68936 |
module IntSyncCrossingSource_4 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
output auto_out_sync_0,
output auto_out_sync_1
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_d; // @[AsyncResetReg.s... | 6.689384 |
module AsyncResetRegVec_w1_i0_6 (
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge ... | 6.68936 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 (
input clock,
input reset,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sync_1; // @[SynchronizerReg.sca... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 outp... | 6.605499 |
module FixedClockBroadcast_7 (
input auto_in_reset,
output auto_out_reset
);
assign auto_out_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.914809 |
module oai21x2_lvt (
Y,
A0,
A1,
B0
);
output Y;
input A0;
input A1;
input B0;
reg Y;
always @(A0 or A1 or B0)
if (B0 == 1'b0) begin
Y = 1'b1;
end else begin
Y = !(A0 | A1);
end
endmodule
| 6.690466 |
module anor21_lvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C) assign Y = ~(C | (B * A));
endmodule
| 6.881661 |
module nor2_lvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.594783 |
module mux2x1_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.134428 |
module mux2x1_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.134428 |
module nand3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.175282 |
module nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.113032 |
module carry_logic_nand (
cout,
a,
a_bar,
b,
b_bar,
carry_in,
vg_en
);
output cout;
input a;
input a_bar;
input b;
input b_bar;
input carry_in;
input vg_en;
endmodule
| 6.500349 |
module inv_lvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.525807 |
module clut4vic (
lut4,
lut4vic,
cbit,
in0,
in0b,
in1,
in1b,
in2,
in2b,
in3,
in3b
);
output lut4;
output lut4vic;
input [15:0] cbit;
input in0;
input in0b;
input in1;
input in1b;
input in2;
input in2b;
input in3;
input in3b;
endmodule
| 7.068048 |
module nand2_lvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.305138 |
module inv_hvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 8.281121 |
module exor2_25 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = (A & !B) | (!A & B);
endmodule
| 8.63069 |
module anor21_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C) assign Y = ~(C | (B * A));
endmodule
| 6.919113 |
module nand4_hvt (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 8.931189 |
module nor4_hvt (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A | B | C | D);
endmodule
| 7.961286 |
module exor2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = (A & !B) | (!A & B);
endmodule
| 9.259946 |
module mux2_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.126877 |
module nand2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.392288 |
module nand3_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.69723 |
module nor2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.725239 |
module nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.297456 |
module inv (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.1601 |
module nor3_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.780348 |
module inv_hvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 8.281121 |
module ml_testdec_columns (
bl,
vdd_drv,
dec_det_even_25,
dec_det_odd_25
);
inout vdd_drv;
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
// List of primary ali... | 6.949738 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
supply0 vss_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
// List of primary aliased buses
nvcm_cell_2x1 m0 (
.wp(wp[0]),
.wr(w... | 6.933495 |
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