code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ActUnit_Connections_OutBlocking_spec_StreamType_Connections_SYN_PORT_Push (
this_val,
this_rdy,
this_msg,
m_data_data_rsc_dat,
m_logical_addr_rsc_dat,
ccs_ccore_start_rsc_dat,
ccs_ccore_done_sync_vld,
ccs_MIO_clk,
ccs_MIO_arst
);
output this_val;
input this_rdy;
output [... | 6.728673 |
module ActUnit_Connections_OutBlockingless_boolcomma_Connections_SYN_PORTgreater_Push_ccs_in_v1 (
idat,
dat
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] idat;
input [width-1:0] dat;
wire [width-1:0] idat;
assign idat = dat;
endmodule
| 6.728673 |
module ActUnit_Connections_OutBlockingless_boolcomma_Connections_SYN_PORTgreater_Push_ccs_sync_out_vld_v1 (
vld,
ivld
);
parameter integer rscid = 1;
input ivld;
output vld;
wire vld;
assign vld = ivld;
endmodule
| 6.728673 |
module ActUnit_Connections_OutBlockingless_boolcomma_Connections_SYN_PORTgreater_Push_Connections_OutBlocking_bool_Connections_SYN_PORT_Push_core
(
this_val,
this_rdy,
this_msg,
ccs_ccore_start_rsc_dat,
ccs_ccore_done_sync_vld,
ccs_MIO_clk,
ccs_MIO_arst
);
output this_val;
reg this_v... | 6.728673 |
module ActUnit_Connections_OutBlocking_bool_Connections_SYN_PORT_Push (
this_val,
this_rdy,
this_msg,
ccs_ccore_start_rsc_dat,
ccs_ccore_done_sync_vld,
ccs_MIO_clk,
ccs_MIO_arst
);
output this_val;
input this_rdy;
output this_msg;
input ccs_ccore_start_rsc_dat;
output ccs_ccore_don... | 6.728673 |
module ActUnit_Adpfloat2Fixed_mgc_shift_l_v5 (
a,
s,
z
);
parameter width_a = 4;
parameter signd_a = 1;
parameter width_s = 2;
parameter width_z = 8;
input [width_a-1:0] a;
input [width_s-1:0] s;
output [width_z -1:0] z;
generate
if (signd_a) begin : SGNED
assign z = fshl_u(a, s,... | 7.584475 |
module ActUnit_Fixed2Adpfloat_mgc_shift_l_v5 (
a,
s,
z
);
parameter width_a = 4;
parameter signd_a = 1;
parameter width_s = 2;
parameter width_z = 8;
input [width_a-1:0] a;
input [width_s-1:0] s;
output [width_z -1:0] z;
generate
if (signd_a) begin : SGNED
assign z = fshl_u(a, s,... | 7.413902 |
module ActUnit (
clk,
rst,
start_val,
start_rdy,
start_msg,
act_port_val,
act_port_rdy,
act_port_msg,
rva_in_val,
rva_in_rdy,
rva_in_msg,
rva_out_val,
rva_out_rdy,
rva_out_msg,
output_port_val,
output_port_rdy,
output_port_msg,
done_val,
done_r... | 6.812263 |
module ActUnit (
clk,
rst,
start_val,
start_rdy,
start_msg,
act_port_val,
act_port_rdy,
act_port_msg,
rva_in_val,
rva_in_rdy,
rva_in_msg,
rva_out_val,
rva_out_rdy,
rva_out_msg,
output_port_val,
output_port_rdy,
output_port_msg,
done_val,
done_r... | 6.812263 |
module concat_module #(
parameter NB_ADDR = 26, // Jump addr in J type instructions
parameter NB_PC = 32,
parameter NB_UPPER_PC = 4, // Number of bits of upper PC+1
parameter NB_LOWER_BITS = 2
) (
input i_clock,
input i_reset,
... | 7.560387 |
module PECore_ccs_conn_in_wait_v1 (
vld,
rdy,
dat,
idat,
irdy,
ivld,
clk,
en,
arst,
srst
);
parameter integer width = 32;
parameter integer ph_clk = 1;
parameter integer ph_en = 1;
parameter integer ph_arst = 1;
parameter integer ph_srst = 1;
//parameter has_... | 7.727247 |
module PECore_ccs_conn_out_wait_v1 (
vld,
rdy,
dat,
idat,
ivld,
irdy,
clk,
en,
arst,
srst
);
parameter integer width = 32;
parameter integer ph_clk = 1;
parameter integer ph_en = 1;
parameter integer ph_arst = 1;
parameter integer ph_srst = 1;
//parameter has_... | 7.727247 |
module PECore_ProductSum_ccs_in_v1 (
idat,
dat
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] idat;
input [width-1:0] dat;
wire [width-1:0] idat;
assign idat = dat;
endmodule
| 6.633852 |
module PECore_ProductSum_mgc_out_dreg_v2 (
d,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input [width-1:0] d;
output [width-1:0] z;
wire [width-1:0] z;
assign z = d;
endmodule
| 6.633852 |
module PECore_ProductSum_mgc_shift_l_v5 (
a,
s,
z
);
parameter width_a = 4;
parameter signd_a = 1;
parameter width_s = 2;
parameter width_z = 8;
input [width_a-1:0] a;
input [width_s-1:0] s;
output [width_z -1:0] z;
generate
if (signd_a) begin : SGNED
assign z = fshl_u(a, s, a[wi... | 6.633852 |
module PECore_ProductSum_ACC_16i25_1o29_6c39adcf8fa7ac08d026ec7c525fe9f9e6 (
I_1,
I_2,
I_3,
I_4,
I_5,
I_6,
I_7,
I_8,
I_9,
I_10,
I_11,
I_12,
I_13,
I_14,
I_15,
I_16,
O_1
);
input [24:0] I_1;
input [24:0] I_2;
input [24:0] I_3;
input [24:0] I_4;
... | 6.633852 |
module PECore_ProductSum (
in_1_data_rsc_dat,
in_2_data_rsc_dat,
out_rsc_z,
ccs_ccore_start_rsc_dat,
ccs_ccore_clk,
ccs_ccore_arst,
ccs_ccore_en
);
input [127:0] in_1_data_rsc_dat;
input [127:0] in_2_data_rsc_dat;
output [31:0] out_rsc_z;
input ccs_ccore_start_rsc_dat;
input ccs_cc... | 6.633852 |
module PECore_mgc_muladd1 (
a,
b,
c,
cst,
d,
z
);
// operation is z = a * (b + d) + c + cst
parameter width_a = 0;
parameter signd_a = 0;
parameter width_b = 0;
parameter signd_b = 0;
parameter width_c = 0;
parameter signd_c = 0;
parameter width_cst = 0;
parameter signd_cst = 0... | 6.774883 |
module PECore_mgc_shift_l_v5 (
a,
s,
z
);
parameter width_a = 4;
parameter signd_a = 1;
parameter width_s = 2;
parameter width_z = 8;
input [width_a-1:0] a;
input [width_s-1:0] s;
output [width_z -1:0] z;
generate
if (signd_a) begin : SGNED
assign z = fshl_u(a, s, a[width_a-1]);
... | 7.86481 |
module PECore_mgc_shift_r_v5 (
a,
s,
z
);
parameter width_a = 4;
parameter signd_a = 1;
parameter width_s = 2;
parameter width_z = 8;
input [width_a-1:0] a;
input [width_s-1:0] s;
output [width_z -1:0] z;
generate
if (signd_a) begin : SGNED
assign z = fshr_u(a, s, a[width_a-1]);
... | 7.86481 |
module PECore_mgc_shift_bl_v5 (
a,
s,
z
);
parameter width_a = 4;
parameter signd_a = 1;
parameter width_s = 2;
parameter width_z = 8;
input [width_a-1:0] a;
input [width_s-1:0] s;
output [width_z -1:0] z;
generate
if (signd_a) begin : SGNED
assign z = fshl_s(a, s, a[width_a-1]);... | 7.86481 |
module BLOCK_1R1W_RBW #(
parameter addr_width = 8,
parameter data_width = 7,
parameter depth = 256,
parameter latency = 1
) (
clk,
clken,
d,
q,
radr,
wadr,
we
);
input clk;
input clken;
input [data_width-1:0] d;
output [data_width-1:0] q;
input [addr_width-1:0] ra... | 7.459037 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_125_8_128_256_256_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0] q... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_123_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_122_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_121_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_120_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_119_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_118_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_117_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_116_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_115_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_114_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_113_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_112_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_111_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_110_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_109_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_Xilinx_RAMS_BLOCK_1R1W_RBW_rwport_en_108_12_128_4096_4096_128_1_gen (
clken,
q,
radr,
we,
d,
wadr,
clken_d,
d_d,
q_d,
radr_d,
wadr_d,
we_d,
writeA_w_ram_ir_internal_WMASK_B_d,
readA_r_ram_ir_internal_RMASK_B_d
);
output clken;
input [127:0... | 6.533713 |
module PECore_PECore_PECoreRun_PECoreRun_fsm (
clk,
rst,
PECoreRun_wen,
fsm_output
);
input clk;
input rst;
input PECoreRun_wen;
output [4:0] fsm_output;
reg [4:0] fsm_output;
// FSM State Type Declaration for PECore_PECore_PECoreRun_PECoreRun_fsm_1
parameter
PECoreRun_rlp_C_0 = 3'd0... | 6.533713 |
module PECore_PECore_PECoreRun_staller (
clk,
rst,
PECoreRun_wen,
PECoreRun_wten,
act_port_Push_mioi_wen_comp,
rva_out_Push_mioi_wen_comp
);
input clk;
input rst;
output PECoreRun_wen;
output PECoreRun_wten;
reg PECoreRun_wten;
input act_port_Push_mioi_wen_comp;
input rva_out_Push_... | 6.533713 |
module PECore_PECore_PECoreRun_start_PopNB_mioi_start_PopNB_mio_wait_dp (
clk,
rst,
start_PopNB_mioi_idat_mxwt,
start_PopNB_mioi_ivld_mxwt,
start_PopNB_mioi_biwt,
start_PopNB_mioi_bdwt,
start_PopNB_mioi_idat,
start_PopNB_mioi_ivld
);
input clk;
input rst;
output start_PopNB_mioi_id... | 6.533713 |
module PECore_PECore_PECoreRun_start_PopNB_mioi_start_PopNB_mio_wait_ctrl (
PECoreRun_wen,
PECoreRun_wten,
start_PopNB_mioi_oswt,
start_PopNB_mioi_biwt,
start_PopNB_mioi_bdwt
);
input PECoreRun_wen;
input PECoreRun_wten;
input start_PopNB_mioi_oswt;
output start_PopNB_mioi_biwt;
output sta... | 6.533713 |
module PECore_PECore_PECoreRun_rva_out_Push_mioi_rva_out_Push_mio_wait_dp (
clk,
rst,
rva_out_Push_mioi_oswt,
rva_out_Push_mioi_wen_comp,
rva_out_Push_mioi_biwt,
rva_out_Push_mioi_bdwt,
rva_out_Push_mioi_bcwt
);
input clk;
input rst;
input rva_out_Push_mioi_oswt;
output rva_out_Push_... | 6.533713 |
module PECore_PECore_PECoreRun_rva_out_Push_mioi_rva_out_Push_mio_wait_ctrl (
PECoreRun_wen,
rva_out_Push_mioi_oswt,
rva_out_Push_mioi_biwt,
rva_out_Push_mioi_bdwt,
rva_out_Push_mioi_bcwt,
rva_out_Push_mioi_ivld_PECoreRun_sct,
rva_out_Push_mioi_irdy
);
input PECoreRun_wen;
input rva_out_... | 6.533713 |
module PECore_PECore_PECoreRun_act_port_Push_mioi_act_port_Push_mio_wait_dp (
clk,
rst,
act_port_Push_mioi_oswt,
act_port_Push_mioi_wen_comp,
act_port_Push_mioi_biwt,
act_port_Push_mioi_bdwt,
act_port_Push_mioi_bcwt
);
input clk;
input rst;
input act_port_Push_mioi_oswt;
output act_p... | 6.533713 |
module PECore_PECore_PECoreRun_act_port_Push_mioi_act_port_Push_mio_wait_ctrl (
PECoreRun_wen,
act_port_Push_mioi_oswt,
act_port_Push_mioi_biwt,
act_port_Push_mioi_bdwt,
act_port_Push_mioi_bcwt,
act_port_Push_mioi_ivld_PECoreRun_sct,
act_port_Push_mioi_irdy
);
input PECoreRun_wen;
input ... | 6.533713 |
module PECore_PECore_PECoreRun_rva_in_PopNB_mioi_rva_in_PopNB_mio_wait_dp (
clk,
rst,
rva_in_PopNB_mioi_idat_mxwt,
rva_in_PopNB_mioi_ivld_mxwt,
rva_in_PopNB_mioi_biwt,
rva_in_PopNB_mioi_bdwt,
rva_in_PopNB_mioi_idat,
rva_in_PopNB_mioi_ivld
);
input clk;
input rst;
output [168:0] rva... | 6.533713 |
module PECore_PECore_PECoreRun_rva_in_PopNB_mioi_rva_in_PopNB_mio_wait_ctrl (
PECoreRun_wen,
PECoreRun_wten,
rva_in_PopNB_mioi_oswt,
rva_in_PopNB_mioi_biwt,
rva_in_PopNB_mioi_bdwt
);
input PECoreRun_wen;
input PECoreRun_wten;
input rva_in_PopNB_mioi_oswt;
output rva_in_PopNB_mioi_biwt;
out... | 6.533713 |
module PECore_PECore_PECoreRun_input_port_PopNB_mioi_input_port_PopNB_mio_wait_dp (
clk,
rst,
input_port_PopNB_mioi_idat_mxwt,
input_port_PopNB_mioi_ivld_mxwt,
input_port_PopNB_mioi_biwt,
input_port_PopNB_mioi_bdwt,
input_port_PopNB_mioi_idat,
input_port_PopNB_mioi_ivld
);
input clk;
... | 6.533713 |
module PECore_PECore_PECoreRun_input_port_PopNB_mioi_input_port_PopNB_mio_wait_ctrl (
PECoreRun_wen,
PECoreRun_wten,
input_port_PopNB_mioi_oswt,
input_port_PopNB_mioi_biwt,
input_port_PopNB_mioi_bdwt
);
input PECoreRun_wen;
input PECoreRun_wten;
input input_port_PopNB_mioi_oswt;
output input... | 6.533713 |
module PECore_PECore_PECoreRun_start_PopNB_mioi (
clk,
rst,
start_val,
start_rdy,
start_msg,
PECoreRun_wen,
PECoreRun_wten,
start_PopNB_mioi_oswt,
start_PopNB_mioi_idat_mxwt,
start_PopNB_mioi_ivld_mxwt
);
input clk;
input rst;
input start_val;
output start_rdy;
input st... | 6.533713 |
module PECore_PECore_PECoreRun_rva_out_Push_mioi (
clk,
rst,
rva_out_val,
rva_out_rdy,
rva_out_msg,
PECoreRun_wen,
rva_out_Push_mioi_oswt,
rva_out_Push_mioi_wen_comp,
rva_out_Push_mioi_idat
);
input clk;
input rst;
output rva_out_val;
input rva_out_rdy;
output [127:0] rva_o... | 6.533713 |
module PECore_PECore_PECoreRun_act_port_Push_mioi (
clk,
rst,
act_port_val,
act_port_rdy,
act_port_msg,
PECoreRun_wen,
act_port_Push_mioi_oswt,
act_port_Push_mioi_wen_comp,
act_port_Push_mioi_idat
);
input clk;
input rst;
output act_port_val;
input act_port_rdy;
output [319... | 6.533713 |
module PECore_PECore_PECoreRun_rva_in_PopNB_mioi (
clk,
rst,
rva_in_val,
rva_in_rdy,
rva_in_msg,
PECoreRun_wen,
PECoreRun_wten,
rva_in_PopNB_mioi_oswt,
rva_in_PopNB_mioi_idat_mxwt,
rva_in_PopNB_mioi_ivld_mxwt
);
input clk;
input rst;
input rva_in_val;
output rva_in_rdy;
... | 6.533713 |
module PECore_PECore_PECoreRun_input_port_PopNB_mioi (
clk,
rst,
input_port_val,
input_port_rdy,
input_port_msg,
PECoreRun_wen,
PECoreRun_wten,
input_port_PopNB_mioi_oswt,
input_port_PopNB_mioi_idat_mxwt,
input_port_PopNB_mioi_ivld_mxwt
);
input clk;
input rst;
input input_... | 6.533713 |
module ccs_in_wait_v1 (
idat,
rdy,
ivld,
dat,
irdy,
vld
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] idat;
output rdy;
output ivld;
input [width-1:0] dat;
input irdy;
input vld;
wire [width-1:0] idat;
wire rdy;
wire ... | 7.497393 |
module ccs_out_wait_v1 (
dat,
irdy,
vld,
idat,
rdy,
ivld
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] dat;
output irdy;
output vld;
input [width-1:0] idat;
input rdy;
input ivld;
wire [width-1:0] dat;
wire irdy;
wire ... | 7.750452 |
module crc32_core_core_fsm (
clk,
rst,
core_wen,
fsm_output,
main_C_0_tr0,
for_C_0_tr0
);
input clk;
input rst;
input core_wen;
output [3:0] fsm_output;
reg [3:0] fsm_output;
input main_C_0_tr0;
input for_C_0_tr0;
// FSM State Type Declaration for crc32_core_core_fsm_1
parame... | 8.032458 |
module crc32_core_staller (
core_wen,
in_rsci_wen_comp,
out_rsci_wen_comp
);
output core_wen;
input in_rsci_wen_comp;
input out_rsci_wen_comp;
// Interconnect Declarations for Component Instantiations
assign core_wen = in_rsci_wen_comp & out_rsci_wen_comp;
endmodule
| 7.150822 |
module crc32_core_out_rsci_out_wait_ctrl (
out_rsci_iswt0,
out_rsci_biwt,
out_rsci_irdy
);
input out_rsci_iswt0;
output out_rsci_biwt;
input out_rsci_irdy;
// Interconnect Declarations for Component Instantiations
assign out_rsci_biwt = out_rsci_iswt0 & out_rsci_irdy;
endmodule
| 7.456378 |
module crc32_core_in_rsci_in_wait_ctrl (
in_rsci_iswt0,
in_rsci_biwt,
in_rsci_ivld
);
input in_rsci_iswt0;
output in_rsci_biwt;
input in_rsci_ivld;
// Interconnect Declarations for Component Instantiations
assign in_rsci_biwt = in_rsci_iswt0 & in_rsci_ivld;
endmodule
| 7.045892 |
module crc32_core_out_rsci (
out_rsc_dat,
out_rsc_vld,
out_rsc_rdy,
out_rsci_oswt,
out_rsci_wen_comp,
out_rsci_idat
);
output [31:0] out_rsc_dat;
output out_rsc_vld;
input out_rsc_rdy;
input out_rsci_oswt;
output out_rsci_wen_comp;
input [31:0] out_rsci_idat;
// Interconnect Decl... | 7.456378 |
module crc32_core_in_rsci (
in_rsc_dat,
in_rsc_vld,
in_rsc_rdy,
in_rsci_oswt,
in_rsci_wen_comp,
in_rsci_idat_mxwt
);
input [7:0] in_rsc_dat;
input in_rsc_vld;
output in_rsc_rdy;
input in_rsci_oswt;
output in_rsci_wen_comp;
output [7:0] in_rsci_idat_mxwt;
// Interconnect Declarati... | 7.045892 |
module crc32 (
clk,
rst,
in_rsc_dat,
in_rsc_vld,
in_rsc_rdy,
out_rsc_dat,
out_rsc_vld,
out_rsc_rdy
);
input clk;
input rst;
input [7:0] in_rsc_dat;
input in_rsc_vld;
output in_rsc_rdy;
output [31:0] out_rsc_dat;
output out_rsc_vld;
input out_rsc_rdy;
// Interconnect ... | 7.019053 |
module conclover_core (
input clk,
input rst,
input [15:0] len_write,
input [15:0] len_read,
input start,
output reg work,
// Inside bus
output reg [15:0] rel_addr,
output reg write,
output reg read,
output reg [7:0] save_data,
input [7:0] read_data,
input rdy,
... | 7.100088 |
module conclover_shift (
input ena,
input clk,
input rst,
input signed [7:0] rec,
output signed [7:0] out0,
output signed [7:0] out1,
output signed [7:0] out2,
output signed [7:0] out3,
output signed [7:0] out4,
output signed [7:0] out5,
output signed [7:0] out6,
output ... | 7.553347 |
module conclover_conclover_signal (
input clk,
input rst,
// Avalon MM
input avs_s0_write,
input avs_s0_read,
input [4:0] avs_s0_address,
input [31:0] avs_s0_writedata,
output reg [31:0] avs_s0_readdata,
// Signal
output reg signed [7:0] sin0,
output reg signed [7:0] sin... | 7.303121 |
module conclover_controller (
input clk,
input rst,
// Avalon MM
input avs_s0_write,
input avs_s0_read,
input [4:0] avs_s0_address,
input [31:0] avs_s0_writedata,
output reg [31:0] avs_s0_readdata,
// Outputs
output reg [15:0] read_start_addr,
output reg [15:0] read_stop... | 7.303121 |
module CONDCHECK (
Cond,
Flag,
Out
);
input [1:0] Cond;
output reg Out;
input [3:0] Flag;
always @* begin
casex (Cond)
2'b00: Out = 1'b1; //No condition
2'b01: Out = Flag[2]; //Equal: out= z_flag
2'b10: Out = (~Flag[3]); //Greater or Equal: out= ~n_flag
2'b11:... | 7.077429 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
wire [7:0] s1, s2;
// assign intermediate_result1 = compare? true: false;
assign s1 = a < b ? a : b;
assign s2 = c < d ? c : d;
assign min = s1 < s2 ? s1 : s2;
endmodule
| 7.203305 |
module condAdder (
step,
A,
totalSteps
);
input step;
input [7:0] A;
output [7:0] totalSteps;
assign totalSteps = (step == 1'b1) ? (A + 8'b1) : (A + 8'b0);
endmodule
| 7.154216 |
module ConditionalCheck (
input [`COND_LEN - 1:0] cond,
input [3:0] statusRegister,
output wire condState
);
wire z, c, n, v;
assign {z, c, n, v} = statusRegister;
reg tempCondition;
assign condState = tempCondition;
always @(*) begin
case (cond)
`COND_EQ: begin
tempCondition... | 6.763969 |
module ConditionalCodeLogic (
input clk,
input [15:0] dataFromBus,
input LDCC,
output reg [2:0] NZP
);
reg [2:0] temp_conditional_code = 0;
always @(*) begin
if (dataFromBus[15] == 1'b1) temp_conditional_code = 3'b100;
else if (dataFromBus[14:0] == 0) temp_conditional_code = 3'b010;
el... | 6.830011 |
module ConditionalLogicUnit (
FlagW,
RegWrite,
MemWrite,
PCSrc,
RegW,
MemW,
Cond,
ALUFlags,
FLAGS_BEFORE,
FLAGS_AFTER
);
input [1:0] FlagW;
input [3:0] ALUFlags, Cond, FLAGS_BEFORE;
input RegW, MemW;
reg CondEx = 0;
reg [1:0] FlagWrite = 2'b00;
output reg [3:0] ... | 6.748074 |
module dispsync (
input [15:0] Hexs, //端口变量说明与定义合并
input [1:0] Scan,
input [3:0] Point,
input [3:0] Les,
output [3:0] Hex,
output p,
LE,
output [3:0] AN
);
assign Hex = (2'b00 == Scan) ? Hexs[3:0] :
(2'b01 == Scan) ? Hexs[7:4] :
(2'b10 == Scan) ? Hexs... | 7.485213 |
module conditional_flow(B1, B2, B3, C, A);
output wire A;
input integer C;
input wire B1, B2, B3;
assign A = (C == 1) ? B1 : ((C == 2) ? B2 : ((C == 3) ?
B3 : 0));
endmodule
| 7.347353 |
module conditional_flow(B1, B2, B3, C, A);
output wire A;
input integer C;
input B1, B2, B3;
always @(B1, B2, B3, C)
begin
if (C == 1) A = B1;
else if (C == 2) A = B2;
else if (C == 3) A = B3;
else A = 0;
end
endmodule
| 7.347353 |
module Conditional_Logic (
input CLK,
input reset,
input [3:0] Cond,
input [3:0] ALUFlags,
input [1:0] FlagW,
input PCS,
input RegW,
input MemW,
input NoWrite,
input in_link,
output wire PCSrc,
output wire RegWrite,
output wire MemWrite,
output wire link
);
wir... | 6.582173 |
module mux1 (
input one,
zero,
sel,
output out
);
assign out = (sel) ? one : zero;
endmodule
| 6.909982 |
module mux2 (
input [1:0] one,
zero,
input sel,
output [1:0] out
);
assign out = (sel) ? one : zero;
endmodule
| 7.816424 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
wire [7:0] x, y;
assign x = (a < b) ? a : b;
assign y = (c < d) ? c : d;
assign min = (x < y) ? x : y;
endmodule
| 7.203305 |
module ConditionControl (
input clk,
input [1:0] Cond,
input N_in,
input Z_in,
input WE_C_aux,
input suma_resta,
input salto,
input WE_flags,
output wire sel_pc,
output wire WE_C
);
reg N = 1'b0;
reg Z = 1'b0;
wire cumple;
always @(posedge clk) begin
if (WE_flags... | 7.376084 |
module ConditionHandler (
output reg T_address, // Sends signal that target address is changing to the branched address
output reg BL_reg, // Sends signal to register that its branching
input B, // receives branching permision from control unit
input Cond_true, // // receives if... | 7.496419 |
module conditions_mux (
output reg out,
input in0,
in1,
input [1:0] select
);
always @(select, in0, in1)
case (select)
2'b00: out = in0;
2'b01: out = in1;
endcase
endmodule
| 6.867387 |
module ConditionTester (
output reg Cond, // True or False
input [3:0] Code, // Condition codes
input [3:0] Flags // Updated flags
//Flags[3] = V | Flags[2] = C | Flags[1] = Z | Flags[0] = N
);
parameter EQ = 4'b0000;
parameter NE = 4'b0001;
parameter CS = 4'b0010; // HS
parameter CC = 4'b00... | 7.053074 |
module condition_logic
#(parameter alu_flags_w = `ALU_NUM_FLAGS,
parameter mac_flags_w = `MAC_NUM_FLAGS,
parameter ctrl_w = `COND_LOGIC_CTRL_WIDTH)
(
input wire [ctrl_w-1:0] ctrl_i,
input wire [alu_flags_w-1:0] alu_flags_i,
input wire [mac_flags_w-1:0] mac_flags_i,
output reg condition_check_o
... | 8.575857 |
module condition_tester (
output reg cond,
input [3:0] flags_in,
condition_code
);
parameter EQ = 4'b0000,
NE = EQ + 1,
CS_HS = NE + 1,
CC_LO = CS_HS + 1,
MI = CC_LO + 1,
PL = MI + 1,
VS = PL + 1,
VC = VS + 1,
HI = VC + 1,
LS = HI + 1,
GE = LS + 1,
LT = GE + 1,... | 6.90801 |
module condi_jump (
input [31:0] A,
input [31:0] B,
input blez,
input beq,
input bne,
output condi_suc
);
wire a_equal_b;
wire a_less_equal_0;
wire a_not_equal_b;
assign a_equal_b = (A == B);
assign a_less_equal_0 = ($signed(A) <= 0);
assign a_not_equal_b = ~a_equal_b;
assign c... | 6.749099 |
module CondLogic (
input CLK,
input PCS,
input RegW,
input MemW,
input [1:0] FlagW,
input [3:0] Cond,
input [3:0] ALUFlags,
input NoWrite,
output wire PCSrc,
output wire RegWrite,
output wire MemWrite
);
reg CondEx;
reg N = 0, Z = 0, C = 0, V = 0;
//reg N,Z,C,V;
wir... | 6.804164 |
module condMux (
input [3:0] data,
output reg [1:0] selOut
);
always @(data) begin
if (data[0]) begin
selOut <= 2'b10;
end else begin
selOut <= 2'b01;
end
end
endmodule
| 7.384607 |
module conduit_splitter #(
parameter OUTPUT_NUM = 2
) (
input conduit_input,
output conduit_output_0,
output conduit_output_1,
output conduit_output_2,
output conduit_output_3,
output conduit_output_4
);
generate
assign conduit_output_0 = conduit_input;
assign conduit_output_1 = ... | 7.09687 |
module cond_branch_control ( /*AUTOARG*/
// Outputs
cond_branch_w_o_h,
// Inputs
funct_3_w_i,
eq_w_i_h,
gteu_w_i_h,
gtes_w_i_h,
ltu_w_i_h,
lts_w_i_h,
cmp_branch_w_i_h
);
//-----------------------------------------------------------------------------
// Inputs
//----------... | 7.982695 |
module cond_check (
input n,
z,
c,
v,
input [3:0] cond,
output reg o
);
always @(*) begin
case (cond)
4'b0000: o = z; // equal
4'b0001: o = ~z; // not equal
4'b0010: o = c; // carry set/unsigned higher or same
4'b0011: o = ~c; // carry clear/unsigned lower
... | 6.912142 |
module cond_decode #(
parameter WIDTH = 16
) (
input C,
L,
F,
N,
Z,
input [3:0] cond_code,
output reg code_met
);
always @(*)
case (cond_code)
`EQ: code_met = Z ? 1'b1 : 1'b0;
`NE: code_met = ~Z ? 1'b1 : 1'b0;
`GE: code_met = (N || Z) ? 1'b1 : 1'b0;
... | 6.706166 |
module cond_check (
cond,
flags,
cond_ex
);
input [3:0] cond, flags;
output reg cond_ex;
wire neg, zero, carry, overflow;
assign {neg, zero, carry, overflow} = flags;
always @(*) begin
case (cond)
4'b0000: cond_ex <= zero;
4'b0001: cond_ex <= ~zero;
4'b0010: cond_ex <= carry... | 6.912142 |
module ff #(
parameter W = 8
) (
clk,
reset,
en,
d,
q
);
input clk, reset, en;
input [W-1:0] d;
output reg [W-1:0] q;
always @(posedge clk or posedge reset) begin
if (reset) q <= 0;
else if (en) q <= d;
end
endmodule
| 7.525989 |
module cond_pass (
input [3:0] cond,
input [3:0] apsr_reg_nzcv,
output passed
);
reg pass_tmp;
always @(cond or apsr_reg_nzcv) begin
case (cond[3:1])
3'b000: pass_tmp = (apsr_reg_nzcv[2]); //EQ or NE
3'b001: pass_tmp = (apsr_reg_nzcv[1]); //CS or CC
3'b010: pass_tmp = (apsr_reg_... | 7.030599 |
module CONFF (
output reg q, //to control unit
input CONin,
clr, //CONin is control signal
input [ 1:0] IRbits,
input [31:0] busMuxOut
);
wire IR0 = IRbits[0];
wire IR1 = IRbits[1];
reg [4:0] decoderOut;
wire dconff, and0, and1, and2, and3, norout;
... | 6.95285 |
module ConfigFSM (
CLK,
WriteData,
WriteStrobe,
Reset,
FrameAddressRegister,
LongFrameStrobe,
RowSelect
);
parameter NumberOfRows = 14;
parameter RowSelectWidth = 5;
parameter FrameBitsPerRow = 32;
parameter desync_flag = 20;
input CLK;
input [31:0] WriteData;
input WriteStro... | 7.114914 |
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