code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module CompressedDecoder (
input reset,
input [31:0] pc,
input [31:0] instruction_code,
input prediction,
output reg jump_flag,
output reg [31:0] jump_address
);
always @(instruction_code) begin
if (reset == 1'b0) begin
jump_flag = 0;
end
else if(instruction_code[6:0] == 7'b1101... | 7.296323 |
module compression_3_2 (
a,
b,
c,
co,
s
);
parameter n = 16; // n 代表a，b，c采用k bit
parameter diffba = 16; //diffba 表示输出的a，b之间位移量
parameter diffca = 16; //diffba 表示输出的a，c之间位移量
input wire [n-1 : 0] a;
input wire [n-1 : 0] b;
input wire [n-1 : 0] c;
output wire [n-1:0] s;
output wire [... | 8.370872 |
module compression (
clk_clk,
leds_w_export,
line1_1_in_port,
line1_1_out_port,
line1_2_in_port,
line1_2_out_port,
line2_1_in_port,
line2_1_out_port,
line2_2_in_port,
line2_2_out_port,
line3_1_in_port,
line3_1_out_port,
line3_2_in_port,
line3_2_out_port,
line4... | 6.550778 |
module compression_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 7.221461 |
module compression_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear... | 7.221461 |
module compression_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg ... | 7.221461 |
module compression_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
in... | 7.221461 |
module compression_LIne2_2 (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [31:0] in_port;
in... | 6.603119 |
module compression_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "compression_onchip_memory2_0.hex";
output [31:0] readdata;
input [15:0] a... | 6.844638 |
module compression_sdram_controller_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [58:0] rd_data;
input... | 6.543426 |
module compression_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1556863269 : 0;
endmodule... | 6.543426 |
module COMPRESSOR (
input x1,
x2,
x3,
x4,
cin,
output cout,
sum,
carry
);
wire r1, r2, r3, r4, r5, r6, r7, r8;
XOR_BASE xor1 (
.X(x1),
.Y(x2),
.s(r1),
.s_bar(r2)
);
XOR_BASE xor2 (
.X(x3),
.Y(x4),
.s(r3),
.s_bar(r4)
);
mux m1 ... | 6.817513 |
module Compressor32 #(
parameter XLEN = 49
) (
input [XLEN - 1 : 0] A_i,
input [XLEN - 1 : 0] B_i,
input [XLEN - 1 : 0] C_i,
output [XLEN - 1 : 0] Sum_o,
output [XLEN - 1 : 0] Carry_o
);
generate
genvar j;
for (j = 0; j < XLEN; j = j + 1) begin
FullAdder FA (
.augen... | 7.180883 |
module dcc_sync ( //clk,
sclk,
dcc_en, // clk rising, sync with start of the frame
finish_dcc, // sclk rising
dcc_vld, // clk rising
dcc_data, //[15:0] clk risimg
statistics_dv, //sclk
statistics_do //[15:0] sclk
);
//input clk;
input sclk, dcc_en, finish_dcc, dcc_vld;
i... | 6.690892 |
module should take top_carry shift one bit to the left as input
// 07/25/2022 - hidden_carry_msb wire added, collect overflow bits to suppress sign extension
// 09/12/2022 - Add BSD-3-Clause Licence
//
//////////////////////////////////////////////////////////////////////////////////
// License information:
//
//... | 7.872173 |
module : compressor42_tb
//version : 1.0
//Description : tb of compressor42_tb
//-----------------------------------------------------------------------
//author : li weihan
//Email : weihanlee@foxmail.com
//time : 26th july, 2020
//-----------------------------------------------------------------------
`timescale 1ns/... | 6.561032 |
module compressor4_2 (
sum,
c1,
c2,
a,
b,
c,
d,
cin
);
input a, b, c, d, cin;
output sum, c1, c2;
wire tmp;
assign tmp = b ^ c ^ d;
assign c1 = (b & c) | (c & d) | (b & d);
assign c2 = (a & tmp) | (tmp & cin) | (a & cin);
assign sum = a ^ tmp ^ cin;
endmodule
| 6.761231 |
module Compressor53 (
input wire x1,
x2,
x3,
x4,
x5,
output reg c2,
c1,
s
);
always @(*) begin
case ({
x1, x2, x3, x4, x5
})
5'b00000: {c2, c1, s} = 3'b000;
5'b00001: {c2, c1, s} = 3'b001;
5'b00010: {c2, c1, s} = 3'b001;
5'b00011: {c2, c1, s} = ... | 6.813352 |
module compressor5to1 (
x1,
x2,
x3,
x4,
x5,
Cin1,
Cin2,
Sum,
Carry,
Cout1,
Cout2
);
input x1, x2, x3, x4, x5, Cin1, Cin2;
output Sum, Cout1, Cout2, Carry;
wire w1, w2, w3;
assign Cout1 = ((x1 ^ x2) & x3) | (x1 & x2);
assign Cout2 = ((x4 ^ x5) & x4) | ((~(x4 ^ x5)... | 7.401516 |
module
//===================================================================
module compressor6_2_top #(parameter DATA_WIDTH = 32)(
clk,
rstn,
flag_low,
a,
b,
c,
d,
e,
f,
sum_result,
cout_result
);
input clk,rstn;
input [DATA... | 7.574158 |
module FA (
input [2:0] p,
output [2:1] w
); // w[2] = carry ; w[1] =sum
xor sum (w[1], p[2], p[1], p[0]);
wire ab, bc, ca;
and a1 (ab, p[2], p[1]);
and a2 (bc, p[1], p[0]);
and a3 (ca, p[0], p[2]);
or carry (w[2], ab, bc, ca);
endmodule
| 8.362615 |
module HA (
input [1:0] p,
output [2:1] w
);
xor sum (w[1], p[0], p[1]);
and carry (w[2], p[0], p[1]);
endmodule
| 9.138493 |
module half_adder (
input a,
input b,
output sum,
output carry
); //dadda8
assign sum = a ^ b;
assign carry = a & b;
endmodule
| 6.966406 |
module fa (
input A,
B,
Ci,
output S,
Co
); //dadda16
xor xor1 (S, A, B, Ci);
assign Co = (A & B) | (B & Ci) | (Ci & A);
endmodule
| 7.001699 |
module ha (
input A,
B,
output S,
C
); //dadda16
xor x1 (S, A, B);
and x2 (C, A, B);
endmodule
| 7.857591 |
module compressor4_2 (
input [3:0] p,
output [2:1] w
); // p3,p2,p1,p0, output w2,w1);
wire a1, a2;
and u1 (a1, p[0], p[1]); //assign a1 = p0 & p1;
and u2 (a2, p[2], p[3]); //assign a2 = p2 & p3;
or u3 (w[2], a1, p[2], p[3]); //assign w2 = a1 | p2 | p3;
or u4 (w[1], a2, p[0], p[1]); //assign w1 ... | 6.761231 |
module compressor5_3 (
input [4:0] p,
output [3:1] w
); // p4,p3,p2,p1,p0, output w3,w2,w1);
wire a1, a2;
and u1 (a1, p[0], p[1]); //assign a1 = p0 & p1;
and u2 (a2, p[2], p[3]); //assign a2 = p2 & p3;
or u3 (w[3], p[0], p[1]); //assign w3 = p0 | p1;
or u4 (w[1], a1, p[2], p[3]); //assign w1 = ... | 6.554722 |
module compressor7_4 (
input [6:0] p,
output [4:1] w
);
compressor4_2 u1 (
.p(p[6:3]),
.w(w[4:3])
);
compressor3_2 u2 (
.p(p[2:0]),
.w(w[2:1])
);
endmodule
| 6.936228 |
module compressor8_4 (
input [7:0] p,
output [4:1] w
);
compressor4_2 u1 (
.p(p[7:4]),
.w(w[4:3])
);
compressor4_2 u2 (
.p(p[3:0]),
.w(w[2:1])
);
endmodule
| 7.001651 |
module compressor9_5 (
input [8:0] p,
output [5:1] w
);
// compressor5_3 u1(.p(p[8:4]), .w(w[5:3]));
compressor4_2 u2 (
.p(p[8:5]),
.w(w[5:4])
);
compressor5_3 u1 (
.p(p[4:0]),
.w(w[3:1])
);
endmodule
| 7.018802 |
module compressor10_5 (
input [9:0] p,
output [5:1] w
);
// compressor6_3 u1(.p(p[9:4]), .w(w[5:3]));
compressor4_2 u2 (
.p(p[9:6]),
.w(w[5:4])
);
compressor6_3 u1 (
.p(p[5:0]),
.w(w[3:1])
);
endmodule
| 6.936703 |
module compressor11_6 (
input [10:0] p,
output [ 6:1] w
);
compressor4_2 u1 (
.p(p[10:7]),
.w(w[6:5])
);
compressor4_2 u2 (
.p(p[6:3]),
.w(w[4:3])
);
compressor3_2 u3 (
.p(p[2:0]),
.w(w[2:1])
);
endmodule
| 6.645693 |
module compressor12_6 (
input [11:0] p,
output [ 6:1] w
);
compressor4_2 u1 (
.p(p[11:8]),
.w(w[6:5])
);
compressor4_2 u2 (
.p(p[7:4]),
.w(w[4:3])
);
compressor4_2 u3 (
.p(p[3:0]),
.w(w[2:1])
);
endmodule
| 6.698893 |
module compressor13_7 (
input [12:0] p,
output [ 7:1] w
);
// compressor5_3 u1(.p(p[12:8]), .w(w[7:5]));
compressor4_2 u2 (
.p(p[12:9]),
.w(w[7:6])
);
compressor4_2 u3 (
.p(p[8:5]),
.w(w[5:4])
);
compressor5_3 u1 (
.p(p[4:0]),
.w(w[3:1])
);
endmodule
| 6.5342 |
module compressor15_8 (
input [14:0] p,
output [ 8:1] w
);
compressor4_2 u1 (
.p(p[14:11]),
.w(w[8:7])
);
compressor4_2 u2 (
.p(p[10:7]),
.w(w[6:5])
);
compressor4_2 u3 (
.p(p[6:3]),
.w(w[4:3])
);
compressor3_2 u4 (
.p(p[2:0]),
.w(w[2:1])
);
endmo... | 6.944636 |
module compressor16_8 (
input [15:0] p,
output [ 8:1] w
);
compressor4_2 u1 (
.p(p[15:12]),
.w(w[8:7])
);
compressor4_2 u2 (
.p(p[11:8]),
.w(w[6:5])
);
compressor4_2 u3 (
.p(p[7:4]),
.w(w[4:3])
);
compressor4_2 u4 (
.p(p[3:0]),
.w(w[2:1])
);
endmo... | 6.878633 |
module compressor17_9(input [16:0]p, output [9:1]w);
// compressor5_3 u1(.p(p[16:12]), .w(w[9:7]));
// compressor4_2 u2(.p(p[11:8]), .w(w[6:5]));
// compressor4_2 u3(.p(p[7:4]), .w(w[4:3]));
// compressor4_2 u4(.p(p[3:0]), .w(w[2:1]));
//endmodule
| 6.622637 |
module compressor_3_2 (
in1,
in2,
in3,
s,
c
);
input in1, in2, in3;
output s, c;
assign c = (in1 & in2) | (in2 & in3) | (in3 & in1);
assign s = (in1 & in2 & in3) | (in1 & ~in2 & ~in3) | (~in1 & in2 & ~in3) | (~in1 & ~in2 & in3);
endmodule
| 7.237792 |
module compressor_3_2_group (
in1,
in2,
in3,
s,
c
);
`include "parameters.v"
parameter GRP_WIDTH = 16;
input [GRP_WIDTH-1:0] in1, in2, in3;
output [GRP_WIDTH-1:0] s, c;
compressor_3_2 compress[GRP_WIDTH-1:0] (
in1,
in2,
in3,
s,
c
);
//Test wire
wire [G... | 7.237792 |
module compressor_42 (
p0,
p1,
p2,
p3,
cin,
s,
ca,
cout
);
parameter B_SIZE = 8;
input [B_SIZE-1:0] p0;
input [B_SIZE-1:0] p1;
input [B_SIZE-1:0] p2;
input [B_SIZE-1:0] p3;
input [B_SIZE-1:0] cin;
output [B_SIZE-1:0] s;
output [B_SIZE-1:0] ca;
output [B_SIZE-1:0] cout;... | 7.00725 |
module compressor_4to3 #(
parameter TARGET_CHIP = 0
) (
input clk,
input [3:0] din,
output [2:0] sum
);
reg [2:0] sum_r = 3'b0 /* synthesis preserve */;
always @(posedge clk) begin
case (din)
4'd0: sum_r <= 3'd0;
4'd1: sum_r <= 3'd1;
4'd2: sum_r <= 3'd1;
4'd3: sum_r <=... | 7.210439 |
module Compressor_4_2 #(
parameter n = 32
) (
input [n-1:0] op0,
input [n-1:0] op1,
input [n-1:0] op2,
input [n-1:0] op3,
output [n-1:0] S,
output [n-1:0] C,
output cout
);
wire [n-1:0] cin;
genvar i;
generate
for (i = 0; i < n; i = i + 1) begin
if (i == 0)
Coun... | 6.903077 |
module compressor_4_2_group (
in1,
in2,
in3,
in4,
cin,
sum,
carry,
cout
);
`include "parameters.v"
parameter GRP_WIDTH = 16;
input [GRP_WIDTH-1:0] in1, in2, in3, in4, cin;
output [GRP_WIDTH-1:0] sum, carry, cout;
compressor_4_2 compressor_group[GRP_WIDTH-1:0] (
in1,
... | 7.593278 |
module compress_32 (
a,
b,
c,
oo,
ot
);
parameter WIDTH = 16;
input [WIDTH-1:0] a, b, c;
output [WIDTH-1:0] oo, ot;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : cmp
assign oo[i] = a[i] ^ b[i] ^ c[i];
assign ot[i] = (a[i] & b[i]) | (a[i] & c[i]) | (b[i] & c[... | 8.126928 |
module
//
// History:
// 2014-06-01: Luke Wang first edition.
//
//=============================================================================
module compress_ctrl (
clock,
reset_n,
inter_reset_n,
// compress process
compress_request,
compress_start,
co... | 7.423624 |
module compress_unit (
input [31:0] data_in,
output reg [1:0] bitmap,
output reg [9:0] length,
output reg [31:0] data_out
);
wire [ 7:0] exponent;
wire [31:0] res_0;
wire [31:0] res_8;
wire [31:0] res_16;
wire [31:0] res_32;
wire [ 7:0] compressor_8_out;
wire [15:0] compressor_16_out;
... | 6.971191 |
module compressor_8 (
input [31:0] data_in,
output [ 7:0] data_out
);
wire sign;
wire [7:0] exponent;
wire [7:0] shift;
wire [22:0] mantissa;
wire [23:0] hidden_mantissa;
wire [23:0] result_mantissa;
assign sign = data_in[31];
assign exponent = data_in[30:23];
assign mantissa = data_in[22:0... | 7.254272 |
module compressor_16 (
input [31:0] data_in,
output [15:0] data_out
);
wire sign;
wire [7:0] exponent;
wire [7:0] shift;
wire [22:0] mantissa;
wire [23:0] hidden_mantissa;
wire [23:0] result_mantissa;
assign sign = data_in[31];
assign exponent = data_in[30:23];
assign mantissa = data_in[22:... | 7.359156 |
module CompressUnitTB;
reg [31:0] data_in;
wire [31:0] data_out;
wire [1:0] bitmap;
integer i;
initial begin
data_in = 32'h01bea23f;
#3;
$finish;
end
// always #1 clk = ~clk;
compress_unit cu (
data_in,
bitmap,
data_out
);
initial begin
$dumpfile("jongse.vcd"... | 7.759219 |
module comprometido (
caracter,
len_string,
counter_caracter
);
output [3:0] caracter, len_string;
input [3:0] counter_caracter;
wire [3:0] multiplexer_out, len_string, C, O, M, P, R, E, T, I, D;
Multiplexer12 #(4) multiplex (
multiplexer_out,
C,
O,
M,
P,
R,
... | 8.54333 |
module proyecto_pc (
input rst,
input clk
);
wire [8:0] i_instruccion;
wire [7:0] i_dato;
wire [7:0] o_direccion_instruccion;
wire [7:0] o_salida_datos;
wire [7:0] o_direccion_datos;
wire RW;
Micro8bits_Harvard compu (
.clk(clk),
.rst(rst),
.i_instruccion(i_instruccion),
... | 6.642869 |
module CompuertaAnd( //TOP MODULE este ees el instanciamiento solo que se hace en el original y no me acorde
input [2:0] iA,
input iClk,
output oSalida
);
wire wSalidaAndEntradaOr;
//nombre del modulo etiqueta
CompuertaAndd Micompuerta1 (
.iA ({iA[1], iA[0]}), //MSB LSB
.iC... | 6.94627 |
module CompuertaAndd (
input [1:0] iA,
input iClk,
output oSalida
);
reg rSalida_D;
reg rSalida_Q;
assign oSalida = rSalida_Q;
always @(posedge iClk) begin
rSalida_Q <= rSalida_D;
end
always @* begin
rSalida_D = iA[0] & iA[1];
end
endmodule
| 7.719499 |
module CompuertaOr (
input [1:0] iA,
input iClk,
output oSalida
);
reg rSalida_D;
reg rSalida_Q;
assign oSalida = rSalida_Q;
always @(posedge iClk) begin
rSalida_Q <= rSalida_D;
end
always @* begin
rSalida_D = iA[0] | iA[1];
end
endmodule
| 6.650716 |
module COMPUERTA_AND (
// Entradas de un AND de 1 BIT
input AND_IN_1,
input AND_IN_2,
// Entrada en forma de vector
input [1:0] AND_IN,
// Salida de AND de bit individuales
output AND_OUT,
// Salida de AND de entrada en forma de vector
output reg AND_V_OUT
);
// Evaluacion de sali... | 7.343454 |
module computation (
output [15:0] altered,
input [15:0] code
);
wire [15:0] subbed;
subByte s1 (
.code(code),
.altered(subbed)
);
shiftRow r1 (
.code(subbed),
.altered(altered)
);
endmodule
| 7.09844 |
module Computation_Steps_Counter #(
parameter Nums_Pipeline_Stages = 4,
parameter Pipeline_Tail = Nums_Pipeline_Stages - 1,
parameter Weight_Nums = 4,
parameter Output_Nums = 8,
parameter Input_Nums = Output_Nums - Weight_Nums + 1,
parameter Total_Computation_Steps_in_bits = 6,
parameter Tot... | 7.117589 |
module will never be stalled
This module can stall stage0, and outputs these values to signal it:
our PC_en
This module can stall stage1, and outputs these values to signal it:
our A_en
out X_en
*/
`include "bpf_defs.vh"
//I use logic where Verilog syntax forces me to use reg, but I mean to
//use a combinational s... | 8.178658 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
// =============================================================================
// =============================================================================
// General Descriptio... | 7.09244 |
module ComputeEnergy #(
parameter integer SAMPLE_WIDTH = 16,
parameter integer ENERGY_WIDTH = 32,
parameter integer SIGNAL_BIAS = -32,
parameter integer DURATION = 16,
parameter integer LAG = 15
) (
input wire clock,
input wire [SAMPLE_WIDTH-1:0] sample_data,
input wire sample_valid,
... | 7.175152 |
module computeHistogram #(
parameter IMAGE_WIDTH = 240,
parameter IMAGE_HEIGHT = 180
) (
input clk,
input reset,
input [7:0] xAddress,
input [7:0] yAddress,
input pixelData,
input startHistogram,
input readHistogram,
input clearHistogram,
input stopHistogram,
output reg ... | 6.678073 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module Memory (
input [15:0] in,
input clock,
load,
input [14:0] address,
output [15:0] out
);
wire [15:0] outM, outS, outK, outSK;
Not g1 (
address[14],
N14
);
And g2 (
N14,
load,
Mload
);
And g3 (
address[14],
load,
Sload
);
RAM16K ... | 7.051739 |
module computer_input_of_verifla (
clk,
rst_l,
rec_dataH,
rec_readyH,
user_reset_low,
user_run
);
// user commands
parameter USERCMD_RESET = 8'h00, USERCMD_RUN = 8'h01;
// CI_states
parameter CI_STATES_BITS = 4, CI_STATE_IDLE = 0, CI_STATE_START_OF_NEW_CMD = 1;
// input
input clk, r... | 7.007041 |
module Computer_System_ADC (
clock,
reset,
read,
write,
readdata,
writedata,
address,
waitrequest,
adc_sclk,
adc_cs_n,
adc_din,
adc_dout
);
/*****************************************************************************
* Parameter Declaratio... | 6.538369 |
module Computer_System_Arduino_GPIO_Dir (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input wri... | 6.538369 |
module Computer_System_Arduino_Reset_N (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 6.538369 |
module Computer_System_Audio_Subsystem_Audio_PLL (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire audio_clk_clk, // audio_clk.clk
output wire reset_source_reset // reset_source.reset
);
wire audio_pll_locked_export; // a... | 6.538369 |
module Computer_System_Audio_Subsystem_Audio_PLL_audio_pll (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false... | 6.538369 |
module connects the an External Bus to Avalon Switch Fabric *
* It acts as both a master for the avalon swtich fabric *
* and a slave to the master peripheral *
* *
*******... | 9.339336 |
module Computer_System_FIFO_IN_FULL_PIO (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:... | 6.538369 |
module Computer_System_FIFO_IN_WRITE_REQ_PIO (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write... | 6.538369 |
module Computer_System_fpga_ack (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] readd... | 6.538369 |
module Computer_System_fpga_done (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] read... | 6.538369 |
module Computer_System_fpga_output_data (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [3:0] in_port;
input reset_n;
wire clk_en;
wire [ 3:0] data_in;
wire [ 3:0] read_mux_out;
reg... | 6.538369 |
module Computer_System_FP_arg_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 6.538369 |
module Computer_System_FP_result (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [31:0] in_port;
input reset_n;
wire clk_en;
wire [31:0] data_in;
wire [31:0] read_mux_out;
reg [31:... | 6.538369 |
module Computer_System_Green_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [8:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 6.538369 |
module Computer_System_HEX3_HEX0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 6.538369 |
module Computer_System_HEX5_HEX4 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [15:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 6.538369 |
module Computer_System_hps_fclk (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [... | 6.538369 |
module Computer_System_hps_input_addr (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [9:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_... | 6.538369 |
module Computer_System_hps_input_data (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [19:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write... | 6.538369 |
module Computer_System_IDATA_PIO (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [23:0] in_port;
input reset_n;
wire clk_en;
wire [23:0] data_in;
wire [23:0] read_mux_out;
reg [31:... | 6.538369 |
module Computer_System_JTAG_UART_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [7:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_w... | 6.538369 |
module Computer_System_JTAG_UART_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [7:0] wfifo_used;
input clk;
input fifo_c... | 6.538369 |
module Computer_System_JTAG_UART_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [7:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
r... | 6.538369 |
module Computer_System_JTAG_UART_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [7:0] rfifo_used;
input clk;
... | 6.538369 |
module Computer_System_JTAG_UART_for_ARM_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
in... | 6.538369 |
module Computer_System_JTAG_UART_for_ARM_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
in... | 6.538369 |
module Computer_System_JTAG_UART_for_ARM_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rs... | 6.538369 |
module Computer_System_JTAG_UART_for_ARM_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
i... | 6.538369 |
module Computer_System_juart0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [7:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 6.538369 |
module Computer_System_juart0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [7:0] wfifo_used;
input clk;
input fifo_clea... | 6.538369 |
module Computer_System_juart0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [7:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg ... | 6.538369 |
module Computer_System_juart0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [7:0] rfifo_used;
input clk;
i... | 6.538369 |
module Computer_System_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [9:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input... | 6.538369 |
module Computer_System_ODATA_PIO (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 6.538369 |
module Computer_System_Onchip_SRAM (
// inputs:
address,
address2,
byteenable,
byteenable2,
c... | 6.538369 |
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