code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Computer_System_Pushbuttons (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_... | 6.538369 |
module Computer_System_Red_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [17:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
... | 6.538369 |
module Computer_System_SDRAM_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [43:0] rd_data;
input clk;
... | 6.538369 |
module Computer_System_SDRAM_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [15:0] q;
input [15:0] data;
input [24:0] rdaddress;
input rdclken;
input [24:0] wraddress;
input wrclock;
input wren;
r... | 6.538369 |
module Computer_System_Slider_Switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [9:0] in_port;
input reset_n;
wire clk_en;
wire [ 9:0] data_in;
wire [ 9:0] read_mux_out;
reg... | 6.538369 |
module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
modul... | 7.349016 |
module Computer_System_SysID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1493960014 : 0;
endmodule
... | 6.538369 |
module Computer_System_System_PLL (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire sys_clk_clk, // sys_clk.clk
output wire sdram_clk_clk, // sdram_clk.clk
output wire reset_source_reset // reset_source.reset
... | 6.538369 |
module Computer_System_System_PLL_sys_pll (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
... | 6.538369 |
module Computer_System_VGA_Subsystem_VGA_PLL (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire vga_clk_clk, // vga_clk.clk
output wire reset_source_reset // reset_source.reset
);
wire video_pll_locked_export; // video... | 6.538369 |
module Computer_System_VGA_Subsystem_VGA_PLL_video_pll (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
... | 6.538369 |
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Edge_Detection_Router_Controller (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input ... | 6.538369 |
module Computer_System_Video_In_Subsystem_Video_In_Edge_Detection_Subsystem_Edge_Detection_Router_Controller (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;... | 6.538369 |
module Computer_System_Video_PLL (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire vga_clk_clk, // vga_clk.clk
output wire reset_source_reset // reset_source.reset
);
wire video_pll_locked_export; // video_pll:locked ... | 6.538369 |
module Computer_tb ();
reg clk_in = 0;
reg btn = 1;
wire led;
reg reset = 1;
Computer HACK1 (
.clk_in(clk_in),
.btn(btn),
.led(led),
.reset(reset)
);
always #1 clk_in = ~clk_in;
initial begin
$dumpfile("Computer_tb.vcd");
$dumpvars(0, Computer_tb);
#150 $finish... | 6.718281 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Descri... | 7.09244 |
module compute_a3 (
clk,
rst_n,
run_EN,
a2,
a3,
a3_compute_Done
);
input clk;
input rst_n;
input run_EN;//enable computing impulse. This should be connected to "compute_a2.a2_compute_Done" in higher level module
output reg [9:0] a3; //a1 is a 10 bits long vector, 1 is 1, 0 is -1
out... | 7.325432 |
module compute_acc_mem_V_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 512;
parameter AWIDTH = 11;
parameter MEM_SIZE = 2048;
parameter COL_WIDTH = 8;
parameter NUM_COL = (DWIDTH / COL_WIDTH);
input [AWIDTH-1:0] addr0;
input... | 7.695657 |
module compute_acc_mem_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd512;
parameter AddressRange = 32'd2048;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
... | 7.695657 |
module compute_C_in (
P,
G,
C_in,
C_in_prev
);
input P, G, C_in_prev;
output C_in;
wire G_in, C_out_1;
//Logic to get Carry in
//Ci = Gi + Pi * Ci-1
//Ci = NAND(Ginv , NAND(P, C_in_P))
not1 not1 (
.in1(G),
.out(G_inv)
);
nand2 nand_C1 (
.in1(P),
.in2(C_in_pr... | 7.533568 |
module compute_data_port_m_axi_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-... | 8.325752 |
module compute_data_port_m_axi_fifo #(
parameter DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
) (
input wire sclk,
input wire reset,
input wire sclk_en,
output reg empty_n,
output reg ... | 8.325752 |
module compute_data_port_m_axi_buffer #(
parameter MEM_STYLE = "block",
DATA_WIDTH = 32,
ADDR_WIDTH = 5,
DEPTH = 32
) (
// system signal
input wire clk,
input wire reset,
input wire sclk_en,
// write
output wire if_full_n,
... | 8.325752 |
module compute_data_port_m_axi_decoder #(
parameter DIN_WIDTH = 3
) (
input wire [ DIN_WIDTH-1:0] din,
output reg [2**DIN_WIDTH-1:0] dout
);
integer i;
always @(din) begin
dout = {2 ** DIN_WIDTH{1'b0}};
for (i = 0; i < din; i = i + 1) dout[i] = 1'b1;
end
endmodule
| 8.325752 |
module compute_ext_s (
clk,
m00,
m01,
m10,
m11,
beta0,
beta1,
beta2,
beta3,
beta4,
beta5,
beta6,
beta7,
alpha0,
alpha1,
alpha2,
alpha3,
alpha4,
alpha5,
alpha6,
alpha7,
ext,
systematic
);
input clk;
input [15:0] m11, m10, m0... | 6.576929 |
module compute_sad (
input wire clk,
input wire sad_start,
input wire [255:0] face,
input wire [287:0] group,
output wire sad_done,
output reg [ 10:0] posx,
output reg [ 31:0] sad
);
integer idx;
genvar jdx;
wire sad_active;
wire sad_vali... | 6.742086 |
module Compute_S (
input wire [(`N*`SYMBOL_WIDTH)-1:0] v,
output wire [ `SYMBOL_WIDTH-1:0] s1,
output wire [ `SYMBOL_WIDTH-1:0] s2
);
wire [21:0] H_row_0;
wire [21:0] H_row_1;
wire [21:0] H_row_2;
wire [21:0] H_row_3;
wire [21:0] H_row_4;
wire [21:0] H_row_5;
assign H_row_0 = 21'b11... | 6.723459 |
module compute_uop_mem_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) r... | 7.290898 |
module compute_uop_mem_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0]... | 7.290898 |
module compute_uop_port_m_axi_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1... | 8.097144 |
module compute_uop_port_m_axi_fifo #(
parameter DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
) (
input wire sclk,
input wire reset,
input wire sclk_en,
output reg empty_n,
output reg ... | 8.097144 |
module compute_uop_port_m_axi_buffer #(
parameter MEM_STYLE = "block",
DATA_WIDTH = 32,
ADDR_WIDTH = 5,
DEPTH = 32
) (
// system signal
input wire clk,
input wire reset,
input wire sclk_en,
// write
output wire if_full_n,
... | 8.097144 |
module compute_uop_port_m_axi_decoder #(
parameter DIN_WIDTH = 3
) (
input wire [ DIN_WIDTH-1:0] din,
output reg [2**DIN_WIDTH-1:0] dout
);
integer i;
always @(din) begin
dout = {2 ** DIN_WIDTH{1'b0}};
for (i = 0; i < din; i = i + 1) dout[i] = 1'b1;
end
endmodule
| 8.097144 |
module Comp_16bits(in,out,rst,ref,clk);
input wire [3:0] in, ref;
input wire rst,clk;
output reg out;
always@(posedge clk,posedge rst)
if (rst) out = 1'b0;
else if (in >= ref) out = 1'b1;
else out = 1'b0;
endmodule
| 7.063914 |
module: Comp_16bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Comp_16bits_tb;
// Inputs
reg [15:0] in;
reg rst;
reg [15:0] ref;
// Outputs
wire out;
// Instantiate th... | 8.61569 |
module Comp_1bit (a,
b,
lgn_in,
e_in,
lgn_out,
e_out,
);
input a, b, gin, e_in, lgn_in;
output lgn_out, e_out;
assign lgn_out = (~e_in & lgn_in) | (e_in & ~a & b);
assign e_out = (e_in & ~(... | 6.50315 |
module comp_3_2 (
input in1,
input in2,
input in3,
output sum,
output c
);
assign carry = (in1 & in2) | (in2 & in3) | (in3 & in1);
assign sum = (in1 & in2 & in3) | (in1 & ~in2 & ~in3) | (~in1 & in2 & ~in3) | (~in1 & ~in2 & in3);
endmodule
| 8.063494 |
module comp_4_2 (
input [3:0] in,
input cin,
output sum,
output carry,
output cout
);
wire w1;
full_adder f1 (
in[1:0],
in[2],
w1,
cout
);
full_adder f2 (
{w1, in[3]},
cin,
sum,
carry
);
endmodule
| 7.040503 |
module comp_4_2_4 (
input [3:0] in0,
input [3:0] in1,
input [3:0] in2,
input [3:0] in3,
input cin,
output [1:0] out0,
output [1:0] out1,
output [1:0] out2,
output [1:0] out3,
output cout
);
wire [6:0] w;
comp_4_2 c0 (
in0[3:0],
cin,
out0[1:0],
w[0]
)... | 6.666424 |
module comp_4_2_8 (
input [3:0] in0,
input [3:0] in1,
input [3:0] in2,
input [3:0] in3,
input [3:0] in4,
input [3:0] in5,
input [3:0] in6,
input [3:0] in7,
input cin,
output [1:0] out0,
output [1:0] out1,
output [1:0] out2,
output [1:0] out3,
output [1:0] out4,
... | 7.179612 |
module comp_6b (
a,
b,
equal
);
input wire [5:0] a;
input wire [5:0] b;
output wire equal;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
assign SYNTHESIZED_WIRE_0 = a[0] ^ b[0];... | 7.072287 |
module comp_8bit_tb ();
reg [7:0] in1, in2;
reg en;
wire grt, less, eq;
comparator_8_bit c0 (
in1,
in2,
en,
grt,
less,
eq
);
initial begin
en = 1;
in1 = 8'b10111001;
in2 = 8'b10111001;
#5 in1 = 8'b11010011;
#5 in1 = 8'b10000000;
#5 en = 0;
end... | 7.437192 |
module comp_8_4 (
input [7:0] in,
input [1:0] cin,
output [1:0] sum,
output [1:0] carry,
output [1:0] cout
);
comp_4_2 c0 (
in[3:0],
cin[0],
sum[0],
carry[0],
cout[0]
);
comp_4_2 c1 (
in[7:4],
cin[1],
sum[1],
carry[1],
cout[1]
);... | 6.536775 |
module Comp_Acc_Sum #(
parameter WIDTH = 23
) (
input clk,
rst,
input ena,
input [15:0] a_Re,
a_Im,
input [15:0] a_d_Re,
a_d_Im,
output signed [WIDTH-1:0] sum_out_Im,
sum_out_Re
);
reg [15:0] ia_Re, ia_Im, ia_d_Re, ia_d_Im;
always @(posedge clk) begin
if (rs... | 7.055694 |
module comp_buf #(
parameter N_THREADS = 16, // min.4
parameter N_THREADS_MSB = `MSB(N_THREADS - 1)
) (
input CLK,
input [N_THREADS_MSB : 0] wr_thread_num,
input wr_en,
input [`COMP_DATA1_MSB : 0] wr_data1,
input [`COMP_DATA2_MSB : 0] wr_data2,
input [N_THREADS_MSB : 0] rd_thread_num1... | 6.713435 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/comp_comb/comp_comb.opt (
a0_pad,
a_pad,
b0_pad,
b_pad,
c0_pad,
c_pad,
d0_pad,
d_pad,
e0_pad,
e_pad,
f0_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_... | 6.939825 |
module comp_conv (
a,
a_comp
);
input [7:0] a;
output [7:0] a_comp;
wire [6:0] tmp; //按位取反的幅度位
wire [7:0] y; //负数的补码
assign tmp = ~a[6:0];
assign y[6:0] = tmp + 1; //按位取反加一
assign y[7] = a[7]; //符号位不变
assign a_comp = a[7] ? y : a;
endmodule
| 6.607806 |
module comp_conv (
a,
a_comp
);
input [7:0] a;
output [7:0] a_comp;
//wire[6:0] b ;//按位取反的幅度位
wire [7:0] y; //复数的补码
//assign b=~a[6:0];
//assign y[6:0]=b+1;
//assign y[7]=a[7]; //符号位
assign a_comp = a[7] ? {a[7], ~a[6:0] + 1} : a;
endmodule
| 6.607806 |
module computes values needed to perform a
// cross-correlation between two signal
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module comp_corr
#(
parameter D... | 6.509111 |
module comp_mult_4 #(
parameter DWIDTH = 8 // data width
) (
// system IF
input clk, // system clock
input rst_n, // hw async reset, active low
input sw_rst, // sw sync reset, active high
// input operands val-rdy IF
input op_val, // input operands v... | 7.743379 |
module comp_mult_wrapper #(
parameter DWIDTH = 8, // data width
parameter NO_MULT = 4 // number of multipliers used (1, 2 or 4)
) (
// system IF
input clk, // system clock
input rst_n, // hw async reset, active low
input sw_rst, // sw sync reset, active high
// input operands ... | 7.07071 |
module comp_n #(
parameter DW = 1
) (
input wire [DW-1:0] a,
input wire [DW-1:0] b,
output wire gt,
output wire eq,
output wire lt
);
assign gt = a > b;
assign eq = a == b;
assign lt = ~(gt | eq);
endmodule
| 7.644731 |
module sccomp_tb ();
reg clk, rstn;
reg [ 4:0] reg_sel;
wire [31:0] reg_data;
// instantiation of sccomp
sccomp U_SCCOMP (
.clk(clk),
.rstn(rstn),
.reg_sel(reg_sel),
.reg_data(reg_data)
);
initial begin
// $readmemh( "extendedtest.dat" , U_SCCOMP.U_IM.ROM); // load... | 6.635637 |
module tb;
parameter SIZE = 8, APPROX_BITS = 0;
logic signed [SIZE-1:0] a, b, cin;
logic signed approx_en;
logic signed [SIZE-1:0] sum, cout;
comp_three_two #(
.SIZE(SIZE),
.APPROX_BITS(APPROX_BITS)
) c0 (
a,
b,
cin,
approx_en,
sum,
cout
);
initial beg... | 6.612288 |
module ComSys (
clk_sys,
reset,
first_sequence,
first_result
);
input clk_sys;
input reset;
output [7:0] first_sequence;
output [7:0] first_result;
wire data_seq;
wire [1:0] conv_data;
wire [1:0] il_out;
wire PSK;
wire [1:0] de_PSK;
wire [1:0] error_sig;
wire [1:0] deil_out;
wire... | 6.854537 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module comtrol_module(
sysclk,
rst_n,
iEn,
... | 7.088073 |
module comtrol_unit (
input clk,
input rst_n,
input RUN,
input [31:0] instruction,
input BUS_rdata_valid,
input BUS_write_done,
output [2:0] reg_mux_CS,
output [4:0] reg_rd,
output [4:0] reg_rs1,
output [4:0] reg_rs2,
output reg_wen,
output [1:0] PC_CS,
output PC_EN,
... | 6.6799 |
module Com_2C (
DataA,
DataOut
);
input [7:0] DataA;
output [7:0] DataOut;
reg [7:0] DataOut;
reg [7:0] DA;
always @(DataA) begin
DA = 8'b10000000;
if (DataA[7]) begin
DataOut = -DataA + DA;
end else DataOut = DataA;
end
endmodule
| 7.888684 |
module com_32 (
a,
b,
c,
co,
sum
);
input a, b, c;
output co, sum;
assign co = (a & b) | (c & (a | b));
assign sum = a ^ b ^ c;
endmodule
| 7.875945 |
module com_controller (
input clock_100,
clk,
input pro_enable,
pro_finish,
tx_end,
pro_wr,
uart_wr,
input [7:0] uart_Din,
pro_Din,
input [17:0] uart_addrs,
pro_addrs,
output reg tx_start = 0,
output reg c_clk,
output reg c_wr,
output reg [17:0] c_addrs,
o... | 7.039293 |
module com_s (
input a,
input b,
input c,
input d,
output s,
output ca,
output co
);
wire temp;
assign temp = a ^ b ^ c ^ d;
assign s = temp;
assign ca = d & ~temp;
assign co = (a & b) || (b & c) || (a & c);
endmodule
| 6.509263 |
module COM_to_FIFO (
output reg isFinish,
output [7:0] CRC,
output [3:0] error,
output reg [7:0] fifo_data_out,
output reg fifo_we,
output tx,
input rx,
input fifo_busy,
input clk,
input enable,
input reset,
output reg [2:0] state
);
wire [7:0] fifo_data;
wire isGetS... | 6.846266 |
module is based on Top module: com_to_mem_top.v
// recive comand, addres and data by
// UART and write information in Block RAM
//`include "clock_divider_param.v"
//`include "clock_enable_param.v"
//`include "7segment_v2.v"
//`include "com_to_mem_FSM.v"
//`include "UART_Loopback_module.v"
module com_to_me... | 7.683834 |
module Con2D #(
parameter DATA_WIDTH = 32,
parameter WIDTH = 7,
parameter k1 = 32'b01000000000000000000000000000000,
parameter k2 = 32'b01000000000000000000000000000000,
parameter k3 = 32'b01000000000000000000000000000000,
parameter k4 = 32'b01000000000000000000000000000000,
parameter k5 = 3... | 7.76427 |
module conbus1x4 (
// System
input sys_clk,
input sys_rst,
// Master
output [15:0] m_di,
input [15:0] m_do,
input m_we,
input [15:0] m_a,
// Slave 0
input [15:0] s0_di,
output [15:0] s0_do,
output s0_we,
output [15:0] s0_a,
// Slave 1
input [15:0] s1_di,
o... | 7.922926 |
module conbus_arb (
input sys_clk,
input sys_rst,
input [6:0] req,
output [6:0] gnt
);
parameter [6:0] grant0 = 7'b0000001,
grant1 = 7'b0000010,
grant2 = 7'b0000100,
grant3 = 7'b0001000,
grant4 = 7'b0010000,
grant5 = 7'... | 7.333783 |
module conbus_arb5 (
input sys_clk,
input sys_rst,
input [4:0] req,
output [2:0] gnt
);
reg [2:0] state;
reg [2:0] next_state;
assign gnt = state;
always @(posedge sys_clk) begin
if (sys_rst) state <= 3'd0;
else state <= next_state;
end
always @(*) begin
next_state = state;... | 7.266432 |
module concat10 (
c10out,
instr10to11
);
output wire [3:0] c10out;
input wire [1:0] instr10to11;
assign c10out = {2'b10, instr10to11};
endmodule
| 7.55078 |
module concat11 (
c11out,
instr9to8
);
output wire [3:0] c11out;
input wire [1:0] instr9to8;
assign c11out = {2'b11, instr9to8};
endmodule
| 7.162903 |
module concat25b (
input wire [15:0] data_0,
input wire [ 4:0] data_1,
input wire [ 4:0] data_2,
output wire [25:0] data_out
);
wire [20:0] aux;
assign aux = {data_1, data_0};
assign data_out = {data_2, aux};
endmodule
| 6.897266 |
module concat32b (
input wire [ 3:0] data_0,
input wire [27:0] data_1,
output wire [31:0] data_out
);
assign data_out = {data_0, data_1};
endmodule
| 7.151997 |
module top;
// These should create two ufunc calls each and the zero replication one
// will not be connected to anything.
wire [31:0] var1 = {{0{ufunc(0)}}, ufunc(0)};
wire [31:0] var2 = {ufunc(0), {0{ufunc(0)}}};
integer fres;
initial begin
#1;
if (fres != 4) $display("FAILED, expected fres = 4, ... | 6.661896 |
module Concatenacion (
input [27:0] A1,
input [31:0] A2,
output [31:0] nadd
);
assign nadd = {A2[31:28], A1[27:0]};
endmodule
| 6.762717 |
module concatenador (
input [15:0] i_con,
output reg [31:0] o_con
);
reg [31:0] con; //lo que se le va agregaar 0000000 o 100000
reg [15:0] qui; //para poderle quitar el signo
always @(*) begin
if (i_con[15] == 0) begin
con = 16'd0;
o_con = {con, i_con};
end
if (i_con[15] == 1... | 7.015596 |
module Concatenare (
mantise,
valoare,
out
);
input wire [21:0] mantise;
input wire [5:0] valoare;
output reg [27:0] out;
always @(valoare) begin
out = {valoare, mantise};
end
endmodule
| 6.873172 |
module top_module (
input [4:0] a,
b,
c,
d,
e,
f,
output [7:0] w,
x,
y,
z
);
assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule
| 7.203305 |
module Concatenater (
input [ 31:8] DMEM,
input [ 15:0] rt_value,
input [31:28] PC,
input [ 25:0] index,
output [ 31:0] out_8,
output [ 31:0] out_16,
output [ 31:0] out_J
);
assign out_8 = {DMEM[31:8], rt_value[7:0]};
assign out_16 = {DMEM[31:16], rt_value[15:0]};
assign out_J = ... | 7.38295 |
module Concatenator (
inp,
concatPart,
out
);
parameter NINP = 5;
parameter NCONCATPART = 3;
input [NINP-1:0] inp;
input [NCONCATPART-1:0] concatPart;
output [NCONCATPART+NINP-1:0] out;
assign out = {concatPart, inp};
endmodule
| 7.204134 |
module concatenador (
entrada_AddPC,
entrada_jump,
saida_endJump
);
input [31:0] entrada_AddPC;
input [25:0] entrada_jump;
output wire [31:0] saida_endJump;
assign saida_endJump = {entrada_AddPC[31:26], entrada_jump};
endmodule
| 7.015596 |
module concatJuPC (
out,
J,
PC
);
input [31:0] J, PC;
output [31:0] out;
assign {out} = {{PC[31:28]}, {J[27:0]}};
endmodule
| 7.56166 |
module TBconcat;
reg [31:0] J, PC;
wire [31:0] out;
concatJuPC con (
out,
J,
PC
);
initial begin
$monitor($time, " PC = %b, JumpAddress = %b, Output = %b.", PC, J, out);
#0 PC = 32'hFFFFFFFF;
J = 32'h88000000;
#20 PC = 32'h98765432;
J = 32'h23456789;
#100 $finish;
e... | 7.702263 |
module ActUnit_Connections_InBlockingless_RVSinkless_spec_Axi_rvaCfggreater_Writecomma_Connections_SYN_PORTgreater_PopNB_mgc_out_dreg_v2 (
d,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input [width-1:0] d;
output [width-1:0] z;
wire [width-1:0] z;
assign z = d;
endmodule
| 6.728673 |
module ActUnit_Connections_InBlockingless_RVSinkless_spec_Axi_rvaCfggreater_Writecomma_Connections_SYN_PORTgreater_PopNB_ccs_in_v1 (
idat,
dat
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] idat;
input [width-1:0] dat;
wire [width-1:0] idat;
assign idat = dat;
e... | 6.728673 |
module ActUnit_Connections_InBlockingless_RVSinkless_spec_Axi_rvaCfggreater_Writecomma_Connections_SYN_PORTgreater_PopNB_Connections_InBlocking_RVSink_spec_Axi_rvaCfg_Write_Connections_SYN_PORT_PopNB_core
(
this_val,
this_rdy,
this_msg,
data_data_rsc_z,
data_addr_rsc_z,
data_wstrb_rsc_z,
... | 6.728673 |
module ActUnit_Connections_InBlocking_RVSink_spec_Axi_rvaCfg_Write_Connections_SYN_PORT_PopNB (
this_val,
this_rdy,
this_msg,
data_data_rsc_z,
data_addr_rsc_z,
data_wstrb_rsc_z,
data_rw_rsc_z,
return_rsc_z,
ccs_ccore_start_rsc_dat,
ccs_MIO_clk,
ccs_MIO_arst
);
input this_va... | 6.728673 |
module ActUnit_Connections_InBlockingless_spec_ActVectorTypecomma_Connections_SYN_PORTgreater_PopNB_mgc_out_dreg_v2 (
d,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input [width-1:0] d;
output [width-1:0] z;
wire [width-1:0] z;
assign z = d;
endmodule
| 6.728673 |
module ActUnit_Connections_InBlockingless_spec_ActVectorTypecomma_Connections_SYN_PORTgreater_PopNB_ccs_in_v1 (
idat,
dat
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] idat;
input [width-1:0] dat;
wire [width-1:0] idat;
assign idat = dat;
endmodule
| 6.728673 |
module ActUnit_Connections_InBlockingless_spec_ActVectorTypecomma_Connections_SYN_PORTgreater_PopNB_Connections_InBlocking_spec_ActVectorType_Connections_SYN_PORT_PopNB_core
(
this_val,
this_rdy,
this_msg,
data_data_rsc_z,
return_rsc_z,
ccs_ccore_start_rsc_dat,
ccs_MIO_clk,
ccs_MIO_a... | 6.728673 |
module ActUnit_Connections_InBlocking_spec_ActVectorType_Connections_SYN_PORT_PopNB (
this_val,
this_rdy,
this_msg,
data_data_rsc_z,
return_rsc_z,
ccs_ccore_start_rsc_dat,
ccs_MIO_clk,
ccs_MIO_arst
);
input this_val;
output this_rdy;
input [319:0] this_msg;
output [319:0] data_da... | 6.728673 |
module ActUnit_Connections_OutBlockingless_RVSinkless_spec_Axi_rvaCfggreater_Readcomma_Connections_SYN_PORTgreater_Push_ccs_in_v1 (
idat,
dat
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] idat;
input [width-1:0] dat;
wire [width-1:0] idat;
assign idat = dat;
en... | 6.728673 |
module ActUnit_Connections_OutBlockingless_RVSinkless_spec_Axi_rvaCfggreater_Readcomma_Connections_SYN_PORTgreater_Push_ccs_sync_out_vld_v1 (
vld,
ivld
);
parameter integer rscid = 1;
input ivld;
output vld;
wire vld;
assign vld = ivld;
endmodule
| 6.728673 |
module ActUnit_Connections_OutBlockingless_RVSinkless_spec_Axi_rvaCfggreater_Readcomma_Connections_SYN_PORTgreater_Push_Connections_OutBlocking_RVSink_spec_Axi_rvaCfg_Read_Connections_SYN_PORT_Push_core
(
this_val,
this_rdy,
this_msg,
m_data_rsc_dat,
ccs_ccore_start_rsc_dat,
ccs_ccore_done_s... | 6.728673 |
module ActUnit_Connections_OutBlocking_RVSink_spec_Axi_rvaCfg_Read_Connections_SYN_PORT_Push (
this_val,
this_rdy,
this_msg,
m_data_rsc_dat,
ccs_ccore_start_rsc_dat,
ccs_ccore_done_sync_vld,
ccs_MIO_clk,
ccs_MIO_arst
);
output this_val;
input this_rdy;
output [127:0] this_msg;
in... | 6.728673 |
module ActUnit_Connections_InBlockingless_boolcomma_Connections_SYN_PORTgreater_PopNB_mgc_out_dreg_v2 (
d,
z
);
parameter integer rscid = 1;
parameter integer width = 8;
input [width-1:0] d;
output [width-1:0] z;
wire [width-1:0] z;
assign z = d;
endmodule
| 6.728673 |
module ActUnit_Connections_InBlockingless_boolcomma_Connections_SYN_PORTgreater_PopNB_ccs_in_v1 (
idat,
dat
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] idat;
input [width-1:0] dat;
wire [width-1:0] idat;
assign idat = dat;
endmodule
| 6.728673 |
module ActUnit_Connections_InBlockingless_boolcomma_Connections_SYN_PORTgreater_PopNB_Connections_InBlocking_bool_Connections_SYN_PORT_PopNB_core
(
this_val,
this_rdy,
this_msg,
data_rsc_z,
return_rsc_z,
ccs_ccore_start_rsc_dat,
ccs_MIO_clk,
ccs_MIO_arst
);
input this_val;
output... | 6.728673 |
module ActUnit_Connections_InBlocking_bool_Connections_SYN_PORT_PopNB (
this_val,
this_rdy,
this_msg,
data_rsc_z,
return_rsc_z,
ccs_ccore_start_rsc_dat,
ccs_MIO_clk,
ccs_MIO_arst
);
input this_val;
output this_rdy;
input this_msg;
output data_rsc_z;
output return_rsc_z;
input... | 6.728673 |
module ActUnit_Connections_OutBlockingless_spec_StreamTypecomma_Connections_SYN_PORTgreater_Push_ccs_in_v1 (
idat,
dat
);
parameter integer rscid = 1;
parameter integer width = 8;
output [width-1:0] idat;
input [width-1:0] dat;
wire [width-1:0] idat;
assign idat = dat;
endmodule
| 6.728673 |
module ActUnit_Connections_OutBlockingless_spec_StreamTypecomma_Connections_SYN_PORTgreater_Push_ccs_sync_out_vld_v1 (
vld,
ivld
);
parameter integer rscid = 1;
input ivld;
output vld;
wire vld;
assign vld = ivld;
endmodule
| 6.728673 |
module ActUnit_Connections_OutBlockingless_spec_StreamTypecomma_Connections_SYN_PORTgreater_Push_Connections_OutBlocking_spec_StreamType_Connections_SYN_PORT_Push_core
(
this_val,
this_rdy,
this_msg,
m_data_data_rsc_dat,
m_logical_addr_rsc_dat,
ccs_ccore_start_rsc_dat,
ccs_ccore_done_syn... | 6.728673 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.