code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mult_and_add_spectrum (
input wire clk28, // reloj de 28 MHz (el reloj maestro)
input wire clkreg, // el reloj de acceso a registros de E/S
input wire [7:0] zxuno_regaddr, // el registro de ZXUNO direccionado actualmente
input wire zxuno_regaddr_changed, // a 1 durante un CLK para indicar que ... | 6.686168 |
module mult_and_add (
input wire clk,
input wire signed [15:0] a,
input wire signed [15:0] b,
input wire signed [15:0] c,
output reg signed [15:0] d
);
wire signed [31:0] product;
assign product = a * b;
always @(posedge clk) begin
d <= { product }[22:7] + c;
end
endmodule
| 6.987688 |
module coproc #(
parameter WIDTH = 16
) (
input wire clk,
input wire arstn,
input wire [ 10:0] sel,
input wire go,
output reg [WIDTH-1:0] y,
input wire [WIDTH-1:0] a, // tos
input wire [WIDTH-1:0] b, // nos
input wire [WIDTH-1... | 7.312288 |
module coproc0 (
input sys_clk,
input rst_n,
input is_coproc0_ins,
input [31:0] instr,
input [31:0] mtc0_data,
output is_c0_out,
output [31:0] mfc0_data_o
);
// Support Instructions:
// [DI, Disable Interrupt]
wire [4:0] rs_id = ins_i[25:21];
wire [4:0] rt_id = ins_i[20:... | 7.36332 |
module coprocessor_addr (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [14:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [3... | 6.687351 |
module coprocessor (
clk_clk,
pio_addr_export,
pio_control_export,
pio_data_high_in_port,
pio_data_high_out_port,
pio_data_low_in_port,
pio_data_low_out_port,
pio_riscv_flags_export,
reset_reset_n
);
input clk_clk;
output [14:0] pio_addr_export;
output [5:0] pio_control_export... | 7.32009 |
module coprocessor_io_addr (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [14:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input... | 6.712447 |
module coprocessor_io_control (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [5:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
inp... | 6.712447 |
module coprocessor_io_data_high (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [31:0] in_port;... | 6.712447 |
module coprocessor_io_riscv_flags (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [1:0] in_port;
input reset_n;
wire clk_en;
wire [ 1:0] data_in;
wire [ 1:0] read_mux_out;
reg [31... | 6.712447 |
module coprocessor_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 6.741815 |
module coprocessor_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear... | 6.741815 |
module coprocessor_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg ... | 6.741815 |
module coprocessor_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
in... | 6.741815 |
module coprocessor_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;... | 6.741815 |
module coprocessor_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_cle... | 6.741815 |
module coprocessor_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg... | 6.741815 |
module coprocessor_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
... | 6.741815 |
module coprocessor_Main_Memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "/mnt/hdd1/dev/risc/de0_nano/nios/mem_init.hex";
output [31:0] readdata;
input ... | 7.585161 |
module coprocessor_memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [10:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
inp... | 7.196655 |
module coprocessor_NiosII_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire... | 6.905567 |
module coprocessor_NiosII_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire... | 6.905567 |
module coprocessor_NiosII_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
... | 6.905567 |
module coprocessor_NiosII_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [14:0] cpu_... | 6.905567 |
module coprocessor_NiosII_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_... | 6.905567 |
module coprocessor_NiosII_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or in... | 6.905567 |
module coprocessor_NiosII_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or... | 6.905567 |
module coprocessor_NiosII_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.905567 |
module coprocessor_NiosII_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output... | 6.905567 |
module coprocessor_NiosII_cpu_nios2_performance_monitors;
endmodule
| 6.905567 |
module coprocessor_NiosII_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_a... | 6.905567 |
module coprocessor_NiosII_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input res... | 6.905567 |
module coprocessor_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [2:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [3... | 6.633791 |
module coprocessor_pio_control (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [2:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
in... | 6.633791 |
module coprocessor_pio_high (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [31:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [31:0] in_port;
i... | 6.633791 |
module coprocessor_riscv_rodata (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "riscv_dmem_reset.hex";
output [31:0] readdata;
input [12:0] ... | 7.677654 |
module coprocessor_tb;
reg c = 0;
reg w = 0;
reg r = 1;
reg [4:0] r_reg = 5'd13;
reg [4:0] w_reg = 5'd13;
reg [31:0] in = 0;
reg [34:0] bus = 0;
wire [31:0] out;
coprocessor coprocessor (
.clk(c),
.reset(r),
.enable(w),
.rreg(r_reg),
.wreg(w_reg),
.wdata(in),
... | 6.816072 |
module coproc_at_gpio (
inp0,
inp1,
coproc_result,
coproc_result_ready
);
input [31:0] inp0, inp1;
output [31:0] coproc_result;
output coproc_result_ready;
wire [23:0] mpr, mpd;
wire [47:0] prd;
reg [22:0] mantissa;
reg [ 8:0] exponent;
wire [7:0] aexponent, bexponent;
wire norm_che... | 6.684295 |
module coproc_at_gpio_tb;
reg [31:0] inp0, inp1;
wire [31:0] coproc_result;
wire coproc_result_ready;
coproc_at_gpio multi (
inp0,
inp1,
coproc_result,
coproc_result_ready
);
initial begin
inp0 = 32'b01000000110111110101110000101001; // 6.98
inp1 = 32'b11000010100111011101... | 6.684295 |
module coproc_tb ();
reg clk = 1;
reg rst_n = 0;
reg [10:0] sel = 0;
reg go = 0;
wire [17:0] y;
reg [17:0] tos = 0;
reg [17:0] nos = 0;
reg [17:0] w = 0;
coproc #(18) u1 (
.clk (clk),
.arstn(rst_n),
.sel (sel),
.go (go),
.y (y),
... | 7.200064 |
module. The source of the incoming
commands can also from the copytoken_selector (the recycle unit on the paper). The command from
copytoken_selector will get priority.
Round-Robin is the stategy to do the selection if multiple ram_module have copy commands targeting this selector at the same time
Each... | 7.44164 |
module (with one BRAM inside). The incoming copy BRAM-based command
of this module is from two kind of sources: copy command FIFOs in the parsers and the unsolved command FIFO of the
corresponding ram_module. If the unsolved command FIFO is not full, the command from parser will get the priority, if full,
... | 7.398197 |
module copy_decoder (
input [15:0] instruction,
output source_immediate,
output source_memory,
output [6:0] immediate,
output [4:0] alu_code,
output pre_increment,
output post_increment,
output decrement,
output [2:0] source_select,
output [2:0] destination_select,
output des... | 7.467988 |
module cordic (
clock,
reset,
enable,
xi,
yi,
zi,
xo,
yo,
zo
);
parameter bitwidth = 16;
parameter zwidth = 16;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi, yi;
output [bitwidth-1:0] xo, yo;
input [zwidth-1:0] zi;
output [zwidth-1:0] zo;
reg ... | 6.912729 |
module cordic1 #(
parameter W = 32,
C = 16
) (
input clk,
input rst_n,
input en,
input mode, //mode ==1 rotation mode ==0 vector
input wire signed [W-1:0] x,
input wire signed [W-1:0] y,
input wire signed [W-1:0] z,
output signed [W-1:0] xout,
output signed [W-1:0] yout,
... | 6.964225 |
module cordic_cell #(
parameter count = 8,
W = 32
) (
input signed [W-1:0] x1,
input signed [W-1:0] y1,
input signed [W-1:0] z1,
input signed [W-1:0] memi,
input en,
input clk,
input rst_n,
input mode,
input [1:0] phase,
output reg mode_out,
output reg signed [W-1:0] ... | 7.500432 |
module cordic_pre #(
parameter W = 32
) (
input signed [W-1:0] x,
input signed [W-1:0] y,
input signed [W-1:0] z,
input clk,
input rst_n,
input mode,
input en,
output reg [1:0] phase,
output reg en_out,
output reg mode_out,
output reg signed [W-1:0] xt,
output reg sig... | 7.842539 |
module cordic_final #(
parameter W = 32
) (
input signed [W-1:0] x,
input signed [W-1:0] y,
input signed [W-1:0] z,
input clk,
input rst_n,
input mode,
input en,
input [1:0] phase,
output reg done,
output reg mode_out,
output reg signed [W-1:0] xt,
output reg signed [... | 7.410909 |
module cordic2x8_UV #(
parameter WIDTH = 24,
parameter WIDTH_SHIFT_BIT = 4,
parameter WIDTH_INDEX = 3
) (
input clk,
input rst_n,
input [383:0] data_in,
input ce1,
ce0,
input [WIDTH_SHIFT_BIT-1:0] shift,
count,
input ... | 7.404822 |
module cordic4x2 #(
parameter WIDTH = 24,
parameter WIDTH_SHIFT_BIT = 4,
parameter WIDTH_INDEX = 2
) (
input clk,
input rst_n,
input [WIDTH-1:0] x_in0,
input [WIDTH-1:0] y_in0,
input [WIDTH-1:0] x_in1,
input [WIDTH-1:0] y_in1,
input [WIDTH-1:0] x_i... | 8.434831 |
module Rotator (
input clock,
input reset,
input [17:0] io_in_x,
input [17:0] io_in_y,
input [17:0] io_in_a,
output [17:0] io_out_x,
output [17:0] io_out_y,
output [17:0] io_out_a
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RA... | 6.52574 |
module Rotator_3 (
input clock,
input reset,
input [17:0] io_in_x,
input [17:0] io_in_y,
input [17:0] io_in_a,
output [17:0] io_out_x,
output [17:0] io_out_y,
output [17:0] io_out_a
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _... | 6.689713 |
module Rotator_12 (
input clock,
input reset,
input [17:0] io_in_x,
input [17:0] io_in_y,
input [17:0] io_in_a,
output [17:0] io_out_x,
output [17:0] io_out_y,
output [17:0] io_out_a
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] ... | 6.717198 |
module Rotator_15 (
input clock,
input reset,
input [17:0] io_in_x,
input [17:0] io_in_y,
input [17:0] io_in_a,
output [17:0] io_out_x,
output [17:0] io_out_y
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [17:... | 6.662577 |
module CordicComputer_TB;
reg clk, rstn;
wire rst = ~rstn;
parameter W2 = 18;
`define M_PI (3.14159265358979323846)
`define DTOR (`M_PI / 180.0)
//clock
always begin
clk = 0;
#5;
clk = 1;
#5;
end
//reset
initial begin
rstn = 1'b0;
#8;
rstn = 1'b1;
end
function integ... | 6.843507 |
module cstageg (
clk,
opin,
xin,
yin,
zin,
ain,
opout,
xout,
yout,
zout
);
parameter shift = 1;
parameter zwidth = 16;
parameter width = 16;
parameter def_op = 0;
input clk;
input [1:0] opin;
input [width-1:0] xin, yin;
input [zwidth-1:0] zin, ain;
output reg [1... | 7.641839 |
module cordicg (
clk,
opin,
xin,
yin,
phasein,
xout,
yout,
phaseout
);
parameter width = 19;
parameter def_op = 0;
input clk; // timespec 8.33 ns
input [1:0] opin; // 1 forces y to zero (rect to polar), 0 forces theta to zero (polar to rect), 3 for slave mode
input [width-1:... | 6.946187 |
module main();
// Configure here, or override externally
parameter width = 18;
parameter nstg = 20;
reg clk, rmix;
reg [1:0] op;
initial clk=0;
integer cc;
reg signed [width-1:0] xin;
reg signed [width-1:0] yin=0;
reg signed [width:0] phasein=0;
reg rand1, rand2, rand3, rand4, rand5, rand6, rand7, rand8; // single b... | 6.846398 |
module CordicRotator (clk, rst, en, xi, yi, zi, xo, yo, zo); //省略信号声明
97 wire signed [bitWidth-1:0] sx,sy;
99 assign sx = xi >>> smi; //smi为常量参数，实际实现时为连线
100 assign sy = yi >>> smi; //
103 wire signed [angFracWidth-1:0] at;
105 assign at = appr(0); //具备近似值修正的反正切表，根据smi查表
106
107 always @(posedge clk)
109... | 6.848023 |
module cordic_stage_16 (
clk,
rst_n,
x_in,
y_in,
angle_in,
angle_adj,
x_out,
y_out,
angle_out
);
parameter SHIFT = 1;
// inputs
input clk;
input rst_n;
input signed [16-1:0] x_in;
input signed [16-1:0] y_in;
input signed [16-1:0] angle_in;
input signed [16-1:0] angle... | 7.514853 |
module cordic_10_16 (
clk,
rst_n,
angle_in,
cos_out,
sin_out
);
// inputs
input clk;
input rst_n;
input signed [16-1:0] angle_in;
// outputs
output signed [16-1:0] cos_out;
output signed [16-1:0] sin_out;
// internal signals
reg signed [16-1:0] x_in;
reg signed [16-1:0] y_in... | 6.962032 |
module cordic_12stage_tb;
//test vector to load data from file
localparam TEST_VECTOR_LENGTH = 500;
localparam CLK_PER_2 = 15.68;
localparam ENABLE_PER = 5000;
localparam STROBE_PER = 50;
localparam SIM_TIME = 1e5;
localparam INPUT_WIDTH = 16;
localparam OUTPUT_WIDTH = 16;
localparam Z_INPUT_WIDTH =... | 7.186557 |
module cordic_function1 (
phase,
clk,
reset,
sin,
cos,
Error
);
input [31:0] phase;
input clk;
input reset;
output [31:0] sin;
output [31:0] cos;
output [31:0] Error;
reg signed [31:0] sin;
reg signed [31:0] cos;
reg signed [31:0] Error;
reg signed [31:0] x[16:0], y[16:0], z... | 6.801211 |
module CORDIC_ATAN #(
parameter PHASE_BITS = 16,
parameter AMPLITUDE_BITS = 14,
parameter ITERATIONS = 14
) (
input clk,
input rst,
input wire signed [AMPLITUDE_BITS-1:0] Xin,
input wire signed [AMPLITUDE_BITS-1:0] Yin,
output wire signed [PHASE_BITS-1:0] PHASE,
output wire signed [A... | 6.789416 |
module cordic_block (
valid,
x0,
y0,
z0,
n,
clk,
x,
y,
z
);
input signed [31:0] x0;
input signed [31:0] y0;
input signed [31:0] z0;
input [31:0] n;
input clk;
input valid;
output reg signed [31:0] x;
output reg signed [31:0] y;
output reg signed [31:0] z;
reg [... | 7.391157 |
module cordic_cell #(
parameter SITA = 0,
N = 0
) (
input clk,
rst,
input signed [15:0] x_in,
y_in,
z_in,
output signed [15:0] x_out,
y_out,
z_out
);
reg signed [15:0] x_reg, y_reg, z_reg, x_next, y_next, z_next;
always @(posedge clk, posedge rst) begin
if (rst) begin
... | 7.500432 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/cordic_comb/cordic_comb.opt (
a2_pad,
a3_pad,
a4_pad,
a5_pad,
a6_pad,
ex0_pad,
ex1_pad,
ex2_pad,
ey0_pad,
ey1_pad,
ey2_pad,
v_pad,
x0_pad,
x1_pad,
x2_pad,
x3_pad... | 6.939825 |
module is not parameterized, because LEN could only take 32
module CORDIC_combination_2bit_int_angle_16bit#(parameter LEN = 16)(
input signed [LEN-1:0] angle,
output signed [LEN-1:0] cosh, // X_n in the theory
output signed [LEN-1:0] sinh // Y_n in the theory
);
localparam ... | 7.624852 |
module cordic_cv (
input clock,
input reset,
input [31:0] io_x,
input [31:0] io_y,
output [31:0] io_theta,
output [31:0] io_r
);
wire cordic_cv_unit_clock; // @[Cordic_CV.scala 104:30]
wire cordic_cv_unit_reset; // @[Cordic_CV.scala 104:30]
wire [31:0] cordic_cv_unit_io... | 7.286598 |
module cordic_divide (
input clock,
input reset,
input [31:0] io_x,
input [31:0] io_y,
output [31:0] io_z
);
wire [31:0] unit_io_x; // @[Cordic_LV.scala 131:22]
wire [31:0] unit_io_out; // @[Cordic_LV.scala 131:22]
wire [4:0] unit_io_cnt; // @[Cordic_LV.scala 131:22]
wir... | 7.37034 |
module cordic_cv (
input clock,
input reset,
input [31:0] io_x,
input [31:0] io_y,
output [31:0] io_arctan
);
wire cordic_cv_unit_clock; // @[Cordic_CV.scala 104:30]
wire cordic_cv_unit_reset; // @[Cordic_CV.scala 104:30]
wire [31:0] cordic_cv_unit_io_x; // @[Cordic_CV.sca... | 7.286598 |
module Cordic_core (
rst,
clk,
in_x,
in_y,
in_z,
in_valid,
out_x,
out_z,
out_valid
);
parameter PIPELINE = 15, //Number of iterations
NORM = 20, //normalized bit width
DW = 16, SUB = NORM - DW; //NORM-16
input rst, clk;
input [DW-1:0] in_x, in_y;
input [NORM-1:0] ... | 7.485978 |
module cordic_cr (
input clock,
input reset,
input [31:0] io_theta,
output [31:0] io_sin,
output [31:0] io_cos
);
wire cordic_unit_clock; // @[Cordic_CR.scala 112:45]
wire cordic_unit_reset; // @[Cordic_CR.scala 112:45]
wire [31:0] cordic_unit_io_theta; // @[Cordic_CR.scala... | 7.428394 |
module cordic_cv (
input clock,
input reset,
input [31:0] io_x,
input [31:0] io_y,
output [31:0] io_theta,
output [31:0] io_r,
output [31:0] io_arctan
);
wire cordic_cv_unit_clock; // @[Cordic_CV.scala 104:30]
wire cordic_cv_unit_reset; // @[Cordic_CV.scala 104:30]
... | 7.286598 |
module cordic_divide (
input clock,
input reset,
input [31:0] io_x,
input [31:0] io_y,
output [31:0] io_z
);
wire [31:0] unit_io_x; // @[Cordic_LV.scala 131:22]
wire [31:0] unit_io_out; // @[Cordic_LV.scala 131:22]
wire [4:0] unit_io_cnt; // @[Cordic_LV.scala 131:22]
wir... | 7.37034 |
module Cordic_Divide_Top (
input clk,
input rst_n,
input signed[63:0] y,
input signed[63:0] x,
output signed[63:0] tan,
output finished
);
wire signed [31:0] shift_num_x, shift_num_y, shift_num_y17;
wire signed [63:0] newx, newy, newy_17;
wire flagx, flagy;
Shift shift_x (
... | 7.467602 |
module CORDIC_DIVIDE_UNIT (
rx_rst,
rx_clk,
rx_x,
rx_y,
rx_z,
tx_x,
tx_y,
tx_z
);
parameter shift = 0, para = 17'h08000;
input rx_rst, rx_clk;
input [31:0] rx_y;
input [16:0] rx_z;
input signed [31:0] rx_x;
output [31:0] tx_y;
output [16:0] tx_z;
output [31:0] tx_x;
/... | 6.549286 |
module cordic_div_smaller (
cordic_div_flag,
quotient,
dividend,
division,
clk,
rst,
cordic_div_en
);
parameter M = 1; // dividend shift bits (<<)
parameter N = 13; // division shift bits (>>) M + N = FractionLength
parameter COUNT = 14; //Maximum count number
output reg signed ... | 8.067641 |
module cordic_div_test_small ();
wire signed [15:0] quotient;
wire cordic_div_flag;
reg signed [15:0] dividend;
reg signed [15:0] division;
reg clk;
reg rst;
reg cordic_div_en;
cordic_div_smaller div_exam (
.cordic_div_flag(cordic_div_flag),
.quotient(quotient),
.dividend(dividend),... | 6.710399 |
module CORDIC_elemet #(
parameter ADDRESS_WIDTH = 8,
//Address bit width for z_k
parameter VALUE_WIDTH = 8,
//Output value's bit width, internal one, for x_k and y_k
parameter [ADDRESS_WIDTH - 1 : 0] e_k = 2 ** (ADDRESS_WIDTH - 1),
//The rotation angle in this step
parameter ORDER = 0
)
//Or... | 8.357443 |
module CORDIC_Exponential_8bit #(
parameter XY_SZ = 8
) (
input clk,
input signed [ 31:0] angle,
input signed [XY_SZ-1:0] Xin,
input signed [XY_SZ-1:0] Yin,
output signed [XY_SZ+1:0] exp
);
wire signed [ XY_SZ:0] Xout; // X_n in the theory
wire signed [ XY_SZ:... | 7.967977 |
module cordic_gen #(
parameter INPUT_CLK = 32'd10000000,
parameter OUTPUT_SAMPLE_RATE = 20'd8000
) (
input wire clk,
input wire [15 : 0] out_freq,
input wire [15 : 0] discr_freq,
output wire [15 : 0] sin,
output wire [15 : 0] cos
);
localparam TWO_PI = 20'd524287;
reg [19 ... | 6.930621 |
module CORDIC_Hyperbolic_8bit #(
parameter XY_SZ = 8
) (
input clk,
input signed [XY_SZ-1:0] angle,
input signed [XY_SZ-1:0] Xin,
input signed [XY_SZ-1:0] Yin,
output signed [ XY_SZ:0] Xout, // X_n in the theory
output signed [ XY_SZ:0] Yout // Y_n in the theory... | 7.869215 |
module Cordic_ir_unit (
rst,
clk,
in_x,
in_y,
in_z,
in_valid,
out_x,
out_y,
out_z,
out_valid
);
parameter PIPELINE = 15, //Number of iterations
PIPENOW = 1, NORM = 20, DW = 16, //normalized bit width
SUB = NORM - DW; //NORM-16
input clk, rst;
input signed [NORM-1:0] ... | 6.790677 |
module cordic_iterate #(
parameter SYM_WIDTH = 1,
parameter INT_WIDTH = 1,
parameter DEC_WIDTH = 14,
parameter n = 0, // 表示第n次迭代
parameter coff = 0 // 传入预处理参数
) (
input wire clk,
input wire en,
input wire signed [`FIXED_DATA_WIDTH-1 : 0] x_0,
input wire signed [`FI... | 8.400483 |
module cordic_main (
output [21:0] xout,
output [21:0] yout,
output [21:0] zout,
input [21:0] xo,
input [21:0] yo,
input [21:0] zo,
input clk,
input reset
);
wire [21:0] x[1:15];
wire [21:0] y[1:15];
wire [21:0] z[1:15];
wire [21:0] atanh[1:14];
assign x[1][21:0] = xo;
assign... | 6.788889 |
module.v - Reed Foster
// generates enable and address signals synchronized with CORDIC IP output
module cordic_module
#( // parameters
ADDR_WIDTH = 11, // 2048 point DFT (need to regenerate Block RAM IP when changing this)
PHASE_WIDTH = 24
)( // ports
input clock, reset_n,
inp... | 9.050929 |
module cordic_mux_tb;
reg clk;
integer cc;
reg fail = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("cordic_mux.vcd");
$dumpvars(5, cordic_mux_tb);
end
for (cc = 0; cc < 50; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#5;
end
if (fail) begin
... | 6.552009 |
module cordic_native_tb ();
reg rst_n = 1'b1;
reg I_clk = 1'b0;
reg [13:0] phase = -14'd2048; // -90deg
reg [13:0] inc_phase = 14'd2; //
reg change_phase = 1'b0;
wire [13:0] S_cos;
wire [13:0] S_sin;
initial begin
//#2 change_phase = 1'b1;
//#3 I_clk = 1'b1;
//#5 I_clk = 1'b0;
//#5 I... | 7.255376 |
module cordic_new_stage (
clock,
reset,
xin,
yin,
zin,
xout,
yout,
zout,
atan_const
);
parameter STAGE_NUMBER = 0;
parameter XY_WIDTH = 16;
parameter Z_INPUT_WIDTH = 16;
parameter Z_OUTPUT_WIDTH = 16;
parameter ATAN_WIDTH = 16;
input wire clock;
input wire reset;
i... | 7.460205 |
module cordic_new_stage_tb;
//test vector to load data from file
parameter TEST_VECTOR_LENGTH = 500;
parameter CLK_PER_2 = 10;
parameter ENABLE_PER = 5000;
parameter STROBE_PER = 50;
parameter SIM_TIME = 1e5;
parameter INPUT_WIDTH = 16;
parameter OUTPUT_WIDTH = 16;
parameter Z_INPUT_WIDTH = 16;
pa... | 7.460205 |
module
module shifter #(parameter N = 16)(dataout,datain,shift);
output [N-1:0] dataout;
input [N-1:0] datain;
input [3:0] shift;
assign dataout = datain >> shift;
endmodule
| 7.458004 |
module for control input
module mux21 #(parameter N = 16)(out,a,b,sel);
output reg [N-1:0]out;
input [N-1:0]a,b;
input sel;
always @ (sel or a or b)
case (sel)
1'b0: out <= a;
1'b1: out <= b;
default: out <= b;
endcase
endmodule
| 7.761515 |
module with pipelining
module cordic_pipeline #(parameter N = 16) (clk,init_angle,sine,cosine,end_angle);
input clk;
input [N-1:0]init_angle;
output [N-1:0]sine,cosine;
output [N-1:0]end_angle;
localparam x0 = 16'b0100000000000000;
localparam y0 = 16'b0;
//arc tan values
wire [N-1:0]atan[0:N-1];
assign atan[0... | 8.061085 |
module cordic_pipelined (
input clk,
rst,
input signed [15:0] z,
output signed [15:0] x,
y
);
wire signed [15:0] x0, y0;
wire signed [15:0] x1, y1, z1;
wire signed [15:0] x2, y2, z2;
wire signed [15:0] x3, y3, z3;
wire signed [15:0] x4, y4, z4;
wire signed [15:0] x5, y5, z5;
wire sign... | 7.281399 |
module cordic_pipline #(
parameter DATA_WIDTH_IN = 11,
parameter Pipeline = 16
) (
input clk,
input rst_n,
input signed [DATA_WIDTH_IN - 1 : 0] x_in,
input signed [DATA_WIDTH_IN - 1 : 0] y_in,
input ... | 9.236063 |
module Cordic_post(
rst, clk,
in_x, in_z,
in_valid,
inf,
out_x, out_z,
out_valid
);
parameter PIPELINE = 15,//Number of iterations
NORM = 20,
DW = 16,//normalized bit width
SUB = NORM - DW;//NORM... | 7.329076 |
module CORDIC_SC #(
////////////////////////////////////////////////////
// Parameters
parameter bw_theta = 9,
parameter bw_out = 16
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
Start,
input [bw_theta-1:0] Theta,
output reg [bw_out-1... | 7.197531 |
module cordic_test;
localparam SZ = 16;
reg clk;
reg strobe_in;
reg [31:0] angle;
wire strobe_out;
wire signed [SZ:0] CosOut, SinOut;
reg [15:0] i;
CORDIC_sin_cos sin_cos_uut (
clk,
strobe_in,
angle,
strobe_out,
CosOut,
SinOut
);
initial begin
//$dumpfil... | 7.711689 |
module cordic_sin_tb ();
reg rst_n = 1'b1;
reg I_clk = 1'b0;
reg [13:0] phase = -14'd1024; // -45deg
wire [13:0] S_cos;
wire [13:0] S_sin;
always #5 I_clk = ~I_clk;
cordic_sin cordic_sin_inst (
.I_rst_n(rst_n), // synchronization reset
.I_clk (I_clk), // clock
.I_phase(phase), // p... | 6.947863 |
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