code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module cordic_sqrt_tb ();
reg clk;
reg rst_n;
wire [10 : 0] out;
initial begin
clk = 0;
rst_n = 0;
#2 rst_n = 1;
end
always #1 begin
clk = !clk;
end
cordic_sqrt u_cordic_sqrt (
.clk (clk),
.rst_n (rst_n),
.sqrt_in_0(21'd40),
.sqrt_in_1(21'd... | 6.729968 |
module cordic_stage (
clock,
reset,
enable,
xi,
yi,
zi,
constant,
xo,
yo,
zo
);
parameter bitwidth = 16;
parameter zwidth = 16;
parameter shift = 1;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi, yi;
input [zwidth-1:0] zi;
input [zwidth-1:0] c... | 6.628248 |
module cordic_tb ();
cordic cordic (
clk,
reset,
enable,
xi,
yi,
zi,
xo,
yo,
zo
);
reg reset;
reg clk;
reg enable;
reg [15:0] xi, yi, zi;
initial reset = 1'b1;
initial #1000 reset = 1'b0;
initial clk = 1'b0;
always #50 clk <= ~clk;
initial... | 7.091795 |
module cordic_tb_updated (
input ready,
input cl,
output reg valid,
output reg clk_test
);
reg [31:0] x0;
reg [31:0] y0;
reg [31:0] z0;
wire [31:0] x;
wire [31:0] y;
cordic_updated uut (
.clk(cl),
.x0 (x0),
.y0 (y0),
.z0 (z0),
.X (x),
.Y (y)
);
... | 6.552667 |
module cordic_test;
reg [15:0] Xin, Yin;
reg [31:0] frequency;
wire [21:0] Xout, Yout, out_data_I, out_data_Q;
reg CLK_12MHZ;
//
// Waveform generator
//
initial begin
$write("Starting sim");
CLK_12MHZ = 1'b0;
//Xin = 16'b0; // Xout = -An*Yin*sin(2*PI*f0/fs*k)
//Yin = 16'd10000; /... | 7.711689 |
module CORDIC_TESTBENCH;
localparam width = 16; //width of x and y
// Inputs
reg [width-1:0] Xin, Yin;
reg [31:0] angle;
reg clk;
reg signed [63:0] i;
wire [width-1:0] COSout, SINout;
localparam An = 32000 / 1.647;
initial begin
//set initial values
angle = 'b001101010101010101010101010... | 6.810443 |
module Cordic_Top (
input clk,
input rst_n,
input signed [63:0] a,
b,
p,
q,
output reg signed [63:0] Real,
Imaginary
);
wire start, finished, finished_LV1, finished_LV2, finished_CR;
wire [63:0] mozhi;
wire signed [63:0] angle1, angle, Sin, Cos;
wire signed [63:0] tan_1, tan_2;
... | 6.554197 |
module cordic_trig_pp #(
parameter SYM_WIDTH = 1,
parameter INT_WIDTH = 1,
parameter DEC_WIDTH = 14
) (
input wire clk,
input wire rstn,
input wire data_ready,
input wire signed [`FIXED_DATA_WIDTH-1 : 0] target_rad,
output wire data_valid,
output wire signed [`FIXED_DATA_WIDTH-1 : ... | 7.408968 |
module cordic_vectoring_top #(
parameter data_width = 16,
cordic_steps = 16,
angle_width = 20
) (
input clk,
input nreset,
input enable,
input signed [data_width-1:0] x_vec_in,
input signed [data_width-1:0] y_vec_in,
output wire signed [data_width-1:0] x_vec_out,
output [cordic_s... | 6.623173 |
module cordic_vect_pp #(
parameter SYM_WIDTH = 1,
parameter INT_WIDTH = 1,
parameter DEC_WIDTH = 14
) (
input wire clk,
input wire rstn,
input wire data_ready,
input wire signed [`FIXED_DATA_WIDTH-1 : 0] init_x,
input wire signed [`FIXED_DATA_WIDTH-1 : 0] init_y,
input wire signed [... | 7.140482 |
module cordic_wrap (
input clk, // timespec 8.0 ns
input [18:0] data,
input [3:0] strobe,
input [1:0] osel,
output reg [18:0] d_out
);
// Just grab things at the IOB
reg [18:0] d1 = 0;
reg [ 3:0] s1 = 0;
reg [ 1:0] o1 = 0;
always @(posedge clk) begin
d1 <= data;
s1 <= strobe;
... | 7.712966 |
module int_encoder_dual_bus #(
parameter VECTOR_INT_TABLE_SIZE = 0
) (
input rst,
input [((VECTOR_INT_TABLE_SIZE == 0) ? 0 : VECTOR_INT_TABLE_SIZE-1):0] int_sig_in,
output int_request,
output reg[((VECTOR_INT_TABLE_SIZE > 127) ? 7 :
(VECTOR_INT_TABLE_SIZE > 63) ? 6 :
(VECTOR_INT_TABLE_SIZE... | 7.167849 |
module ImmGenWire (
input [31:0] io_inst,
input [ 2:0] io_sel,
output [31:0] io_out
);
wire [11:0] Iimm = io_inst[31:20]; // @[ImmGen.scala 21:30]
wire [11:0] Simm = {io_inst[31:25], io_inst[11:7]}; // @[ImmGen.scala 22:50]
wire [12:0] Bimm = {
io_inst[31], io_inst[7], io_inst[30:25], io_inst[... | 6.876503 |
module BrCondArea (
input [31:0] io_rs1,
input [31:0] io_rs2,
input [ 2:0] io_br_type,
output io_taken
);
wire [31:0] diff = io_rs1 - io_rs2; // @[BrCond.scala 37:21]
wire neq = diff != 32'h0; // @[BrCond.scala 38:19]
wire eq = ~neq; // @[BrCond.scala 39:14]
wire isSameSign = io_rs1... | 8.510131 |
module int_encoder_single_bus #(
parameter VECTOR_INT_TABLE_SIZE = 0
) (
input [((VECTOR_INT_TABLE_SIZE == 0) ? 0 : VECTOR_INT_TABLE_SIZE-1):0] int_sig_in,
output int_request,
output reg[((VECTOR_INT_TABLE_SIZE > 127) ? 7 :
(VECTOR_INT_TABLE_SIZE > 63) ? 6 :
(VECTOR_INT_TABLE_SIZE > 31) ? 5 :
... | 7.046547 |
module core (
input clk,
input rst
);
wire [31:0] pc_out;
wire [31:0] pc_in;
wire [31:0] if_id_pc_out;
program_counter program_counter (
.clk(clk),
.rst(rst),
.pc_in(pc_in),
.pc_out(pc_out),
.pc_reg_out(if_id_pc_out),
.if_id_ins_valid(if_id_ins_valid)
);
wire [... | 6.619831 |
module Core2_fifo_0_to_1_dual_clock_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
output [31:0] q;
output rdempty;
output rdfull;
output [3:0] rdusedw;
output wrempty;... | 6.985476 |
module Core2_Implementation #(
parameter MUL = 3'b001
) (
//INPUTS
input wire clk,
input wire [127:0] A,
input wire [127:0] B, //change
input wire [ 1:0] select_line,
input wire In_Busy,
//OUTPUT
output wire Out_Busy,
output [255:0] ... | 8.013877 |
module Core2_onchip_memory_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core2_onchip_memory_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 7.123487 |
module Core2_onchip_memory_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core2_onchip_memory_1.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 7.123487 |
module Core2_onchip_shared (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core2_onchip_shared.hex";
output [31:0] readdata;
input [13:0] address;
input [3:0] byteenab... | 7.123487 |
module Core3_fifo_0_to_1_dual_clock_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
output [31:0] q;
output rdempty;
output rdfull;
output [3:0] rdusedw;
output wrempty;... | 7.149568 |
module Core3_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wi... | 6.571355 |
module Core3_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
... | 6.571355 |
module Core3_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0... | 6.571355 |
module Core3_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input ... | 6.571355 |
module Core3_onchip_memory_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core3_onchip_memory_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 7.251691 |
module Core3_onchip_memory_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core3_onchip_memory_1.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 7.251691 |
module Core3_onchip_memory_2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core3_onchip_memory_2.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 7.251691 |
module Core3_onchip_shared (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core3_onchip_shared.hex";
output [31:0] readdata;
input [13:0] address;
input [3:0] byteenab... | 7.251691 |
module Core4_cpu_2_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.833694 |
module Core4_cpu_2_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.833694 |
module Core4_cpu_2_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.833694 |
module Core4_cpu_2_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.833694 |
module Core4_cpu_2_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.833694 |
module Core4_cpu_2_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.833694 |
module Core4_cpu_2_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.833694 |
module Core4_cpu_2_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.833694 |
module Core4_cpu_2_nios2_performance_monitors;
endmodule
| 6.833694 |
module Core4_fifo_0_to_1_dual_clock_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
output [31:0] q;
output rdempty;
output rdfull;
output [3:0] rdusedw;
output wrempty;... | 7.024612 |
module Core4_onchip_memory_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core4_onchip_memory_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 7.120828 |
module Core4_onchip_memory_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core4_onchip_memory_1.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 7.120828 |
module Core4_onchip_memory_2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core4_onchip_memory_2.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 7.120828 |
module Core4_onchip_memory_3 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core4_onchip_memory_3.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 7.120828 |
module Core4_onchip_shared (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core4_onchip_shared.hex";
output [31:0] readdata;
input [13:0] address;
input [3:0] byteenab... | 7.120828 |
module Core4_switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [17:0] in_port;
input reset_n;
wire clk_en;
wire [17:0] data_in;
wire [17:0] read_mux_out;
reg [31:0] readdata... | 6.668099 |
module Core5_cpu_2_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.540219 |
module Core5_cpu_2_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.540219 |
module Core5_cpu_2_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.540219 |
module Core5_cpu_2_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.540219 |
module Core5_cpu_2_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.540219 |
module Core5_cpu_2_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.540219 |
module Core5_cpu_2_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.540219 |
module Core5_cpu_2_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.540219 |
module Core5_cpu_2_nios2_performance_monitors;
endmodule
| 6.540219 |
module Core5_fifo_0_to_1_dual_clock_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
output [31:0] q;
output rdempty;
output rdfull;
output [3:0] rdusedw;
output wrempty;... | 6.958717 |
module Core5_onchip_memory_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core5_onchip_memory_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.883287 |
module Core5_onchip_memory_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core5_onchip_memory_1.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.883287 |
module Core5_onchip_memory_2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core5_onchip_memory_2.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.883287 |
module Core5_onchip_memory_3 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core5_onchip_memory_3.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.883287 |
module Core5_onchip_memory_4 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core5_onchip_memory_4.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.883287 |
module Core5_onchip_memory_5 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core5_onchip_memory_5.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.883287 |
module Core5_onchip_shared (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core5_onchip_shared.hex";
output [31:0] readdata;
input [13:0] address;
input [3:0] byteenab... | 6.883287 |
module HS65_LHS_XOR2X12 (
Z,
A,
B
);
output Z;
input A;
input B;
xor #1 U1 (Z, A, B);
specify
if (!B) (A + => Z) = (`HS65_LHS_XOR2X12_A_R_Z_R_0, `HS65_LHS_XOR2X12_A_F_Z_F_0);
if (B) (A - => Z) = (`HS65_LHS_XOR2X12_A_F_Z_R_1, `HS65_LHS_XOR2X12_A_R_Z_F_1);
if (!A) (B + => Z) = (`HS... | 6.552633 |
module HS65_LHS_XOR2X17 (
Z,
A,
B
);
output Z;
input A;
input B;
xor #1 U1 (Z, A, B);
specify
if (!B) (A + => Z) = (`HS65_LHS_XOR2X17_A_R_Z_R_0, `HS65_LHS_XOR2X17_A_F_Z_F_0);
if (B) (A - => Z) = (`HS65_LHS_XOR2X17_A_F_Z_R_1, `HS65_LHS_XOR2X17_A_R_Z_F_1);
if (!A) (B + => Z) = (`HS... | 6.552633 |
module HS65_LHS_XOR2X23 (
Z,
A,
B
);
output Z;
input A;
input B;
xor #1 U1 (Z, A, B);
specify
if (!B) (A + => Z) = (`HS65_LHS_XOR2X23_A_R_Z_R_0, `HS65_LHS_XOR2X23_A_F_Z_F_0);
if (B) (A - => Z) = (`HS65_LHS_XOR2X23_A_F_Z_R_1, `HS65_LHS_XOR2X23_A_R_Z_F_1);
if (!A) (B + => Z) = (`HS... | 6.552633 |
module HS65_LHS_XOR2X3 (
Z,
A,
B
);
output Z;
input A;
input B;
xor #1 U1 (Z, A, B);
specify
if (!B) (A + => Z) = (`HS65_LHS_XOR2X3_A_R_Z_R_0, `HS65_LHS_XOR2X3_A_F_Z_F_0);
if (B) (A - => Z) = (`HS65_LHS_XOR2X3_A_F_Z_R_1, `HS65_LHS_XOR2X3_A_R_Z_F_1);
if (!A) (B + => Z) = (`HS65_LH... | 6.552633 |
module HS65_LHS_XOR2X6 (
Z,
A,
B
);
output Z;
input A;
input B;
xor #1 U1 (Z, A, B);
specify
if (!B) (A + => Z) = (`HS65_LHS_XOR2X6_A_R_Z_R_0, `HS65_LHS_XOR2X6_A_F_Z_F_0);
if (B) (A - => Z) = (`HS65_LHS_XOR2X6_A_F_Z_R_1, `HS65_LHS_XOR2X6_A_R_Z_F_1);
if (!A) (B + => Z) = (`HS65_LH... | 6.552633 |
module HS65_LH_AND2ABX18 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, A);
not U2 (INTERNAL2, B);
and #1 U3 (Z, INTERNAL1, INTERNAL2);
specify
(A - => Z) = (`HS65_LH_AND2ABX18_A_F_Z_R_0, `HS65_LH_AND2ABX18_A_R_Z_F_0);
(B - => Z) = (`HS65_LH_AND2ABX18_B_F_Z_R_0, `HS6... | 6.52034 |
module HS65_LH_AND2ABX27 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, A);
not U2 (INTERNAL2, B);
and #1 U3 (Z, INTERNAL1, INTERNAL2);
specify
(A - => Z) = (`HS65_LH_AND2ABX27_A_F_Z_R_0, `HS65_LH_AND2ABX27_A_R_Z_F_0);
(B - => Z) = (`HS65_LH_AND2ABX27_B_F_Z_R_0, `HS6... | 6.52034 |
module HS65_LH_AND2ABX35 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, A);
not U2 (INTERNAL2, B);
and #1 U3 (Z, INTERNAL1, INTERNAL2);
specify
(A - => Z) = (`HS65_LH_AND2ABX35_A_F_Z_R_0, `HS65_LH_AND2ABX35_A_R_Z_F_0);
(B - => Z) = (`HS65_LH_AND2ABX35_B_F_Z_R_0, `HS6... | 6.52034 |
module HS65_LH_AND2ABX9 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, A);
not U2 (INTERNAL2, B);
and #1 U3 (Z, INTERNAL1, INTERNAL2);
specify
(A - => Z) = (`HS65_LH_AND2ABX9_A_F_Z_R_0, `HS65_LH_AND2ABX9_A_R_Z_F_0);
(B - => Z) = (`HS65_LH_AND2ABX9_B_F_Z_R_0, `HS65_LH... | 6.52034 |
module HS65_LH_BFX106 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX106_A_R_Z_R, `HS65_LH_BFX106_A_F_Z_F);
endspecify
endmodule
| 6.620234 |
module HS65_LH_BFX142 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX142_A_R_Z_R, `HS65_LH_BFX142_A_F_Z_F);
endspecify
endmodule
| 6.570782 |
module HS65_LH_BFX18 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX18_A_R_Z_R, `HS65_LH_BFX18_A_F_Z_F);
endspecify
endmodule
| 6.570418 |
module HS65_LH_BFX2 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX2_A_R_Z_R, `HS65_LH_BFX2_A_F_Z_F);
endspecify
endmodule
| 6.955095 |
module HS65_LH_BFX22 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX22_A_R_Z_R, `HS65_LH_BFX22_A_F_Z_F);
endspecify
endmodule
| 6.557097 |
module HS65_LH_BFX27 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX27_A_R_Z_R, `HS65_LH_BFX27_A_F_Z_F);
endspecify
endmodule
| 6.538538 |
module HS65_LH_BFX31 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX31_A_R_Z_R, `HS65_LH_BFX31_A_F_Z_F);
endspecify
endmodule
| 6.633815 |
module HS65_LH_BFX35 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX35_A_R_Z_R, `HS65_LH_BFX35_A_F_Z_F);
endspecify
endmodule
| 6.731138 |
module HS65_LH_BFX40 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX40_A_R_Z_R, `HS65_LH_BFX40_A_F_Z_F);
endspecify
endmodule
| 6.825231 |
module HS65_LH_BFX44 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX44_A_R_Z_R, `HS65_LH_BFX44_A_F_Z_F);
endspecify
endmodule
| 6.705935 |
module HS65_LH_BFX49 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX49_A_R_Z_R, `HS65_LH_BFX49_A_F_Z_F);
endspecify
endmodule
| 6.788982 |
module HS65_LH_BFX53 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX53_A_R_Z_R, `HS65_LH_BFX53_A_F_Z_F);
endspecify
endmodule
| 6.559196 |
module HS65_LH_BFX9 (
Z,
A
);
output Z;
input A;
buf #1 U1 (Z, A);
specify
(A + => Z) = (`HS65_LH_BFX9_A_R_Z_R, `HS65_LH_BFX9_A_F_Z_F);
endspecify
endmodule
| 6.563651 |
module HS65_LH_ITHX20 (
Z,
A,
E
);
output Z;
input A;
input E;
notif1 #1 U1 (Z, A, E);
specify
(A - => Z) = (`HS65_LH_ITHX20_A_F_Z_R_1, `HS65_LH_ITHX20_A_R_Z_F_1);
(E => Z) = (`HS65_LH_ITHX20_E_F_Z_LZ_1,`HS65_LH_ITHX20_E_F_Z_HZ_0,`HS65_LH_ITHX20_E_F_Z_LZ_1,`HS65_LH_ITHX20_E_R_Z_ZH_0,... | 7.054828 |
module HS65_LH_ITHX25 (
Z,
A,
E
);
output Z;
input A;
input E;
notif1 #1 U1 (Z, A, E);
specify
(A - => Z) = (`HS65_LH_ITHX25_A_F_Z_R_1, `HS65_LH_ITHX25_A_R_Z_F_1);
(E => Z) = (`HS65_LH_ITHX25_E_F_Z_LZ_1,`HS65_LH_ITHX25_E_F_Z_HZ_0,`HS65_LH_ITHX25_E_F_Z_LZ_1,`HS65_LH_ITHX25_E_R_Z_ZH_0,... | 7.054828 |
module HS65_LH_ITHX30 (
Z,
A,
E
);
output Z;
input A;
input E;
notif1 #1 U1 (Z, A, E);
specify
(A - => Z) = (`HS65_LH_ITHX30_A_F_Z_R_1, `HS65_LH_ITHX30_A_R_Z_F_1);
(E => Z) = (`HS65_LH_ITHX30_E_F_Z_LZ_1,`HS65_LH_ITHX30_E_F_Z_HZ_0,`HS65_LH_ITHX30_E_F_Z_LZ_1,`HS65_LH_ITHX30_E_R_Z_ZH_0,... | 6.607724 |
module HS65_LH_IVX106 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX106_A_F_Z_R, `HS65_LH_IVX106_A_R_Z_F);
endspecify
endmodule
| 6.710772 |
module HS65_LH_IVX13 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX13_A_F_Z_R, `HS65_LH_IVX13_A_R_Z_F);
endspecify
endmodule
| 6.631623 |
module HS65_LH_IVX18 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX18_A_F_Z_R, `HS65_LH_IVX18_A_R_Z_F);
endspecify
endmodule
| 6.533392 |
module HS65_LH_IVX2 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX2_A_F_Z_R, `HS65_LH_IVX2_A_R_Z_F);
endspecify
endmodule
| 6.909235 |
module HS65_LH_IVX27 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX27_A_F_Z_R, `HS65_LH_IVX27_A_R_Z_F);
endspecify
endmodule
| 6.65985 |
module HS65_LH_IVX31 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX31_A_F_Z_R, `HS65_LH_IVX31_A_R_Z_F);
endspecify
endmodule
| 6.648586 |
module HS65_LH_IVX40 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX40_A_F_Z_R, `HS65_LH_IVX40_A_R_Z_F);
endspecify
endmodule
| 6.749296 |
module HS65_LH_IVX44 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX44_A_F_Z_R, `HS65_LH_IVX44_A_R_Z_F);
endspecify
endmodule
| 6.725132 |
module HS65_LH_IVX49 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX49_A_F_Z_R, `HS65_LH_IVX49_A_R_Z_F);
endspecify
endmodule
| 6.585888 |
module HS65_LH_IVX53 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX53_A_F_Z_R, `HS65_LH_IVX53_A_R_Z_F);
endspecify
endmodule
| 6.640542 |
module HS65_LH_IVX62 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LH_IVX62_A_F_Z_R, `HS65_LH_IVX62_A_R_Z_F);
endspecify
endmodule
| 6.69628 |
module HS65_LH_NOR2X13 (
Z,
A,
B
);
output Z;
input A;
input B;
or U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LH_NOR2X13_A_F_Z_R_0, `HS65_LH_NOR2X13_A_R_Z_F_0);
(B - => Z) = (`HS65_LH_NOR2X13_B_F_Z_R_0, `HS65_LH_NOR2X13_B_R_Z_F_0);
endspecify
e... | 6.527857 |
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