code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module HS65_LS_IVX49 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LS_IVX49_A_F_Z_R, `HS65_LS_IVX49_A_R_Z_F);
endspecify
endmodule
| 6.520768 |
module HS65_LS_IVX53 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LS_IVX53_A_F_Z_R, `HS65_LS_IVX53_A_R_Z_F);
endspecify
endmodule
| 6.501507 |
module HS65_LS_IVX62 (
Z,
A
);
output Z;
input A;
not #1 U1 (Z, A);
specify
(A - => Z) = (`HS65_LS_IVX62_A_F_Z_R, `HS65_LS_IVX62_A_R_Z_F);
endspecify
endmodule
| 6.701799 |
module HS65_LS_NAND2AX14 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, B);
or #1 U2 (Z, A, INTERNAL1);
specify
(A + => Z) = (`HS65_LS_NAND2AX14_A_R_Z_R_1, `HS65_LS_NAND2AX14_A_F_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2AX14_B_F_Z_R_0, `HS65_LS_NAND2AX14_B_R_Z_F_0);
end... | 6.54738 |
module HS65_LS_NAND2AX21 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, B);
or #1 U2 (Z, A, INTERNAL1);
specify
(A + => Z) = (`HS65_LS_NAND2AX21_A_R_Z_R_1, `HS65_LS_NAND2AX21_A_F_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2AX21_B_F_Z_R_0, `HS65_LS_NAND2AX21_B_R_Z_F_0);
end... | 6.54738 |
module HS65_LS_NAND2AX29 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, B);
or #1 U2 (Z, A, INTERNAL1);
specify
(A + => Z) = (`HS65_LS_NAND2AX29_A_R_Z_R_1, `HS65_LS_NAND2AX29_A_F_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2AX29_B_F_Z_R_0, `HS65_LS_NAND2AX29_B_R_Z_F_0);
end... | 6.54738 |
module HS65_LS_NAND2AX4 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, B);
or #1 U2 (Z, A, INTERNAL1);
specify
(A + => Z) = (`HS65_LS_NAND2AX4_A_R_Z_R_1, `HS65_LS_NAND2AX4_A_F_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2AX4_B_F_Z_R_0, `HS65_LS_NAND2AX4_B_R_Z_F_0);
endspeci... | 6.54738 |
module HS65_LS_NAND2AX7 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, B);
or #1 U2 (Z, A, INTERNAL1);
specify
(A + => Z) = (`HS65_LS_NAND2AX7_A_R_Z_R_1, `HS65_LS_NAND2AX7_A_F_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2AX7_B_F_Z_R_0, `HS65_LS_NAND2AX7_B_R_Z_F_0);
endspeci... | 6.54738 |
module HS65_LS_NAND2X11 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X11_A_F_Z_R_1, `HS65_LS_NAND2X11_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X11_B_F_Z_R_1, `HS65_LS_NAND2X11_B_R_Z_F_1);
endspec... | 6.54738 |
module HS65_LS_NAND2X14 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X14_A_F_Z_R_1, `HS65_LS_NAND2X14_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X14_B_F_Z_R_1, `HS65_LS_NAND2X14_B_R_Z_F_1);
endspec... | 6.54738 |
module HS65_LS_NAND2X2 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X2_A_F_Z_R_1, `HS65_LS_NAND2X2_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X2_B_F_Z_R_1, `HS65_LS_NAND2X2_B_R_Z_F_1);
endspecify
... | 6.54738 |
module HS65_LS_NAND2X21 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X21_A_F_Z_R_1, `HS65_LS_NAND2X21_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X21_B_F_Z_R_1, `HS65_LS_NAND2X21_B_R_Z_F_1);
endspec... | 6.54738 |
module HS65_LS_NAND2X29 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X29_A_F_Z_R_1, `HS65_LS_NAND2X29_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X29_B_F_Z_R_1, `HS65_LS_NAND2X29_B_R_Z_F_1);
endspec... | 6.54738 |
module HS65_LS_NAND2X4 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X4_A_F_Z_R_1, `HS65_LS_NAND2X4_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X4_B_F_Z_R_1, `HS65_LS_NAND2X4_B_R_Z_F_1);
endspecify
... | 6.54738 |
module HS65_LS_NAND2X43 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X43_A_F_Z_R_1, `HS65_LS_NAND2X43_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X43_B_F_Z_R_1, `HS65_LS_NAND2X43_B_R_Z_F_1);
endspec... | 6.54738 |
module HS65_LS_NAND2X5 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X5_A_F_Z_R_1, `HS65_LS_NAND2X5_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X5_B_F_Z_R_1, `HS65_LS_NAND2X5_B_R_Z_F_1);
endspecify
... | 6.54738 |
module HS65_LS_NAND2X57 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X57_A_F_Z_R_1, `HS65_LS_NAND2X57_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X57_B_F_Z_R_1, `HS65_LS_NAND2X57_B_R_Z_F_1);
endspec... | 6.54738 |
module HS65_LS_NAND2X7 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (INTERNAL1, A, B);
not #1 U2 (Z, INTERNAL1);
specify
(A - => Z) = (`HS65_LS_NAND2X7_A_F_Z_R_1, `HS65_LS_NAND2X7_A_R_Z_F_1);
(B - => Z) = (`HS65_LS_NAND2X7_B_F_Z_R_1, `HS65_LS_NAND2X7_B_R_Z_F_1);
endspecify
... | 6.54738 |
module Core6_cpu_2_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.517337 |
module Core6_cpu_2_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.517337 |
module Core6_cpu_2_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.517337 |
module Core6_cpu_2_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.517337 |
module Core6_cpu_2_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.517337 |
module Core6_cpu_2_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.517337 |
module Core6_cpu_2_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.517337 |
module Core6_cpu_2_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.517337 |
module Core6_cpu_2_nios2_performance_monitors;
endmodule
| 6.517337 |
module Core6_fifo_0_to_1_dual_clock_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
output [31:0] q;
output rdempty;
output rdfull;
output [3:0] rdusedw;
output wrempty;... | 6.7658 |
module Core6_onchip_memory_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core6_onchip_memory_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.611728 |
module Core6_onchip_memory_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core6_onchip_memory_1.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.611728 |
module Core6_onchip_memory_2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core6_onchip_memory_2.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.611728 |
module Core6_onchip_memory_3 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core6_onchip_memory_3.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.611728 |
module Core6_onchip_memory_4 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core6_onchip_memory_4.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.611728 |
module Core6_onchip_memory_5 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core6_onchip_memory_5.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.611728 |
module Core6_onchip_shared (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core6_onchip_shared.hex";
output [31:0] readdata;
input [13:0] address;
input [3:0] byteenab... | 6.611728 |
module Core7_fifo_0_to_1_dual_clock_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
output [31:0] q;
output rdempty;
output rdfull;
output [3:0] rdusedw;
output wrempty;... | 6.849435 |
module Core7_onchip_memory_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core7_onchip_memory_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.958209 |
module Core7_onchip_memory_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core7_onchip_memory_1.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.958209 |
module Core7_onchip_memory_2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core7_onchip_memory_2.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.958209 |
module Core7_onchip_memory_3 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core7_onchip_memory_3.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.958209 |
module Core7_onchip_memory_4 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core7_onchip_memory_4.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.958209 |
module Core7_onchip_memory_5 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core7_onchip_memory_5.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.958209 |
module Core7_onchip_memory_6 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core7_onchip_memory_6.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.958209 |
module Core7_onchip_shared (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core7_onchip_shared.hex";
output [31:0] readdata;
input [13:0] address;
input [3:0] byteenab... | 6.958209 |
module Core8_cpu_1_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.609753 |
module Core8_cpu_1_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.609753 |
module Core8_cpu_1_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.609753 |
module Core8_cpu_1_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.609753 |
module Core8_cpu_1_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.609753 |
module Core8_cpu_1_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.609753 |
module Core8_cpu_1_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.609753 |
module Core8_cpu_1_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.609753 |
module Core8_cpu_1_nios2_performance_monitors;
endmodule
| 6.609753 |
module Core8_cpu_2_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.989602 |
module Core8_cpu_2_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.989602 |
module Core8_cpu_2_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.989602 |
module Core8_cpu_2_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.989602 |
module Core8_cpu_2_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.989602 |
module Core8_cpu_2_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.989602 |
module Core8_cpu_2_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.989602 |
module Core8_cpu_2_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.989602 |
module Core8_cpu_2_nios2_performance_monitors;
endmodule
| 6.989602 |
module Core8_cpu_3_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.598697 |
module Core8_cpu_3_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.598697 |
module Core8_cpu_3_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.598697 |
module Core8_cpu_3_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.598697 |
module Core8_cpu_3_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.598697 |
module Core8_cpu_3_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.598697 |
module Core8_cpu_3_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.598697 |
module Core8_cpu_3_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.598697 |
module Core8_cpu_3_nios2_performance_monitors;
endmodule
| 6.598697 |
module Core8_cpu_4_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.91363 |
module Core8_cpu_4_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.91363 |
module Core8_cpu_4_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.91363 |
module Core8_cpu_4_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.91363 |
module Core8_cpu_4_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.91363 |
module Core8_cpu_4_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.91363 |
module Core8_cpu_4_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.91363 |
module Core8_cpu_4_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.91363 |
module Core8_cpu_4_nios2_performance_monitors;
endmodule
| 6.91363 |
module Core8_cpu_5_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.749762 |
module Core8_cpu_5_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.749762 |
module Core8_cpu_5_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.749762 |
module Core8_cpu_5_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.749762 |
module Core8_cpu_5_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.749762 |
module Core8_cpu_5_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.749762 |
module Core8_cpu_5_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.749762 |
module Core8_cpu_5_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.749762 |
module Core8_cpu_5_nios2_performance_monitors;
endmodule
| 6.749762 |
module Core8_cpu_6_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.758239 |
module Core8_cpu_6_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.758239 |
module Core8_cpu_6_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.758239 |
module Core8_cpu_6_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.758239 |
module Core8_cpu_6_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.758239 |
module Core8_cpu_6_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.758239 |
module Core8_cpu_6_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.758239 |
module Core8_cpu_6_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.758239 |
module Core8_cpu_6_nios2_performance_monitors;
endmodule
| 6.758239 |
module Core8_cpu_7_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocire... | 6.916196 |
module Core8_cpu_7_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: be... | 6.916196 |
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