code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Core8_cpu_7_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
... | 6.916196 |
module Core8_cpu_7_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
assign switch_for... | 6.916196 |
module Core8_cpu_7_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count == 3)) fifowp_... | 6.916196 |
module Core8_cpu_7_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)... | 6.916196 |
module Core8_cpu_7_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthes... | 6.916196 |
module Core8_cpu_7_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
tr... | 6.916196 |
module Core8_cpu_7_nios2_performance_monitors;
endmodule
| 6.916196 |
module Core8_fifo_0_to_1_dual_clock_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw
);
output [31:0] q;
output rdempty;
output rdfull;
output [3:0] rdusedw;
output wrempty;... | 6.680339 |
module Core8_onchip_memory_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core8_onchip_memory_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.761822 |
module Core8_onchip_memory_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core8_onchip_memory_1.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.761822 |
module Core8_onchip_memory_2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core8_onchip_memory_2.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.761822 |
module Core8_onchip_memory_3 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core8_onchip_memory_3.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.761822 |
module Core8_onchip_memory_4 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core8_onchip_memory_4.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.761822 |
module Core8_onchip_memory_5 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core8_onchip_memory_5.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.761822 |
module Core8_onchip_memory_6 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core8_onchip_memory_6.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.761822 |
module Core8_onchip_memory_7 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core8_onchip_memory_7.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byte... | 6.761822 |
module Core8_onchip_shared (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "Core8_onchip_shared.hex";
output [31:0] readdata;
input [13:0] address;
input [3:0] byteenab... | 6.761822 |
module CoreAHBtoAPB3_PenableScheduler (
input wire HCLK,
input wire HRESETN,
input wire setPenable,
input wire clrPenable,
output reg PENABLE
);
parameter SYNC_RESET = 0;
//-----------------------------------------------------------------
// Local parameters
//-------------------------... | 8.128145 |
module COREBOOTSTRAP_BOOT_RESET (
// input ports
HCLK,
PO_RESETN,
EXT_RESETN,
SYS_RESET_REQ,
// output ports
HRESETN
);
parameter RST_POR_DURATION = 100;
parameter RST_EXTPROC_DURATION = 1000;
// input ports
input HCLK;
wire HCLK;
input PO_RESETN;
wire PO_RESETN;
input E... | 6.858918 |
module COREBOOTSTRAP_CKSUM_CTRL (
HCLK,
cks_data,
cksum_done,
latch_sdi,
HRESETN,
CKSUM_ERR,
boot_sdi,
rd_all_done
);
parameter CKSUM_EN = 0; // Whether a checksum is to be calculated, based on copied bootcode, and compared against stored checksum.
// Port: Port_1
input HCLK; ... | 6.858918 |
module COREBOOTSTRAP_SPI_SEL (
HOST_SCK,
HOST_SDI,
HOST_SDO,
HOST_SS,
FLASH_SCK,
FLASH_SDI,
FLASH_SDO,
FLASH_SS,
PROC_SYS_RESETN,
boot_sck,
boot_sdi,
boot_sdo,
boot_ss,
sel_host
);
// Port: CoreSPI_IF
input HOST_SCK; // SPI clock from the hos... | 6.858918 |
module coregfile (
input wire clk, // main clock
// debug
`ifdef DEBUG
input wire [3:0] debug_addr, // debug address
output wire [31:0] debug_data_cp, // debug data
`endif
// read channel
input wire [3:0] addr_r_cp,
output wire [31:0] data_r_cp,
// write channel W
input wire en_w... | 7.174318 |
module coreid (
input wire clk,
input wire rst_n,
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire regaddr_changed,
output reg [7:0] dout,
output wire oe_n
);
reg [7:0] text[0:15];
integer i;
initial begin
for (i = 0; i < 16; i = i + 1) text[i] = 8'h00;
text[0] ... | 6.63339 |
module contains the MAC array, L0, output FIFO and SFU
//? clk - Master clock
//? reset - Master reset, high enable
//? inst[33:0] - All extra signals
//? 6 - ofifo_rd
//? 5 - ififo_wr
//? 4 - ififo_rd
//? 3 - l0_rd
//? 2 - l0_wr
//? 1 - execute
//? 0 - load
module corelet #(
parameter... | 7.358377 |
module W0RM_CoreMemory #(
parameter BLOCK_RAM = 0,
parameter ADDR_WIDTH = 32,
parameter INST_WIDTH = 16,
parameter DATA_WIDTH = 32,
parameter BASE_ADDR = 32'h20000000
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] inst_addr,
input wire inst_read,
inst_valid_in,... | 6.656269 |
module CorePLL (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire locked // locked.export
);
CorePLL_0002 corepll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.o... | 7.250765 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_ARBITER (
input clk,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [6:0] io_in_0_bits_idx,
input io_in_0_bits_way_en,
output io_in_1_ready,
input io_in_1_valid,
input [6:0] io_in_1_bits_idx,
input io_in_1_bits_... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_ARBITER_1 (
input clk,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [6:0] io_in_0_bits_idx,
input io_in_0_bits_way_en,
input [18:0] io_in_0_bits_data_tag,
input [1:0] io_in_0_bits_data_coh_state,
output io_in_1_re... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_ARBITER_2 (
input clk,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [12:0] io_in_0_bits_addr,
input io_in_0_bits_write,
input [63:0] io_in_0_bits_wdata,
input [7:0] io_in_0_bits_wmask,
input io_in_0_bits_way_en,
... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_CLIENT_UNCACHED_TILE_LINK_IO_ARBITER (
input clk,
input reset,
output io_in_0_acquire_ready,
input io_in_0_acquire_valid,
input [25:0] io_in_0_acquire_bits_addr_block,
input io_in_0_acquire_bits_client_xact_id,
input [2:0] io_in_0_acquire... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_CLIENT_UNCACHED_TILE_LINK_IO_ARBITER_1 (
input clk,
input reset,
output io_in_0_acquire_ready,
input io_in_0_acquire_valid,
input [25:0] io_in_0_acquire_bits_addr_block,
input [1:0] io_in_0_acquire_bits_client_xact_id,
input [2:0] io_in_0... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_FINISH_QUEUE (
input clk,
input reset,
output io_enq_ready,
input io_enq_valid,
input [1:0] io_enq_bits_manager_xact_id,
input io_enq_bits_manager_id,
input io_deq_ready,
output io_deq_valid,
output [1:0] io_deq_bits_manager_xact_... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_FLOW_THROUGH_SERIALIZER (
input clk,
input reset,
output io_in_ready,
input io_in_valid,
input [2:0] io_in_bits_addr_beat,
input io_in_bits_client_xact_id,
input [1:0] io_in_bits_manager_xact_id,
input io_in_bits_is_builtin_type,
... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_HELLA_CACHE_ARBITER (
input clk,
input reset,
output io_requestor_0_req_ready,
input io_requestor_0_req_valid,
input [31:0] io_requestor_0_req_bits_addr,
input [8:0] io_requestor_0_req_bits_tag,
input [4:0] io_requestor_0_req_bits_cmd,
... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_ID_MAPPER (
input clk,
input reset,
input io_req_valid,
output io_req_ready,
input [1:0] io_req_in_id,
output [4:0] io_req_out_id,
input io_resp_valid,
output io_resp_matches,
input [4:0] io_resp_out_id,
output [1:0] io_resp_i... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_LEVEL_GATEWAY (
input clk,
input reset,
input io_interrupt,
output io_plic_valid,
input io_plic_ready,
input io_plic_complete
);
reg inFlight;
reg [31:0] GEN_2;
wire T_6;
wire GEN_0;
wire GEN_1;
wire T_10;
wire T_11;
assi... | 6.544407 |
module PROC_SUBSYSTEM_CORERISCV_AXI4_0_CORERISCV_AXI4_METADATA_ARRAY (
input clk,
input reset,
output io_read_ready,
input io_read_valid,
input [6:0] io_read_bits_idx,
input io_read_bits_way_en,
output io_write_ready,
input io_write_valid,
input [6:0] io_write_bits_idx,
input io_... | 6.544407 |
module corescore_alhambra_II (
input i_clk,
output wire locked_led,
output wire o_uart_tx
);
wire clk;
wire locked;
//Mirror locked PLL to LED
assign locked_led = locked;
//Create a 16MHz clock from 12MHz using PLL
pll pll48 (
.clock_in (i_clk),
.clock_out(clk),
.locked (l... | 8.726717 |
module corescore_arty_a7 (
input wire i_clk,
output wire q,
output wire o_uart_tx
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
arty_a7_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
wire [7:0] tdata;
wire tlast;
wir... | 8.100234 |
module corescore_chameleon96 (
input wire i_clk,
input wire i_rst_n,
output wire q,
output wire uart_txd
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = uart_txd;
de0_nano_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(!i_rst_n),
.o_clk(clk),
.o_rst(rst)... | 8.356421 |
module corescore_cisco_hwic_3g_cdma (
input wire clk25,
output wire led0,
output wire uart_txd,
output wire uart_drv_ena_,
output wire uart_drv_sd_
);
wire clk;
wire rst;
//Mirror UART output to LED
assign led0 = uart_txd;
assign uart_drv_ena_ = 1'b0; // ADM3222 EN_: Set 0 to ... | 8.19906 |
module corescore_cmod_a7 (
input wire i_clk,
output wire q,
output wire o_uart_tx
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
cmod_a7_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
... | 7.577541 |
module corescore_colorlight (
input wire i_clk,
input wire btn0,
output wire o_uart_tx
);
wire clk;
wire rst;
corescore_colorlight_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(!btn0),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
wire [7:0] ... | 7.238249 |
module corescore_colorlight_clock_gen (
input i_clk,
input i_rst,
output o_clk,
output o_rst
);
wire locked;
reg [1:0] rst_reg;
always @(posedge o_clk)
if (i_rst) rst_reg <= 2'b11;
else rst_reg <= {!locked, rst_reg[1]};
assign o_rst = rst_reg[0];
pll pll (
.clki (i_clk),
... | 7.238249 |
module corescore_cyc1000 (
input wire i_clk,
output wire q,
output wire o_uart_tx
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
cyc1000_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
... | 8.74097 |
module corescore_de0_nano (
input wire i_clk,
input wire i_rst_n,
output wire q,
output wire o_uart_tx
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
de0_nano_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(!i_rst_n),
.o_clk(clk),
.o_rst(rst)
... | 8.08743 |
module corescore_de10_nano (
input wire i_clk,
input wire i_rst_n,
output wire q,
output wire uart_txd
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = uart_txd;
de0_nano_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(!i_rst_n),
.o_clk(clk),
.o_rst(rst)
... | 8.207761 |
module corescore_de5_net (
input wire i_clk,
input wire i_rst_n,
output wire o_led_n,
output wire o_hex0_dp_n,
output wire o_hex1_dp_n,
output wire o_uart_txd,
output wire o_rs422_de,
output wire o_rs422_re_n,
output wire o_rs422_te
);
wire clk;
wire rst;
// Mirror UART out... | 8.055301 |
module corescore_deca (
input wire i_clk,
input wire i_rst_n,
output wire q,
output wire uart_txd
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = uart_txd;
de0_nano_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(!i_rst_n),
.o_clk(clk),
.o_rst(rst)
);
... | 8.263903 |
module corescore_ebaz4205 (
input wire i_clk,
output wire o_uart_tx
);
wire clk;
wire rst;
ebaz4205_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire ... | 8.112239 |
module corescore_emitter_uart #(
parameter clk_freq_hz = 0,
parameter baud_rate = 57600
) (
input wire i_clk,
input wire i_rst,
input wire [7:0] i_data,
input wire i_valid,
output reg o_ready,
output wire o_uart_tx
);
localparam START_VALUE = clk_f... | 6.975706 |
module corescore_ep2c5t144_devboard (
input wire clk50,
output wire led0,
output wire uart_txd
);
wire clk;
wire rst;
//Mirror UART output to LED
assign led0 = uart_txd;
ep2c5t144_clock_gen clock_gen (
.i_clk(clk50),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter ... | 7.930057 |
module corescore_fpc_iii (
input i_clk,
output o_uart_tx
);
wire clk;
wire rst;
corescore_fpc_iii_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire ... | 7.478384 |
module corescore_fpc_iii_clock_gen (
input i_clk,
output o_clk,
output o_rst
);
wire locked;
reg [1:0] rst_reg;
always @(posedge o_clk) rst_reg <= {!locked, rst_reg[1]};
assign o_rst = rst_reg[0];
pll pll (
.clki (i_clk),
.clko (o_clk),
.locked(locked)
);
endmodule
| 7.478384 |
module corescore_generic (
input wire i_clk,
input wire i_rst,
output wire o_uart_tx
);
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore (
.i_clk (i_clk),
.i_rst (i_rst),
.o... | 7.725582 |
module corescore_genesys2 (
input wire i_clk_p,
input wire i_clk_n,
output wire o_uart_tx
);
wire i_clk;
wire clk;
wire rst;
IBUFDS ibufds (
.I (i_clk_p),
.IB(i_clk_n),
.O (i_clk)
);
genesys2_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
... | 7.725582 |
module corescore_go_board (
input wire i_clk,
output wire o_uart_tx,
output wire o_led1,
output wire o_led2 = 0,
output wire o_led3 = 0,
output wire o_led4 = 0,
output wire o_pmod1
);
// Mirror UART output to LED1 and PMOD1
assign o_led1 = !o_uart_tx;
assign o_pmod1 = o_uart_tx;
... | 7.665494 |
module corescore_hpc_k7 (
input wire i_clk,
output wire o_uart_tx
);
wire clk;
wire rst;
hpc_k7_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire t... | 8.64465 |
module corescore_hpc_ku (
input wire i_clk,
output wire o_uart_tx
);
wire clk;
wire rst;
hpc_ku_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire t... | 8.64465 |
module corescore_hx8k (
input i_clk,
output wire o_uart_tx
);
wire clk;
wire locked;
//Create a 16MHz clock from 12MHz using PLL
pll pll12 (
.clock_in (i_clk),
.clock_out(clk),
.locked (locked)
);
reg rst = 1'b1;
always @(posedge clk) rst <= !locked;
parameter memfile_em... | 8.246714 |
module corescore_icebreaker (
input i_clk,
output wire o_uart_tx
);
wire clk;
wire locked;
//Create a 16MHz clock from 12MHz using PLL
SB_PLL40_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000),
.DIVF(7'b1010100),
.DIVQ(3'b110),
.FILTER_RANGE(3'b001)
) pll (
.LOCK(l... | 8.047261 |
module corescore_icestick (
input i_clk,
output wire o_uart_tx
);
wire clk;
wire locked;
//Create a 16MHz clock from 12MHz using PLL
pll pll12 (
.clock_in (i_clk),
.clock_out(clk),
.locked (locked)
);
reg rst = 1'b1;
always @(posedge clk) rst <= !locked;
parameter memfil... | 8.047261 |
module corescore_icesugar (
output wire g,
output wire b,
output wire r,
output wire o_uart_tx
);
wire clk48;
wire clk;
wire locked;
SB_HFOSC inthosc (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (clk48)
);
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b001... | 8.047261 |
module corescore_intel_a10gx_devkit (
input wire rstn,
input wire clk50
);
wire clk;
wire rst;
wire [7:0] tdata;
wire tlast;
wire tvalid;
reg tready;
reg [7:0] r_dat;
wire r_ena;
// ================================================================
// Ge... | 7.429578 |
module corescore_intel_agilex7 (
// input wire rstn,
input wire i_clk,
input wire i_rstn
);
wire clk;
wire rst;
wire [7:0] tdata;
wire tlast;
wire tvalid;
reg tready;
reg [7:0] r_dat;
wire r_ena;
wire ninit_done;
wire locked;
reg ... | 7.429578 |
module corescore_intel_cyc10lp_devkit (
input wire clk50,
output wire uart_txd
);
wire clk;
wire rst;
intel_cyc10lp_devkit_clock_gen clock_gen (
.i_clk(clk50),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire ... | 7.429578 |
module corescore_intel_max10_devkit (
input wire clk50,
output wire led0,
output wire uart_txd
);
wire clk;
wire rst;
//Mirror UART output to LED
assign led0 = uart_txd;
intel_max10_devkit_clock_gen clock_gen (
.i_clk(clk50),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile... | 7.429578 |
module corescore_intel_s10gx_devkit (
input wire rstn,
input wire clk50
);
wire clk;
wire rst;
wire [7:0] tdata;
wire tlast;
wire tvalid;
reg tready;
reg [7:0] r_dat;
wire r_ena;
wire locked;
// ===================================================... | 7.429578 |
module corescore_kc705 (
input wire i_clk_p,
input wire i_clk_n,
output wire q,
output wire o_uart_tx
);
wire i_clk;
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
IBUFDS ibufds (
.I (i_clk_p),
.IB(i_clk_n),
.O (i_clk)
);
corescore_kc705_clo... | 6.936083 |
module corescore_kc705_clock_gen (
input wire i_clk,
output wire o_clk,
output reg o_rst
);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(8),
.CLKIN1_PERIOD(5.0), //200MHz
.CLKOUT0_DIVIDE(100),
.DIVCLK_DIVIDE(1),
... | 6.936083 |
module corescore_marble (
input wire i_clk_p,
input wire i_clk_n,
output wire o_uart_tx,
output wire o_uart_tx2,
input wire i_uart_rx
);
assign o_uart_tx2 = o_uart_tx;
wire main_crg_clkin, main_crg_clkout0;
IBUFDS IBUFDS (
.I (i_clk_p),
.IB(i_clk_n),
.O (main_crg_clkin)
... | 6.703759 |
module corescore_max1000 (
input wire CLK12M,
output wire q,
output wire o_uart_tx
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
max1000_clock_gen clock_gen (
.i_clk(CLK12M),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex"... | 8.644317 |
module corescore_nexys_a7 (
input wire i_clk,
output wire o_uart_tx
);
wire clk;
wire rst;
nexys_a7_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire ... | 8.046299 |
module corescore_nexys_video (
input wire i_clk,
output wire o_uart_tx
);
wire clk;
wire rst;
nexys_video_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wi... | 8.046299 |
module corescore_polarfire (
input wire i_clk,
input wire resetbtn,
output wire q,
output reg h,
output wire o_uart_tx
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
assign rst = ~resetbtn;
PF_CCC_C0_PF_CCC_C0_0_PF_CCC clock_gen (
.REF_CLK_0(i_clk... | 7.618193 |
module corescore_sockit (
input wire i_clk,
input wire i_rst_n,
output wire q,
output wire uart_txd
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = uart_txd;
de0_nano_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(!i_rst_n),
.o_clk(clk),
.o_rst(rst)
);... | 8.370868 |
module corescore_storeypeak (
input wire i_clk,
output wire q,
output wire o_uart_tx
);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = ~o_uart_tx;
storeypeak_clock_gen clock_gen (
.i_clk(i_clk),
.o_clk(clk),
.o_rst(rst)
);
parameter memfile_emitter = "emitter... | 8.437982 |
module corescore_tinyfpga_bx (
input wire i_clk,
inout wire pin_usb_p,
inout wire pin_usb_n,
output wire pin_pu
);
wire clk;
wire clk_locked;
// USB Host Detect Pull Up
assign pin_pu = 1'b1;
pll pll48 (
.clock_in (i_clk),
.clock_out(clk),
.locked (clk_locked)
);
... | 7.046622 |
module corescore_ulx3s (
input wire i_clk,
input wire btn0,
output wire wifi_gpio0,
output wire o_uart_tx,
output wire q
);
wire clk;
wire rst;
assign q = o_uart_tx;
assign wifi_gpio0 = btn0;
corescore_ulx3s_clock_gen clock_gen (
.i_clk(i_clk),
.i_rst(!btn0),
.o_clk(... | 7.091456 |
module corescore_ulx3s_clock_gen (
input i_clk,
input i_rst,
output o_clk,
output o_rst
);
wire locked;
reg [1:0] rst_reg;
always @(posedge o_clk)
if (i_rst) rst_reg <= 2'b11;
else rst_reg <= {!locked, rst_reg[1]};
assign o_rst = rst_reg[0];
pll pll (
.clki (i_clk),
... | 7.091456 |
module corescore_upduino2 (
output wire g,
output wire b,
output wire r,
output wire o_uart_tx
);
wire clk48;
wire clk;
wire locked;
SB_HFOSC inthosc (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (clk48)
);
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b001... | 7.677494 |
module CoreState (
input wire clk,
input wire rst_n,
input wire slake,
start,
flag,
clear,
zero_n,
ensure,
output reg [1:0] state
);
// Declare state register
// Declare states
parameter INITIAL = 0, ZERO = 1, COIN = 2, COUNTDOWN = 3;
// Determine th... | 6.773491 |
module ImmGenWire (
input [31:0] io_inst,
input [ 2:0] io_sel,
output [31:0] io_out
);
wire [11:0] Iimm = io_inst[31:20]; // @[ImmGen.scala 21:30]
wire [11:0] Simm = {io_inst[31:25], io_inst[11:7]}; // @[ImmGen.scala 22:50]
wire [12:0] Bimm = {
io_inst[31], io_inst[7], io_inst[30:25], io_inst[... | 6.876503 |
module BrCondArea (
input [31:0] io_rs1,
input [31:0] io_rs2,
input [ 2:0] io_br_type,
output io_taken
);
wire [31:0] diff = io_rs1 - io_rs2; // @[BrCond.scala 37:21]
wire neq = diff != 32'h0; // @[BrCond.scala 38:19]
wire eq = ~neq; // @[BrCond.scala 39:14]
wire isSameSign = io_rs1... | 8.510131 |
module decoder2to4 (
a,
b
);
parameter n = 2;
parameter m = 4;
input [n-1:0] a;
output [m-1:0] b;
wire [m-1:0] b = 1 << a;
endmodule
| 7.120389 |
modules for a single RANC core.
//////////////////////////////////////////////////////////////////////////////////
module Core_3x2 #(
parameter CORE_NUMBER = 0
)(
input clk,
input tick,
input reset_n,
input ren_in_west,
input ren_in_east,
input ren_in_north,
input ren_in_south,
... | 6.884169 |
module core_alu (
/* operand_port */
input [`OPERAND_WIDTH-1:0] oprd1,
input [`OPERAND_WIDTH-1:0] oprd2,
/* control_signals */
input [`ALU_CTRL_WIDTH-1:0] alu_ctrl_i,
/* alu_output */
output [`OPERAND_WIDTH-1:0] alu_o
);
parameter ADD = `ALU_CTRL_WIDTH'b00000;
parameter SUB = `ALU_CTR... | 8.131689 |
module core_alu_ctrl (
/* imput_signals */
input [1:0] alu_op, // 00 / 01(R-type) / 10(I-type)
input [6:0] funct7,
input [2:0] funct3,
/* output_control_signals */
output [`ALU_CTRL_WIDTH-1:0] alu_ctrl
);
parameter ADD = `ALU_CTRL_WIDTH'b00000;
parameter SUB = `ALU_CTRL_WIDTH'b00001;
pa... | 7.709223 |
module Stub File
// -------------------------------------------------------------------
module core_alu (
alu_en_i,
alu_operand1_i,
alu_operand2_i,
alu_opcode_i,
alu_cy_i,
alu_ac_i,
alu_ov_i,
... | 7.539286 |
module pc_reg_test ();
reg eval_en;
reg [`MemByteBus] opnum1;
reg [`MemByteBus] opnum2;
reg [`ALUFuncBus] alufunc;
wire [`MemByteBus] aluout;
core_alu core_alu_inst (
.eval_en (eval_en),
.opnum1_in(opnum1),
.opnum2_in(opnum2),
.func_in (alufunc),
.res_out (aluout)
);
a... | 6.757819 |
module name:BTB module used to cache recent target of jumps and branches
module core_btb(//input
clk,
rst,
pc,
update_btb_tag,
update_btb_target,
btb_target_in,
btb_type_in,
P... | 6.891497 |
module core_c1_clic (
input interrupt_plic_in,
input interrupt_soft_in,
input interrupt_time_in,
//input [1:0] interrupt_mode,
//input exception_addr_misaligned,
//input exception_addr_access_fault,
input exception_illegal_instruction,
input exception_breakpoint,
//input exception_l... | 7.658542 |
module core_c1_exu_alu (
//四个源操作数输入
input [31:0] exu_pc_addr,
input [31:0] exu_rs1_data,
input [31:0] exu_rs2_data,
input [31:0] exu_imm32,
input [ 7:0] cmd_type_bus, //指令类型
input [11:0] cmd_op_alu, //指令操作
output [31:0] alu_rd_data,
output alu_rd_valid //写寄存器请求
);
w... | 7.669845 |
module core_c1_exu_bjp (
//四个源操作数输入
input [31:0] exu_pc_addr,
input [31:0] exu_rs1_data,
input [31:0] exu_rs2_data,
input [31:0] exu_imm32,
input [7:0] cmd_type_bus, //指令类型
input [7:0] cmd_op_bjp, //指令操作
output bjp_rd_valid,
output [31:0] bjp_rd_data,
output ... | 9.318278 |
module core_c1_exu_lsu (
input [7:0] cmd_type_bus, //指令类型
input [7:0] cmd_op_memory, //指令操作
input exu_pause,
input [31:0] exu_rs1_data,
input [31:0] exu_rs2_data,
input [31:0] exu_imm32,
input [31:0] lsu_load_data,
output [31:0] lsu_store_addr,
output lsu_store_e... | 7.920521 |
module core_c1_ifu_to_exu_reg (
input exu_pause,
input ifu_inst_valid,
output exu_inst_valid,
input [31:0] ifu_inst,
output [31:0] exu_inst,
input [31:0] ifu_pc_addr,
output [31:0] exu_pc_addr,
input [31:0] regs_rs1_data,
output [31:0] exu_rs1_data,
input [31:0] regs_r... | 7.08087 |
module core_clk #(
parameter PRESCALER = 16
) (
input clk,
input rst,
output reg [PRESCALER-1:0] core_clk
);
initial begin
core_clk = 0;
end
always @(posedge clk or posedge rst) begin
if (rst) core_clk <= 0;
else core_clk <= core_clk + 1;
end
endmodule
| 7.159786 |
modules
////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps
module core_control(
ctrl_clk,
ctrl_reset,
ctrl_instruction,
ctrl_valid_inst,
ctrl_valid_data,
ctrl_data_in_size,
ctrl_data_contition,
mc_done,
mc_data_done,
mc_data_length,
procc_instruction,
pr... | 6.874849 |
module: Core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module core_cpu_test;
// Inputs
reg clk;
reg rst;
wire [15:0] mem_to_core_data;
reg i2c_wr_en;
reg [1:0] i2c_sts;
reg [7... | 7.003797 |
module core_ctrl (
/* instruction_input */
input [`CPU_INSTR_SIZE-1:0] instr_i,
input [2:0] branch_judgment,
/* output control signals */
// use in IFU
output pc_src,
// use in IDU
output idx_src,
// use in EXU
output [1:0] alu_op,
output alu_src,
output alu_w_sext,
... | 8.09979 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.