code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module core_ep2c5_picorv32_wb_soc (
input CLK50MHZ,
input RST_KEY,
output [3:0] LED,
input H_LEFT_3,
output H_LEFT_4
);
wire wb_clk;
wire wb_rst;
altpll_wb_clkgen #(
.DEVICE_FAMILY ("Cyclone II"),
.INPUT_FREQUENCY(50),
/* wb_clk: 24 MHz */
.WB_DIVIDE_BY (25),
... | 7.581154 |
module core_ep4ce6_picorv32_wb_soc (
input CLK50MHZ,
input RST_KEY,
output [3:0] LED,
input H_LEFT_3,
output H_LEFT_4
);
wire wb_clk;
wire wb_rst;
altpll_wb_clkgen #(
.DEVICE_FAMILY ("Cyclone IV E"),
.INPUT_FREQUENCY(50),
/* wb_clk: 24 MHz */
.WB_DIVIDE_BY (25),... | 7.735955 |
module alu
`ifdef CUSTOM_DEFINE
#(parameter ALU_OPWIDTH = `ALU_OP_WIDTH,
parameter DATA_WIDTH = `REG_DATA_WIDTH,
parameter ALU_OP_ADD = `ALU_OP_ADD,
parameter ALU_OP_SUB = `ALU_OP_SUB,
parameter ALU_OP_SLL = `ALU_OP_SLL,
parameter ALU_OP_SLT = `ALU_OP_SLT,
parameter ALU_OP_SLTU = `ALU_OP_SLTU,
parame... | 7.667879 |
module br
`ifdef CUSTOM_DEFINE
#(parameter BR_OP_WIDTH = `BR_OP_WIDTH,
parameter DATA_WIDTH = `REG_DATA_WIDTH,
parameter BR_EQ = `ALU_OP_ADD,
parameter BR_NE = `ALU_OP_SUB,
parameter BR_LT = `ALU_OP_SLL,
parameter BR_GE = `ALU_OP_SLT)
`else
#(parameter BR_OP_WIDTH = 2,
parameter DATA_WIDTH = ... | 7.682453 |
module lis `ifdef CUSTOM_DEFINE
#(parameter LIS_OP_WIDTH = `LIS_OP_WIDTH,
parameter DATA_WIDTH = `REG_DATA_WIDTH,
parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH,
parameter LIS_LB = `LIS_LB,
parameter LIS_LH = `LIS_LH,
parameter LIS_LW = `LIS_LW,
parameter LIS_LBU = `LIS_LBU,
p... | 9.468923 |
module to implement entire Excution Stage
//
// ====================================================================
`include "defines.v"
module core_exu (
/* reg_signals */
// input
// from ID/EX_Register
input [`CPU_PC_SIZE-1:0] pc_i,
input [`CPU_INSTR_SIZE-1:0] instr_i,
input [`OPERAND_WI... | 8.470867 |
module core_ex_mem (
/* input_port */
// main signals
input [ `CPU_PC_SIZE-1:0] pc_i,
input [`CPU_INSTR_SIZE-1:0] instr_i,
input [ `OPERAND_WIDTH-1:0] imm_i,
input [`CPU_RFIDX_WIDTH-1:0] rsd_idx_i,
input [`OPERAND_WIDTH-1:0] rs2_data_i,
input [`OPERAND_WIDTH-1:0] alu_i,
// cont... | 7.823275 |
module core_flattened #(
parameter imem_addr_width_p = 10
, net_ID_p = 10'b0000000001
) (
input clk
, input reset
, input [$bits(net_packet_s)-1:0] net_packet_flat_i
, output [$bits(net_packet_s)-1:0] net_packet_flat_o
, input [$bits(mem_out_s)-1:0] from_mem_flat_i
, output [ $bits... | 6.687467 |
module Stub File
// -------------------------------------------------------------------
module core_fsm (
fsm_clock_i,
fsm_reset_i_b,
fsm_reset_core_o_b,
fsm_alu_result_i,
fsm_sfr_addr_o,
fsm_bit_byte_flag_o,
... | 7.539286 |
module core_hazard_ctrl (
input rst_n,
// register controll
output [3:0] haz_enb_bus_out,
output [1:0] haz_kill_bus_out,
//
output haz_mux_trn_out,
// forwarding
output [3:0] haz_bp_mux_exe_out,
output haz_bp_mux_mem_out,
// sourses and destinations
input... | 8.549981 |
module to implement entire Decode Stage
//
// ====================================================================
`include "defines.v"
module core_idu (
/* reg_signals */
// input
// from IF/ID_Register
input [`CPU_PC_SIZE-1:0] pc_i,
input [`CPU_INSTR_SIZE-1:0] instr_i,
// from Register... | 8.470867 |
module core_if (
input rst,
input wire [`InstAddressBus] pc_addr_in, // 程序计数器地址
input wire [ `SelectModeBus] select_as_in,
output wire [`InstAddressBus] rom_addr_out, // ROM地址
input wire [ `InstByteBus] rom_data_in, // ROM数据
output reg pc_rw_out,
// 从core_ctrl输入... | 8.114834 |
module to implement entire Instruction_fetch Stage
//
// ====================================================================
`include "defines.v"
module core_ifu (
/* instruction_fetch_signals */
output [`CPU_PC_SIZE-1:0] pc_idx,
input [`CPU_INSTR_SIZE-1:0] instr_fetched,
/* reg_signals */
// ou... | 8.470867 |
module core_if_id (
/* input_port */
// main signals
input [`CPU_PC_SIZE-1:0] pc_i,
input [`CPU_INSTR_SIZE-1:0] instr_i,
/* output_port */
// main signals
output [`CPU_PC_SIZE-1:0] pc_o,
output [`CPU_INSTR_SIZE-1:0] instr_o,
/* control_signals */
/* basic_signals */
input ... | 7.813265 |
module core_if_s (
input clk,
input rst_n,
//register control
input if_kill,
input if_enb,
//from hazard control
input if_mux_trn_s_in,
// for transfer of address
input [31:0] if_addr_mux_trn_in,
//for l1i $
out... | 6.621513 |
module pc_reg_test ();
reg [`InstAddressBus] pc_addr;
wire [`InstAddressBus] rom_addr;
wire [`InstAddressBus] rom_index;
reg [`InstByteBus] rom_data;
reg [`InstAddressBus] rom[0:15];
wire [`InstAddressBus] pc;
wire [`InstByteBus] inst;
core_if core_if_inst (
.pc_addr_in (pc_addr),
.rom_ad... | 6.757819 |
module core_imm (
/* input_instruction */
input [`CPU_INSTR_SIZE-1:0] instr_i,
/* output_immediate_operand */
output [ `OPERAND_WIDTH-1:0] imm_o
);
// Nodes between AND-gate and OR-gate
wire n1;
wire n2;
wire n3;
wire n4;
wire n5;
wire n6;
wire n7;
// Immediate Operand
wire [`OPERA... | 8.170491 |
module core_input #(
parameter N_CORES = 3,
parameter N_CORES_MSB = `MSB(N_CORES - 1),
parameter N_THREADS = 2 * N_CORES,
parameter N_THREADS_MSB = `MSB(N_THREADS - 1)
) (
input CLK,
// from realign
input realign_wr_en_r,
realign_valid_eqn,
realign_valid,
input [N_THREADS_MSB :... | 7.525217 |
module core_input_buf (
input CLK,
input [31:0] din,
input [3:0] wr_addr,
input wr_en,
output reg [31:0] dout = 0,
input rd_en,
input [3:0] rd_addr
);
// Data block 512-bit (2x)
(* RAM_STYLE="DISTRIBUTED" *)
reg [31:0] input_buf[0:15];
always @(posedge CLK) begin
if (rd_en) d... | 7.506433 |
module to implement entire Decode Stage
//
// ====================================================================
`include "defines.v"
module core_mem (
/* reg_signals */
// input
// from EX/MEM_Register
input [`CPU_PC_SIZE-1:0] pc_i,
input [`CPU_INSTR_SIZE-1:0] instr_i,
input [`OPERAND_WID... | 8.470867 |
module responsible for access internal and external memories
// --------------------------------------------------------------------
module core_mem_ctrl(
mem_ctrl_clk_i,
mem_ctrl_rom_rd_b_i,
mem_ctrl_ram_rd_b_i,
mem_ctrl_ram_wr_b_i,
... | 7.696918 |
module responsible for access internal and external memories
// --------------------------------------------------------------------
`timescale 1ns/10ps
module core_mem_ctrl_tb();
reg clk_i;
reg rom_rd_i;
reg ram_rd_i;
reg ram_wr_i;
reg bit_byte_flag_i;
reg ext_r... | 7.696918 |
module core_mem_s (
input mem_val_inst_in,
input clk,
input rst_n,
input mem_enb,
//control pins
input [ 2:0] mem_wb_sx_op_in,
input mem_l1d_req_val_in,
input mem_l1d_req_cop_in,
input [ 2:0] mem_l1d_req_size_in,
input mem_we_reg_f... | 7.079086 |
module core_mem_wb (
/* input_port */
// main signals
input [ `CPU_PC_SIZE-1:0] pc_i,
input [`CPU_INSTR_SIZE-1:0] instr_i,
input [ `OPERAND_WIDTH-1:0] imm_i,
input [`CPU_RFIDX_WIDTH-1:0] rsd_idx_i,
input [`OPERAND_WIDTH-1:0] alu_i,
input [`OPERAND_WIDTH-1:0] mem_data_i,
// cont... | 7.441294 |
module core_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "core_onchip_memory2_0.hex";
output [31:0] readdata;
input [11:0] address;
inpu... | 6.662655 |
module core_output_buf_bram (
input CLK,
input [31:0] din,
input wr_en,
input [3:0] wr_addr,
input wr_seq,
// ==============================================================
//
// OUTPUT OPERATION
//
// 1. At some stage, 'core_out_ready' asserts.
// core_out_ctx_num, co... | 8.137565 |
module name program counter module
module core_pc(//input
clk,
rst,
btb_target,
ras_target,
pc_go,
stall,
// from id module
good_target, // target from decode stage, correct target
id_p... | 6.716993 |
module
// and its decisions.
// -----------------------------------------------------------------------------
`include "/home/student/EMC08/digital_A/core/design/rtl_v/time_scale.v"
module core_pcau (
pcau_clock_mem_i,
pcau_reset_i_b,
pcau_offset_i,
... | 7.682132 |
module Stub File
// -------------------------------------------------------------------
module core_pcau (
pcau_clock_mem_i,
pcau_clock_i,
pcau_reset_i_b,
pcau_offset_i,
pcau_en_i,
pcau_pc_o,
pcau_pc_... | 7.539286 |
module core_pc_reg (
/* read _port */
output [63:0] pc_o,
/* write_port */
input [63:0] pc_i,
/* control_signals */
input wen,
/* basic_signals */
input clk,
input rst_n
);
Reg #(`CPU_PC_SIZE, `CPU_PC_RST_IDX) pc (
.clk (clk),
.rst (~rst_n),
.din (pc_i),
... | 7.882585 |
module core_peripheric (
clk,
addr,
d_in,
d_out,
wr,
rd
);
input clk;
input [15:0] d_in;
output reg [15:0] d_out;
output reg [7:0] addr; // 8 LSB from j1_io_addr
output reg rd;
output reg wr;
reg [15:0]
F_1, F_2, F_3, F_4, F_5, F_6; // aqui se almacenan los terminos d... | 7.257666 |
module name: PHT :Pattern History Table
module core_pht(//input
clk,
rst,
if_pc, // pc[10:5]
id_pc, // pc[10:5]
update_BP,
pred_right,
taken,
BHR_in,
... | 6.943556 |
module core_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [9:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] wr... | 6.659513 |
module Core_pipIF (
// System
input wire i_Clk,
input wire i_Rstn,
// Branch & Jump
input wire i_EX_Branch_En, // Branch enabler
input wire [`MemAddr ] i_EX_Branch_Addr, // Branch address
// Istruction Memory
input wire [`BusWidth] i_IMEM_Data, // Instruction fetched
out... | 7.217135 |
module core_pixel (
output [7:0] O_PIXEL_IN_ADDR0,
output [7:0] O_PIXEL_IN_ADDR1,
output [7:0] O_PIXEL_IN_ADDR2,
output [7:0] O_PIXEL_IN_ADDR3,
output [7:0] O_PIXEL_OUT_ADDRB,
output [7:0] O_PIXEL_OUT_ADDRG,
output [7:0] O_PIXEL_OUT_ADDRR,
output [7:0] O_PIXEL_OUT_ADDR0,
output [7:0... | 6.769608 |
module core_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked, ... | 7.511666 |
module programCounter
`ifdef CUSTOM_DEFINE
#(parameter REG_DATA_WIDTH = `REG_DATA_WIDTH)
`else
#(parameter REG_DATA_WIDTH = 32)
`endif
(
rst_n,
clk,
new_pc_i, // New PC
pc // PC
//reg_pc_o
);
input rst_n, clk;
input [REG_DATA_WIDTH-1:0] new_pc_i;
output [REG_DATA_W... | 6.882022 |
module.
//
// ====================================================================
`include "defines.v"
module core_regfile (
/* read_port */
// read_port_1
input [`CPU_RFIDX_WIDTH-1:0] r1_idx,
output [`CPU_RFDATA_WIDTH-1:0] r1_data,
// read_port_2
input [`CPU_RFIDX_WIDTH-1:0] r2_idx,
o... | 7.850245 |
module core_reg_file (
input clk,
input rst_n,
input [ 4:0] rs1_in,
input [ 4:0] rs2_in,
input [ 4:0] rd_in,
input [31:0] data_in,
input we_in,
input order_in,
output [31:0] src1_out,
output [31:0] src2_out
);
integer i;
reg [31:0] reg_fil... | 7.728141 |
module core_sobel (
p0,
p1,
p2,
p3,
p5,
p6,
p7,
p8,
out
);
input [7:0] p0, p1, p2, p3, p5, p6, p7, p8; // 8 bit pixels inputs
output [7:0] out; // 8 bit output pixel
wire signed [10:0] gx, gy; //11 bits because max value of gx and gy is
//255*4 and last bit for sign ... | 7.431967 |
module uart_tramsmiter_sim (
input wire rstn,
input wire uart_clk,
input wire request,
input wire [7:0] data,
output wire ack,
output reg tx_out
);
wire wreq;
wire tx_req;
reg del_request;
reg [7:0] tx_reg;
reg tx_empty;... | 7.475341 |
module uart_veri_transmitter_sim (
input wire clk,
input wire request,
input wire [7:0] data,
output reg ack,
output reg debug_busy,
output reg [7:0] debug_data
);
reg [1:0] ack_reg;
initial begin
ack_reg = 2'd0;
debug_busy = 1'b1;
end
always @(po... | 6.532657 |
module uart_veri_receiver_sim (
input wire tx_empty,
input wire [7:0] tx_reg
);
wire rx_ready /*verilator public*/;
wire [7:0] rx_data /*verilator public*/;
assign rx_ready = ~tx_empty;
assign rx_data = tx_reg;
endmodule
| 8.209491 |
module core_timer (
//global signals
output wire core_timer_int, //interrupt notification to core
//AHB INTERFACE
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [`AHB_ADDR_WIDTH - 1 : 0] HADDR,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire [2:0] HBUR... | 6.579988 |
module core_timer_regs (
//global signals
input wire HCLK, //AHB clock
input wire HRESETn, //AHB reset, active low
//interface with AHB2regbus
input wire valid_reg_access, //valid reg access
input wire [ 15:0] addr, //reg access add... | 6.932737 |
module to implement entire Write_back Stage
//
// ====================================================================
`include "defines.v"
module core_wb (
/* reg_signals */
// input from MEM/WB_Register
input [`CPU_PC_SIZE-1:0] pc_i,
input [`CPU_INSTR_SIZE-1:0] instr_i,
input [`OPERAND_WIDTH-1... | 8.470867 |
module core_wb_s (
input clk,
// input rst_n,
//control
input wb_mux_alu_mem_in,
input wb_ack_from_lid_in,
input wb_we_reg_file_in,
input [ 2:0] wb_sx_op_in,
input [ 4:0] wb_rd_in,
//data terminals
input [31:0] wb_alu_result_in,
input ... | 7.96617 |
module pcie_core_wrap (
// IO pins
output [ `NLANES-1:0] pci_exp_txp,
output [ `NLANES-1:0] pci_exp_txn,
input [ `NLANES-1:0] pci_exp_rxp,
input [ `NLANES-1:0] pci_exp_rxn,
input sys_clk_p,
input sys_clk_n,
input ... | 7.002048 |
module xrv32i_soc_test ();
reg clk;
reg rst;
wire led;
xrv32i_soc xrv32i_soc_inst (
.clk(clk),
.rst(rst),
.led_out(led)
);
wire [`RegistersByteBus] r27, r28, r29;
wire [1023:0] addr_in;
wire [4:0] master_id;
wire [31:0] addr_in_out;
assign r27 = xrv32i_soc_inst.xrv32i_core.r... | 7.615139 |
module xrv32i_test ();
reg clk;
reg rst;
wire [ `InstByteBus] inst;
wire [`MemAddressBus] inst_addr;
reg [ `InstByteBus] insts [0:29];
assign inst = insts[inst_addr>>2];
xrv32i xrv32i_inst (
.clk(clk),
.rst(rst),
.inst_in (inst), ... | 8.48926 |
module Coridc_pre(
rst, clk,
in_valid,
in_x, in_y,
out_x, out_y,
inf,
out_valid
);
parameter DW = 16;
input rst, clk;
input in_valid;
input signed [DW-1:0] in_x, in_y;
output signed [DW-1:0] out_x, out_y;
output [2:0] inf;
output reg out_valid;
reg signed [DW-... | 6.749139 |
module correcao0(a, b, c, d, out1, out2, out3);
output out1, out2, out3;
input a,b,c,d;
wire(resp,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,not1,not2,not3,not4);
not n1(not1,c);
not n2(not2,d);
//---s2-----
and a1(q1,not1,not2,b);
and a2(q2,not1,a);
and a3(q3,not2,a,b);
or o1(out1,q1,q2,q3);
//Fim s2
//---s1... | 6.611555 |
module ui_START(
// input [3:0]KEY,
// input CLOCK_50,
// input [9:0]SW,
// output VGA_CLK, // VGA Clock
// output VGA_HS, // VGA H_SYNC
// output VGA_VS, // VGA V_SYNC
// output VGA_BLANK_N, // VGA BLANK
// output VGA_SYNC_N, // VGA SYNC
// output [9:0] VGA_R, // VGA Red[9:0]
// o... | 6.996592 |
module ui_correct (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
input clear,
output [7:0] x,
output [6:0] y,
output [2:0] color,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI_correct c0 (
clear,
... | 6.794153 |
module control_UI_correct (
input clear,
input clk,
input reset_n,
input enable_unit,
output reg enable,
output reg writeEn,
output reg reset_datapath,
output [2:0] color
);
localparam ENABLE_STATE = 4'b0000, ENABLE_WAIT = 4'b0001, DRAW = 4'b0010, DISABLE = 4'b0011;
reg [1:0] curren... | 6.990792 |
module datapath_correct (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1, increment2, increment3, increment4, increment5, increment6, increment7, incr... | 6.603628 |
module not1 (
input i1,
output o1
);
assign o1 = !i1;
endmodule
| 7.35925 |
module not1 (
input i1,
output reg o1
);
always @(i1) begin
o1 = !i1;
end
endmodule
| 7.35925 |
module not1 (
input i1,
output o1
);
reg o1;
always @(i1) begin
o1 = !i1;
end
endmodule
| 7.35925 |
module not1 (
input i1,
output o1
);
reg r;
always @(i1) begin
r = !i1;
end
assign o1 = r;
endmodule
| 7.35925 |
module NED (
input signal,
input clk,
output detect
);
reg signalafterdelay;
always @(posedge clk) begin
signalafterdelay <= signal;
end
assign detect = signalafterdelay & ~signal;
endmodule
| 6.606488 |
module correction #(
parameter TIMESTAMP_WIDTH = 64,
parameter DDS_WIDTH = 32
) (
// input
input [TIMESTAMP_WIDTH-1:0] time_pps,
input pps_valid,
input correction_mode,
// output
output reg [DDS_WIDTH-1:0] dds,
// misc
input reset,
... | 9.169821 |
module correlate_cos_sin #(
parameter ACCUM = 24,
parameter MSB = ACCUM - 1,
parameter SUMHI = 0, // is "ones-counting" needed?
parameter DELAY = 3
) (
input clk,
input en,
input hi,
input ar,
input br,
input bi,
input [MSB:0] dcos,
input [MSB:0] dsin,
o... | 6.989922 |
module correlate_cos_sin_DSP #(
parameter ACCUM = 24, // 24-bit is the maximum for this module
parameter MSB = ACCUM - 1,
parameter XSB = ACCUM + MSB,
parameter SUMHI = 0, // is "ones-counting" needed?
parameter DELAY = 3
) (
input clk,
input clr,
input en,
i... | 6.989922 |
module correlator_is (
clk_6M,
rstz,
p_1us,
correWindow,
sync_in,
ref_sync,
regi_correthreshold,
ps_corre_threshold,
corre_tslotdly_endp,
corre_halftslotdly_endp,
corr_2tslotdly_endp,
corr_3tslotdly_endp,
corr_4tslotdly_endp,
pscorr_trgp
);
input clk_6M, rstz,... | 6.770033 |
module: correlator_xor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module correlator_tb;
// Inputs
reg clk;
reg resetn;
reg go;
wire [127:0] bram_data;
reg [5:0] x_offset;
reg [... | 7.266258 |
module corrimiento (
input [23:0] in,
output wire [25:0] out
);
assign out = in << 2;
endmodule
| 7.589581 |
module CORR_ACC(rx_clk,rx_rst,rx_data_real,rx_data_imag,rx_loc_boc,rx_prn_sop,rx_prn_eop,
tx_corr_acc);
parameter CORR_WIDTH = 33;
parameter CORR_ACC_WIDTH = 34;
parameter DAT_WIDTH = 16;
input rx_clk,rx_rst;
input[DAT_WIDTH-1:0] rx_data_real,rx_data_imag;
input rx_loc_boc;
input rx_prn_sop,rx_prn_eop;
<<<<<<< H... | 6.759688 |
module CortexM0 (
input wire CLK,
input wire RESET_N, // reset when negative
// For instruction memory
output wire IREQ,
output wire [31:0] IADDR,
input wire [31:0] INSTR,
// For data memory
output wire DREQ,
output wire [31:0] DADDR,
output wire DRW,
output wire [ 1:0] DS... | 7.015155 |
module
module fetch(
input wire CLK,
input wire branch,
input [31:0] wire PC,
input [31:0] wire ALU_PC,
output [31:0] wire PC_OUT
);
reg [31:0] PC, EXE_PC, PC_temp; // Program Counter
assign PC_OUT = PC_temp;
always @ (negedge CLK) begin
// Update PC
if (branch == 1'b0) begin
EXE_PC <= PC - 2;
PC_temp <=... | 7.103141 |
module
module Shift_C (
output wire [31:0] result,
output wire [31:0] carry_out,
input wire [31:0] value,
input wire [31:0] SRType,
input wire [31:0] amount,
input wire carry_in
);
endmodule
| 6.772707 |
module ADDwithCarry (
output wire [31:0] result,
output wire [31:0] carry,
output wire [31:0] overflow,
input wire [31:0] x,
input wire [31:0] y,
input wire carry_in
);
endmodule
| 7.387828 |
module InitBlock (
input wire [31:0] cond,
input wire [31:0] APSR_N,
input wire [31:0] APSR_Z,
input wire [31:0] APSR_C,
input wire [31:0] APSR_V,
output wire pass
);
always @(cond) begin
case (cond)
0: begin
assign pass = (APSR_Z == 1);
end
1: begin
assi... | 8.402621 |
module CORTEXM0DS_wrap (
// CLOCK AND RESETS ------------------
input wire HCLK, // Clock
input wire HRESETn, // Asynchronous reset
// AHB-LITE MASTER PORT --------------
output wire [31:0] HADDR, // AHB transaction address
output wire [ 2:0] HBURST, // AHB burst: tied to single
... | 7.348382 |
module is designed as an example reset controller for the Cortex-M0
// // processor It takes a global reset that can be asynchronously asserted
// and generates from it synchronously asserted and deasserted resets based
// on synchronous reset requests
// This module is intended to interface to the example PMU provi... | 7.113164 |
module cortexm0_wic (
input FCLK,
input nRESET,
input WICLOAD, // WIC mask load from core
input WICCLEAR, // WIC mask clear from core
input [33:0] WICINT, // Interrupt request from system
input [33:0] WICMASK, // Mask from core
input WICE... | 7.367945 |
module CM1_JTAG (
input HCLK, // AHBʱ
input rst_x, // 弶ȫ첽λź
// JTAG inputs
input nTRST, // JTAG reset
input TCK, // JTAG clock
input TDI, // JTAG data in
inout TMS, // JTAG mode select
// JTAG outputs
... | 7.0911 |
module Cortina (
clk,
accion,
direccion,
pwm
);
input clk;
input [1:0] accion;
output reg [1:0] direccion;
output reg pwm;
reg pwm1;
reg pwm2;
reg [25:0] counter1;
parameter SUBIR = 2'b10, BAJAR = 2'b01;
always @(posedge clk) begin
counter1 = counter1 + 1;
if (counter1 < 50... | 6.819963 |
module CORTOCIRCUITO #( //PARAMETERS
parameter DATA_WIDTH = 32
) ( //INPUTS
input [4:0] i_rd_rt_mem,
input [4:0] i_rd_rt_wb,
input [4:0] i_rs,
input [4:0] i_rt,
input [1:0] i_wb_mem,
input [1:0] i_wb_wb,
//OUTPUTS
output [1:0] o_cortocircuitoA,
output [1:0] o_cortocircuit... | 6.503106 |
module coscnt (
input clk,
rst,
TLTY,
repcnt0,
start,
output reg done,
ldx,
rsel,
xsel,
ldt,
ld1,
ldr,
en,
addsub,
inccnt,
ld0cnt
);
reg [2:0] ps, ns;
always @(TLTY, repcnt0, start, ps) begin
done = 0;
ldx = 0;
rsel = 0;
xsel = 0;
l... | 6.580773 |
module coscnt (
input clk,
rst,
TLTY,
repcnt0,
start,
output reg done,
ldx,
rsel,
xsel,
ldt,
ld1,
ldr,
en,
addsub,
inccnt,
ld0cnt
);
reg [2:0] ps, ns;
always @(TLTY, repcnt0, start, ps) begin
done = 0;
ldx = 0;
rsel = 0;
xsel = 0;
l... | 6.580773 |
module cosDP (
input [15:0] xin,
input [8:0] y,
input clk,
rst,
input ld0cnt,
inccnt,
rsel,
xsel,
ldx,
ldt,
ld1,
ldr,
en,
addsub,
output [15:0] z,
output reg TLTY,
repcnt0
);
reg [2:0] repcnt;
reg [15:0] repbus, subbus;
reg [15:0] xreg, treg, rre... | 7.238226 |
module cosDP (
input [15:0] xin,
input [8:0] y,
input clk,
rst,
input ld0cnt,
inccnt,
rsel,
xsel,
ldx,
ldt,
ld1,
ldr,
en,
addsub,
output [15:0] z,
output reg TLTY,
repcnt0
);
reg [2:0] repcnt;
reg [15:0] repbus, subbus;
reg [15:0] xreg, treg, rre... | 7.238226 |
module cosimSPWM (
output Sau,
output Sal,
output Sbu,
output Sbl,
output Scu,
output Scl,
output signed [31:0] out,
input signed [31:0] x,
input signed [31:0] y,
input signed [31:0] z,
input clk,
res
);
spwm #(32, 28) uut (
.x (x),
.y (y),
.z (z)... | 6.899393 |
module CosLookUp (
clk,
reset,
aci,
cos_out
);
input reset;
input [2:0] aci; //
output reg signed [16:0] cos_out;
input clk;
always @(posedge clk) begin
if (reset) cos_out <= 17'd0;
else begin
case (aci)
3'b000: cos_out <= 17'b0000001_0000000000; //0 *
//3'... | 7.096054 |
module cosModule (
phase,
cosOut
);
input [`phaseRes-1:0] phase;
output reg [`SinSize-1:0] cosOut;
always @(phase) begin
if (phase == `phaseRes'd0) cosOut = `SinSize'd4095;
else if (phase == `phaseRes'd1) cosOut = `SinSize'd2896;
else if (phase == `phaseRes'd2) cosOut = `SinSize'd0;
else... | 6.660539 |
module CostasLoop (
rst,
clk,
din,
di,
dq,
df
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟：8MHz
input signed [7:0] din; //输入数据：8MHz
output signed [25:0] di; //同步后的输出信号(同相支路)
output signed [25:0] dq; //同步后的输出信号(正交支路)
output signed [25:0] df; //环路滤波器输出数据
//实例化NCO核所需的接口信号
... | 8.734152 |
module cost_acc (
clk,
rst,
en,
i_d,
o
);
// parameters
parameter WIDTH = 32;
parameter FRAC = 24;
parameter N_OUT = 2;
// common ports
input clk;
input rst;
// control ports
input en;
// input ports
input signed [N_OUT*WIDTH-1:0] i_d;
// output ports
output signed [WI... | 7.206386 |
module cost_acc_tb ();
// parameters
parameter WIDTH = 32;
parameter FRAC = 24;
parameter N_OUT = 2;
reg clk;
reg rst;
reg en;
reg signed [N_OUT*WIDTH-1:0] i_d;
wire signed [WIDTH-1:0] o;
endmodule
| 7.332896 |
module cosx_org (
input clk,
rst,
start,
input [9:0] x,
input [7:0] y,
output done,
output [9:0] result,
output [2:0] pss,
output coo,
output is_negg
);
wire co, gt, initr, initt, zc, ldx, s, ldt, enc, ldr, is_neg;
wire [2:0] ps;
controller control (
clk,
rst,
... | 6.500595 |
module cos_make (
input clk,
input rst_n,
output reg [7:0] cos_s,
output reg signed [7:0] cos_c
);
//------------------------------------//
parameter freq_s = 32'd429497; //źƵ10k
parameter freq_c = 32'd42949673; //زƵ1M
parameter cnt_width = 8'd32;
//------------------------------------//
... | 7.412386 |
module Cos_sin #(
parameter ADDR_WIDTH = 2,
DATA_WIDTH = 32
) (
// Inputs
input iClk,
input iRst,
input [13:0] iCx_g,
//Outputs
output [15:0] oY_g
);
reg [31:0] rData;
reg [19:0] rPout;
reg [ 6:0] rCx_g;
reg [19:0] rY_g;
reg [18:0] rCo;
reg [12:0] rC1;
wire [ 6:0] ... | 8.618034 |
module cos_sine (
clk,
rst,
U1,
g0,
g1
);
input clk, rst;
input [15:0] U1;
output [15:0] g0, g1;
reg [18:0] c0[127:0];
reg [11:0] c1[127:0];
wire [1:0] quad;
reg [13:0] xga, xgb, yga, ygb;
initial begin
$readmemh("Z:\ELEN249\netlist\ip_catalog\HwNG\HwNG.srcs\sources_1\new\cos_... | 8.527696 |
module cos_sine (
input clk,
rst_n,
input [9:0] x, //input has a 10-bit resolution(from 0 to 2pi)
output [7:0] y_sine,
y_cos //output has 8-bit resolution(from -1 to 1)
);
reg [7:0] y_sine_q = 0, y_sine_d, y_cos_q = 0, y_cos_d;
reg [7:0] x_sine_addr, x_cos_addr; //determines the address to b... | 8.527696 |
module cos_sine_TB ();
reg clk, rst;
reg [15:0] U1;
wire [15:0] g0, g1;
cos_sine cos_sine1 (
.clk(clk),
.rst(rst),
.U1 (U1),
.g0 (g0),
.g1 (g1)
);
always #10 clk = !clk;
initial begin
clk = 1'b0;
rst = 1'b1;
#30;
rst = 1'b0;
#20;
U1 = 16'b0000_0... | 6.550914 |
module count_up_down_top (
// Inputs
input clk,
input rst_btn,
// Outputs
output reg [3:0] led
);
// Internal signals
wire rst;
wire div_clk;
wire up_done;
wire down_done;
wire [3:0] up_out;
wire [3:0] down_out;
// Storage elements
reg init_go;
... | 7.36293 |
module COUNT #(
parameter N = 7
) (
A,
S
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value;
for (log2 = 0; temp > 0; log2 = log2 + 1) temp = temp >> 1;
end
endfunction
localparam K = log2(N);
localparam K2 = log2(N - 2 ** (K - 1));
i... | 7.615653 |
module top_module (
input clk,
input reset,
output [3:0] q
);
always @(posedge clk)
if (reset || q == 4'd10) q <= 1;
else q <= q + 1;
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
always @(posedge clk)
if (reset || q == 4'd9) q <= 0;
else q <= q + 1;
endmodule
| 7.203305 |
module Adder (
input [31:0] io_in1,
output [31:0] io_out
);
assign io_out = 32'h1 + io_in1; // @[Adder.scala 13:22]
endmodule
| 7.642138 |
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