code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Register (
input clock,
input reset,
input [31:0] io_in,
output [31:0] io_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [31:0] reg_; // @[Register.scala 11:23]
assign io_out = reg_; // @[Register.scala 13:12]
always @(posedge clo... | 7.117303 |
module Count1000_WatchDog (
clk,
rst,
count,
WatchDogEnable,
out
);
input clk, rst, count, WatchDogEnable;
output reg out;
reg [9:0] counter;
always @(posedge clk) begin
if (rst == 0) begin
out <= 0;
counter <= 0;
end else begin
if (WatchDogEnable == 1) begin
... | 6.865403 |
module count10_tb ();
reg rst;
reg clk;
reg en;
wire [3:0] count;
wire co;
initial begin
rst = 0;
clk = 0;
en = 0;
#10 rst = 1;
#10 rst = 0;
en = 1;
end
always #10 clk = ~clk;
count_10 count10 (
rst,
clk,
en,
count,
co
);
endmodule
| 6.645256 |
module count12 (
input clock,
input reset,
output reg [1:0] dig_sel // 2 bit output
);
reg [11:0] counter;
// a 12 bit counter was chosen to get an appropriate
// display refresh rate
wire pulse;
always @(posedge clock) begin
if (reset) counter <= 12'd0; //synchronous reset
el... | 7.086595 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q
);
reg [3:0] acc;
initial acc = 0;
assign q = acc;
always @(posedge clk) begin
if (reset) acc = 4'd0;
else acc += 1'd1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
output [3:0] q
);
reg [3:0] acc;
initial acc = 0;
assign q = acc;
always @(posedge clk) begin
if (reset) acc = 4'd1;
else begin
if (acc == 4'd10) acc = 4'd1;
else acc += 1'd1;
end
end
endmodule
| 7.203305 |
module count32 (
a_clr,
s_clr,
clk,
en,
d
);
/***************************************************/
parameter UDLY = 1;
/***************************************************/
input a_clr;
input s_clr;
input clk;
input en;
output [31:0] d;
/*****************************************... | 6.577514 |
module counter60_tb;
reg clk, rst_n, en;
wire [7:0] dout;
wire co;
always begin
#1 clk = ~clk;
end
initial begin
clk = 1'b0;
rst_n = 1'b1;
en = 1'b0;
#2 rst_n = 1'b0;
#2 rst_n = 1'b1;
en = 1'b1;
end
counter60 u5 (
.clk(clk),
.rst_n(rst_n),
.en(en),
... | 6.599026 |
module count60_td ();
reg rst;
reg clk;
reg en;
wire [7:0] count;
wire co;
initial begin
rst = 0;
clk = 0;
en = 0;
#100 rst = 1;
#40 rst = 0;
en = 1;
end
always #10 clk = ~clk;
count_60 count60 (
rst,
clk,
en,
count,
co
);
endmodule
| 6.508712 |
module count6_tb ();
reg rst;
reg clk;
reg en;
wire [3:0] count;
wire co;
initial begin
rst = 0;
clk = 0;
en = 0;
#100 rst = 1;
#40 rst = 0;
en = 1;
end
always #10 clk = ~clk;
count_6 count6 (
rst,
clk,
en,
count,
co
);
endmodule
| 6.538621 |
module count6_td ();
reg rst;
reg clk;
reg en;
wire [3:0] count;
wire co;
initial begin
rst = 0;
clk = 0;
en = 0;
#100 rst = 1;
#40 rst = 0;
en = 1;
end
always #10 clk = ~clk;
count_6 count6 (
rst,
clk,
en,
count,
co
);
endmodule
| 6.519236 |
module Count8 (
clock,
reset,
enable,
count
);
input clock, reset; // NbNCZbg
input enable; // JEgECl[u
output [2:0] count; // JEgl
// L@\̂M
reg [2:0] count;
// GbWEgK Zbg
always @(posedge clock or negedge reset) begin
if (!reset) begin
count <= 3'b000; // Zbg
end els... | 6.76437 |
module saves us from defining CWidth/Internal
// counters.
//
// TODO: Make the number of Intermediate signals _parameterizable_
// (maybe I'll do this when I see we need more than 1 ...)
//------------------------------------------------------------------------------
module CountAlarm(Clock, Reset, Enable, Int... | 7.415589 |
module: counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module countb;
// Inputs
reg clk;
// Instantiate the Unit Under Test (UUT)
counter uut (
.clk(clk)
);
initial begi... | 7.040838 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q
);
assign ena[1] = (q[3:0] == 4'd9);
assign ena[2] = (ena[1] && q[7:4] == 4'd9);
assign ena[3] = (ena[2] && q[11:8] == 4'd9);
bcd_cnt u_bcd_cnt_1 (
clk,
reset,
1'b1... | 7.203305 |
module countbits (
clk,
data,
ones
);
// parameter DATA_WIDTH = 4;
parameter DATA_WIDTH = 32;
input clk;
input [DATA_WIDTH - 1:0] data;
output [$clog2(DATA_WIDTH):0] ones;
reg [$clog2(DATA_WIDTH):0] ones;
reg [$clog2(DATA_WIDTH):0] v_count;
integer i;
always @(posedge clk) begin... | 7.101221 |
module countbits (
clk,
data,
ones
);
// parameter DATA_WIDTH = 4;
parameter DATA_WIDTH = 32;
input clk;
input [DATA_WIDTH - 1:0] data;
output [2:0] ones;
reg [2:0] ones;
reg [2:0] v_count;
integer i;
always @(posedge clk) begin : COUNT_BITS
v_count = 0;
for (i = 0... | 7.101221 |
module countbits_tb;
parameter DATA_WIDTH = 4;
parameter CLK_PERIOD = 10 /*ns*/;
reg clk;
reg [ DATA_WIDTH - 1:0] data;
wire [$clog2(DATA_WIDTH):0] ones;
integer i;
countbits uut (
.clk (clk),
.data(data),
.ones(ones)
);
... | 7.257471 |
module exploits the fact that we needn't actually
// check EVERY bit to determine equality. The output may be true
// or false for inputs larger than the comparison value. Here's a
// truth table:
//
// Count input TerminalCount output
// < Compare 1'b0
// == Compare 1'b1
// > Compare 1'b... | 7.773643 |
module of Project_Countdown
module countdown(
input clk, rst, clk_1Hz,
input toggle, clear, init_en,
input run,pause,
input [16:0] tar_sec,
output reg [16:0] seconds, // current second status
output reg buzzer = 0,
output reg state = 0, // termination triggers buzzer(1)
output reg... | 7.542411 |
module CountdownTimer10 (
CLOCK,
reset,
start,
value,
pause,
active,
done
);
input CLOCK, reset, start, pause;
output active, done;
output [3:0] value; // provides the value (max 4 bits) of the
// current time on the timer – you’ll pass this on to a BCD decoder,
// and then to a ... | 6.542491 |
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable;
assign c_load = reset | (Q == 4'd12 & enable == 1);
assign c_d = 4'd1;
count4 the_counter (
clk,
c_enable,
c_l... | 7.203305 |
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
);
always @(posedge clk) begin
if (reset) begin
Q <= 4'd1;
end else begin
if (enable) begin
if (Q == 12) begin
Q <= 4'd1;
... | 7.203305 |
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
);
wire [3:0] Q1, Q2, Q3;
bcdcount bcdcount0 (
clk,
reset,
c_enable[0],
Q1
);
bcdcount bcdcount1 (
clk,
reset,
c_enable[1],
Q2
);
bcdcount bcdcount2 (
clk,... | 7.203305 |
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign... | 7.233807 |
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
| 6.939007 |
module
// rst - Reset signal to clear state machine and counter
// go - Go signal to start state machine
//
// Outputs:
// out[3:0] - Bus that counts from 0x0 to 0xf or 0xf to 0x0
// done - Signal that pulses on 1 clock cycle when FSM is complete
//
// Send rising edge o... | 7.111291 |
module counter_top (
clock,
reset,
button,
ones,
tens
);
(* src = "examples/counter.v:73.9-73.15" *)
input button;
wire button;
(* src = "examples/counter.v:78.8-78.24" *)
wire button_debounced;
(* src = "examples/counter.v:71.9-71.14" *)
input clock;
wire clock;
(* src = "examples... | 6.97985 |
module counter_tb ();
reg clk, reset, enable;
wire [3:0] count;
reg dut_error;
counter U0 (
.clk (clk ),
.reset (reset ),
.enable(enable),
.count (count )
);
event reset_enable;
event terminate_sim;
initial begin
$display("######################################... | 7.107233 |
module: counter_09
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module counter09_tb;
// Inputs
reg clk;
reg reset;
integer i;
// Outputs
wire [3:0] out1;
// Instantiate the Uni... | 6.914912 |
module Counter0_7 (
input wire clk,
clr,
output reg out
);
reg [2:0] state;
always @(posedge clk, posedge clr) begin
if (clr) state = 3'd0;
else if (state < 3'd7) state = state + 3'd1;
end
always @(state) begin
out = state >= 3'd4;
end
endmodule
| 7.541967 |
module counter1 #(
parameter CNT_WIDTH = 32
) (
input clk,
input reset,
input valid,
input ready,
output reg [CNT_WIDTH-1:0] cnt1
);
always @(posedge clk) begin
if (reset) cnt1 <= 0;
else if (valid && ready) cnt1 <= cnt1 + 1;
else cnt1 <= cnt1;
end
endmodule
| 6.761208 |
module Counter100ms (
rst,
in_1ms,
out_100ms
);
input rst, in_1ms;
output reg out_100ms;
reg [6:0] cnt1ms;
always @(posedge in_1ms, negedge rst) begin
if (rst == 0) begin
cnt1ms = 7'd0;
out_100ms = 0;
end else begin
if (cnt1ms == 7'd99) begin
out_100ms = 1;
... | 6.538579 |
module counter15b (
clock,
cnt_en,
sclr,
q
);
input clock;
input cnt_en;
input sclr;
output [14:0] q;
wire [14:0] sub_wire0;
wire [14:0] q = sub_wire0[14:0];
lpm_counter lpm_counter_component (
.sclr(sclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
.ac... | 6.532846 |
module Counter16bRev (
clk,
s,
cnt,
Rc
);
input wire clk, s;
output reg [15:0] cnt;
output wire Rc;
initial cnt = 0;
assign Rc = (~s & (~|cnt)) | (s & (&cnt));
always @(posedge clk) begin
if (s) cnt <= cnt + 1;
else cnt <= cnt - 1;
end
endmodule
| 6.797293 |
module Counter16bRev_tb ();
reg clk;
reg s;
wire [15:0] cnt;
wire Rc;
Counter16bRev UUT (
.clk(clk),
.s (s),
.cnt(cnt),
.Rc (Rc)
);
initial begin
$dumpfile("Counter16bRev_tb.vcd");
$dumpvars(0, Counter16bRev_tb);
clk = 0;
s = 1;
#320;
#10;
s = 0;
... | 6.797293 |
module Counter16_LPM (
aclr,
clock,
cnt_en,
q
);
input aclr;
input clock;
input cnt_en;
output [15:0] q;
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
lpm_counter LPM_COUNTER_component (
.aclr(aclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
... | 6.585172 |
module counter18 (
clk,
clr,
ld,
counter,
data
);
input clk, clr, ld;
input [4:0] data;
output [4:0] counter;
reg [4:0] counter;
always @(posedge clk or posedge clr)
if (clr == 1) counter <= 0;
else if (ld == 1) counter <= data;
else if (counter >= 17) counter <= 0;
else c... | 6.943411 |
module delay_1s (
output reg delay,
input CLOCK_50
);
reg [25:0] count;
always @(posedge CLOCK_50) begin
if (count == 26'd1_499_99) begin
count <= 26'd0;
delay <= 1;
end else begin
count <= count + 1;
delay <= 0;
end
end
endmodule
| 6.680783 |
module counter1_5 (
input clk,
input rst,
output reg [1:0] out
);
reg [1:0] M_counter_d, M_counter_q = 1'h0;
always @* begin
M_counter_d = M_counter_q;
out = M_counter_q;
if (M_counter_q == 2'h3) begin
M_counter_d = 1'h0;
end else begin
M_counter_d = M_counter_q + 1'h1;
... | 6.919907 |
module counter1 (
aclr,
clk_en,
clock,
cnt_en,
q
);
input aclr;
input clk_en;
input clock;
input cnt_en;
output [7:0] q;
endmodule
| 6.94605 |
module counter20b (
clock,
cnt_en,
sclr,
q
);
input clock;
input cnt_en;
input sclr;
output [19:0] q;
wire [19:0] sub_wire0;
wire [19:0] q = sub_wire0[19:0];
lpm_counter lpm_counter_component (
.sclr(sclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
.ac... | 6.68982 |
module counter22 (
clk,
rstn,
out
);
output reg [3:0] out = 4'b0000;
input clk;
input rstn;
always @(negedge clk) begin
if (rstn) out <= out + 1;
else out = 4'h0;
end
always @(*) begin
if (!rstn) out = 4'b0000;
end
endmodule
| 7.156961 |
module counter24_and_counter60_tb ();
reg clk, nCR, EN;
wire [3:0] CntH, CntL;
wire [7:0] Cnt;
initial begin
clk = 1'b0;
nCR = 1'b0;
#100 nCR = 1'b1;
EN = 1'b0;
#100 EN = 1'b1;
end
//产生50MHz的时钟
always #10 clk = ~clk;
//引用两个被测试模块
counter24 T0 (
.CntH(CntH),
.CntL(CntL... | 6.550703 |
module counter2Re (
reset,
clock,
en,
q,
clear
);
input clock;
input en;
input reset;
input clear;
output q;
reg [5:0] q_dat;
assign q = (q_dat == 6'd63) ? 1 : 0;
always @(posedge clock)
if (reset) q_dat <= 6'd0;
else begin
if (clear) q_dat <= 0;
else if (q_dat ... | 6.983727 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add2_COUT (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(1'b0),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(... | 7.301465 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
SB_DFF inst0 (
.C(CLK),
.D(I[0]),
.Q(inst0_Q)
);
SB_DFF inst1 (
.C(CLK),
.D(I[1]),
.Q(inst1_Q)
);
assign O = {inst1_Q, inst0_Q};
endmodule
| 6.626169 |
module Counter2_COUT (
output [1:0] O,
output COUT,
input CLK
);
wire [1:0] inst0_O;
wire inst0_COUT;
wire [1:0] inst1_O;
Add2_COUT inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register2 inst1 (
.I (inst0_O),
.O (inst1_O),
... | 7.893937 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
wire inst4_O;
wire inst5_O;
LUT2 #(
.INIT(4'h6)
) inst0 (
.I0(I0[0]),
.I1(I1[0]),
.O (inst0_O)
);
MUXCY inst1 (
.DI(... | 6.529797 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) inst1 (
.C (CLK),
.... | 6.626169 |
module Counter2_COUT (
output [1:0] O,
output COUT,
input CLK
);
wire [1:0] inst0_O;
wire inst0_COUT;
wire [1:0] inst1_O;
Add2_cout inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register2 inst1 (
.I (inst0_O),
.O (inst1_O),
... | 7.893937 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire inst0_O5;
wire inst0_O6;
wire inst1_O;
wire inst2_O;
wire inst3_O5;
wire inst3_O6;
wire inst4_O;
wire inst5_O;
LUT6_2 #(
.INIT(64'h66666666AAAAAAAA)
) inst0 (
.I0(I0[0]),
.I1(I1[0... | 6.529797 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire inst0_Q;
wire inst1_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) inst1 (
.C (CLK),
.... | 6.626169 |
module Counter2_COUT (
output [1:0] O,
output COUT,
input CLK
);
wire [1:0] inst0_O;
wire inst0_COUT;
wire [1:0] inst1_O;
Add2_cout inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register2 inst1 (
.I (inst0_O),
.O (inst1_O),
... | 7.893937 |
module Counter_tb ();
reg clk; // clock
reg rst; // reset
reg enable;
reg up_down;
wire [3:0] number;
Counter2 dut (
.clk(clk),
.rst(rst),
.enable(enable),
.up_down(up_down),
.number(number[3:0])
);
integer num_cycles = 0;
initial begin
$monitor("%64d\n", num_c... | 6.630148 |
module counter3b (
clock,
cnt_en,
sclr,
q
);
input clock;
input cnt_en;
input sclr;
output [2:0] q;
wire [2:0] sub_wire0;
wire [2:0] q = sub_wire0[2:0];
lpm_counter lpm_counter_component (
.sclr(sclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
.aclr(1'... | 6.838697 |
module counter3bit (
input wire clk,
input wire rst,
output reg [2:0] Q
);
always @ (posedge(clk)) // When will Always Block Be Triggered
begin
if (rst == 3'b111)
// How Output reacts when Reset Is Asserted
Q <= 3'b0;
else
// How Output reacts when Rising Edge of Clock Arrives... | 8.2951 |
module counter3b_updwn (
clock,
cnt_en,
sclr,
updown,
q
);
input clock;
input cnt_en;
input sclr;
input updown;
output [2:0] q;
wire [2:0] sub_wire0;
wire [2:0] q = sub_wire0[2:0];
lpm_counter lpm_counter_component (
.sclr(sclr),
.clock(clock),
.updown(updown),
... | 7.246759 |
module counter3_04 (
clk_04,
rst_04,
dout_04
);
input clk_04, rst_04;
output [1:0] dout_04;
reg [1:0] dout_04;
always @(posedge clk_04 or posedge rst_04) begin
if (rst_04) dout_04 <= 0;
else if (dout_04[1:0] == 2'b10) begin
dout_04[1:0] <= 2'b00;
end else begin
dout_04 <= d... | 6.503301 |
module Counter4b (
// Inputs
clk,
// Output
Qb,
Qc,
Qd,
Qa,
Rc
);
// Inputs
input wire clk;
// Output
output wire Qa;
output wire Qb;
output wire Qc;
output wire Qd;
output wire Rc;
wire d2;
wire d3;
wire d4;
RisingEdge_DFlipFlop fd1 (
.D (~Qa),
.c... | 8.266165 |
module counter4bit (
output [3:0] q,
input clk,
input reset
);
wire q0q1;
assign q0q1 = q[0] & q[1];
wire q0q1q2;
assign q0q1q2 = q0q1 & q[2];
jkFlipFlop f0 (
q[0],
1'b1,
1'b1,
clk,
reset
);
jkFlipFlop f1 (
q[1],
q[0],
q[0],
clk,
r... | 6.667356 |
module Counter4b_tb ();
// Inputs
reg clk;
// Output
wire Qb;
wire Qc;
wire Qd;
wire Qa;
wire Rc;
// Bidirs
// reg integer i;
// Instantiate the UUT
Counter4b UUT (
.clk(clk),
.Qb (Qb),
.Qc (Qc),
.Qd (Qd),
.Qa (Qa),
.Rc (Rc)
);
// Initialize Inputs
... | 7.59657 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Register4R (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
SB_DFFSR inst0 (
.C(CLK),
.R(RESET),
.D(I[0]),
.Q(inst0_Q)
);
SB_DFFSR inst1 (
.C(CLK),
.R(RESET),
.D(I[1]),
... | 6.731517 |
module Counter4R (
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] inst0_O;
wire [3:0] inst1_O;
Add4 inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O (inst0_O)
);
Register4R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assi... | 6.774562 |
module Counter4_Mod16_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst1_O;
Counter4R inst0 (
.O(inst0_O),
.CLK(CLK),
.RESET(inst1_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8000)
) inst1 (
.I0(inst0_O[0]),
.I1(inst0_O[1]),
.I2(inst0_O[2... | 7.712729 |
module Register4R (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
.INIT(1'h0)
... | 6.731517 |
module Counter4R (
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] inst0_O;
wire [3:0] inst1_O;
Add4 inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O (inst0_O)
);
Register4R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assi... | 6.774562 |
module Decode4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h8000)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.074411 |
module Counter4_Mod16_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst1_O;
Counter4R inst0 (
.O(inst0_O),
.CLK(CLK),
.RESET(inst1_O)
);
Decode4 inst1 (
.I(inst0_O),
.O(inst1_O)
);
assign O = inst0_O;
assign COUT = inst1_O;
endmodule... | 7.712729 |
module Register4R (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (RESET),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
... | 6.731517 |
module Counter4R (
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] inst0_O;
wire [3:0] inst1_O;
Add4 inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O (inst0_O)
);
Register4R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assi... | 6.774562 |
module Decode4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h8000)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.074411 |
module Counter4_Mod16_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst1_O;
Counter4R inst0 (
.O(inst0_O),
.CLK(CLK),
.RESET(inst1_O)
);
Decode4 inst1 (
.I(inst0_O),
.O(inst1_O)
);
assign O = inst0_O;
assign COUT = inst1_O;
endmodule... | 7.712729 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Register4R (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
SB_DFFSR inst0 (
.C(CLK),
.R(RESET),
.D(I[0]),
.Q(inst0_Q)
);
SB_DFFSR inst1 (
.C(CLK),
.R(RESET),
.D(I[1]),
... | 6.731517 |
module Counter4R (
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] inst0_O;
wire [3:0] inst1_O;
Add4 inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O (inst0_O)
);
Register4R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assi... | 6.774562 |
module Counter4_Mod1_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst1_O;
Counter4R inst0 (
.O(inst0_O),
.CLK(CLK),
.RESET(inst1_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0001)
) inst1 (
.I0(inst0_O[0]),
.I1(inst0_O[1]),
.I2(inst0_O[2]... | 7.712729 |
module Register4R (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
.INIT(1'h0)
... | 6.731517 |
module Counter4R (
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] inst0_O;
wire [3:0] inst1_O;
Add4 inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O (inst0_O)
);
Register4R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assi... | 6.774562 |
module Decode4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h0001)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.074411 |
module Counter4_Mod1_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst1_O;
Counter4R inst0 (
.O(inst0_O),
.CLK(CLK),
.RESET(inst1_O)
);
Decode4 inst1 (
.I(inst0_O),
.O(inst1_O)
);
assign O = inst0_O;
assign COUT = inst1_O;
endmodule
... | 7.712729 |
module Register4R (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (RESET),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
... | 6.731517 |
module Counter4R (
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] inst0_O;
wire [3:0] inst1_O;
Add4 inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O (inst0_O)
);
Register4R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assi... | 6.774562 |
module Decode4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h0001)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.074411 |
module Counter4_Mod1_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst1_O;
Counter4R inst0 (
.O(inst0_O),
.CLK(CLK),
.RESET(inst1_O)
);
Decode4 inst1 (
.I(inst0_O),
.O(inst1_O)
);
assign O = inst0_O;
assign COUT = inst1_O;
endmodule
... | 7.712729 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Register4R (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
SB_DFFSR inst0 (
.C(CLK),
.R(RESET),
.D(I[0]),
.Q(inst0_Q)
);
SB_DFFSR inst1 (
.C(CLK),
.R(RESET),
.D(I[1]),
... | 6.731517 |
module Counter4R (
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] inst0_O;
wire [3:0] inst1_O;
Add4 inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O (inst0_O)
);
Register4R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assi... | 6.774562 |
module Counter4_Mod8_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst1_O;
Counter4R inst0 (
.O(inst0_O),
.CLK(CLK),
.RESET(inst1_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0080)
) inst1 (
.I0(inst0_O[0]),
.I1(inst0_O[1]),
.I2(inst0_O[2]... | 7.556283 |
module Register4R (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
.INIT(1'h0)
... | 6.731517 |
module Counter4R (
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] inst0_O;
wire [3:0] inst1_O;
Add4 inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O (inst0_O)
);
Register4R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assi... | 6.774562 |
module Decode4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h0080)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.074411 |
module Counter4_Mod8_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst1_O;
Counter4R inst0 (
.O(inst0_O),
.CLK(CLK),
.RESET(inst1_O)
);
Decode4 inst1 (
.I(inst0_O),
.O(inst1_O)
);
assign O = inst0_O;
assign COUT = inst1_O;
endmodule
... | 7.556283 |
module Register4R (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
FDRSE #(
.INIT(1'h0)
) inst0 (
.C (CLK),
.CE(1'b1),
.R (RESET),
.S (1'b0),
.D (I[0]),
.Q (inst0_Q)
);
FDRSE #(
... | 6.731517 |
module Counter4R (
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] inst0_O;
wire [3:0] inst1_O;
Add4 inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b1}),
.O (inst0_O)
);
Register4R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assi... | 6.774562 |
module Decode4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h0080)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.074411 |
module Counter4_Mod8_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] inst0_O;
wire inst1_O;
Counter4R inst0 (
.O(inst0_O),
.CLK(CLK),
.RESET(inst1_O)
);
Decode4 inst1 (
.I(inst0_O),
.O(inst1_O)
);
assign O = inst0_O;
assign COUT = inst1_O;
endmodule
... | 7.556283 |
module counter4p (
clk,
rstn, // clock to see the 4p time to change the address of the ifmap
out
);
// This always block will be triggered at the falling edge of clk (0->1)
// Once inside this block, it checks if the reset is 0, if yes then change out to zero
// If reset is 1, then design should be ... | 7.333828 |
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