code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module c_mat_mult (
input_a,
input_b,
result
);
`include "c_constants.v"
// matrix dimensions
parameter dim1_width = 1;
parameter dim2_width = 1;
parameter dim3_width = 1;
// multiplication operator
parameter prod_op = `BINARY_OP_AND;
// addition operator
parameter sum_op = `BINARY_OP_... | 7.668949 |
module c_multi_hot_det (
data,
multi_hot
);
`include "c_constants.v"
`include "c_functions.v"
// width of input vector
parameter width = 8;
// number of reduction levels required
localparam num_levels = clogb(width);
// smallest power-of-two width that is greater than or equal to width
local... | 7.850922 |
module
*/
`define allXs {C_WIDTH{1'bx}}
`define allZs {C_WIDTH{1'bz}}
module C_MUX_SLICE_BUFE_V4_0 (I, OE, O);
parameter C_WIDTH = 16; /* Width of the single input */
input [C_WIDTH-1 : 0] I;
input OE;
output [C_WIDTH-1 : 0] O;
reg [C_WIDTH-1 : 0] intO;
wire [C_WIDTH-1 : 0] #1 O = intO;
initial ... | 6.557481 |
module
*/
`define allXs {C_WIDTH{1'bx}}
`define allZs {C_WIDTH{1'bz}}
module C_MUX_SLICE_BUFT_V4_0 (I, T, O);
parameter C_WIDTH = 16; /* Width of the single input */
input [C_WIDTH-1 : 0] I;
input T;
output [C_WIDTH-1 : 0] O;
reg [C_WIDTH-1 : 0] intO;
wire [C_WIDTH-1 : 0] #1 O = intO;
initial
... | 6.557481 |
module c_m_para_3 #(
parameter LENGTH = 14
) (
input [LENGTH-1:0] data_in_0,
input [LENGTH-1:0] data_in_1,
output [ LENGTH:0] data_out_0,
output [ LENGTH:0] data_out_1
);
wire [LENGTH:0] tmp_data_re_0_w;
wire [LENGTH:0] tmp_data_re_1_w;
wire [LENGTH:0] tmp_data_re_2_w;
wire [LENGTH:0] t... | 6.679578 |
module c_one_hot_filter (
data_in,
data_out
);
`include "c_functions.v"
// width of input vector
parameter width = 8;
// number of stages
localparam depth = clogb(width);
// width rounded up to nearest power of two
localparam ext_width = (1 << depth);
// input data
input [0:width-1] data_... | 8.160366 |
module c_one_hot_therm_conv (
data_in,
data_out
);
`include "c_functions.v"
// number of input ports (i.e., decoded width)
parameter width = 8;
// number of stages
localparam depth = clogb(width);
// one-hot input data
input [0:width-1] data_in;
// thermometer-style encoded output data
ou... | 7.492616 |
module PCstk (/* in */ T_RST, DSPCLK, PCin, PushPC_EN, PopPC_EN,
PCS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopPC, nTopPC, PC_full, PC_empty,
PC_has1);
input [13:0] PCin;
input T_RST, DSPCLK, PushPC_EN, PopPC_EN, PCS_CKenb;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [13:0] TopPC,
nTopPC;
output PC_empty,
PC_full,
... | 6.939359 |
module PCS16x14 (
PCSCLK,
WE,
WA,
stkin,
RA,
RA_m,
TopPC,
nTopPC
);
output [13:0] TopPC, nTopPC;
input [13:0] stkin;
input [3:0] RA, RA_m, WA;
input PCSCLK, WE;
reg [13:0] PCcell[15:0];
reg [13:0] TopPC, nTopPC;
always @(posedge PCSCLK) if (WE) PCcell[WA] <= #`db stki... | 7.993148 |
module c_prefix_net (
g_in,
p_in,
g_out,
p_out
);
`include "c_functions.v"
// width of inputs
parameter width = 16;
// generate wraparound connections
parameter enable_wraparound = 0;
// number of stages
localparam depth = clogb(width);
// width rounded up to nearest power of two
... | 8.449719 |
module c_prio_sel (
priorities,
enable,
select
);
`include "c_functions.v"
// number of input ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 16;
// width of priority fields
localparam prio_width = clogb(num_priorities);
// priority values
input... | 7.906821 |
module c_rand (
clk,
rst,
reseed,
seed_val,
out
);
input clk, rst, reseed;
input [31:0] seed_val;
output [15:0] out;
wire [15:0] out;
reg [31:0] state;
always @(posedge clk or posedge rst) begin
if (rst) state <= 0;
else begin
if (reseed) state <= seed_val;
else be... | 7.163439 |
module c_reduce_bits (
data_in,
data_out
);
`include "c_constants.v"
// number of input ports
parameter num_ports = 1;
// width of each port
parameter width = 32;
// operator
parameter op = `BINARY_OP_AND;
// vector of inputs
input [0:num_ports*width-1] data_in;
// result
output [0:n... | 7.578329 |
module c_rotate (
amount,
data_in,
data_out
);
`include "c_functions.v"
`include "c_constants.v"
// width of input data
parameter width = 8;
// direction in which to rotate
parameter rotate_dir = `ROTATE_DIR_LEFT;
// width of rotation amount
localparam amount_width = clogb(width);
// ... | 8.09715 |
module c_rr_arbiter (
clk,
reset,
active,
req_pr,
gnt_pr,
gnt,
update
);
`include "c_constants.v"
`include "c_functions.v"
// number of input ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 1;
// store priorities in encoded form
par... | 7.191157 |
module c_samq_tracker (
clk,
reset,
active,
push_valid,
push_sel_qu,
pop_valid,
pop_sel_qu,
almost_empty_qu,
empty_qu,
almost_full_qu,
full_qu,
two_free_qu,
errors_qu
);
`include "c_functions.v"
`include "c_constants.v"
//-------------------------------------... | 6.878437 |
module c_select_mofn (
select,
data_in,
data_out
);
`include "c_constants.v"
// number of input ports
parameter num_ports = 4;
// width of each port
parameter width = 32;
// multiplication operator
parameter prod_op = `BINARY_OP_AND;
// addition operator
parameter sum_op = `BINARY_OP_... | 8.445352 |
module c_shift_reg (
clk,
reset,
active,
data_in,
data_out
);
`include "c_constants.v"
// width of register
parameter width = 32;
// depth of register (number of levels)
parameter depth = 2;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// ... | 9.198213 |
module STS7x23 (
STSCLK,
WE,
WA,
stkin,
RA,
TopST
);
output [24:0] TopST;
input [24:0] stkin;
input [2:0] RA, WA;
input STSCLK, WE;
reg [24:0] STcell[6:0];
wire [24:0] TopST;
always @(posedge STSCLK) if (WE) STcell[WA] <= #1 stkin[24:0];
assign TopST[24:0] = STcell[RA];... | 7.375809 |
module c_testbench ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
localparam BAUD_RATE = 115_200;
localparam BAUD_PERIOD = 1_000_000_000 / BAUD_RATE; // 8680.55 ns
localparam TIMEOUT_CYCLE = 100_000;
initial clk = 0;
always #(CPU_CLOCK_... | 7.336079 |
module c_tests_tb ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
localparam TIMEOUT_CYCLE = 100_000;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk = ~clk;
reg bp_enable = 1'b0;
cpu #(
.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ),
... | 7.444628 |
module c_unit_tb;
// Inputs
reg rst_done, clk, rst;
reg [3:0] select;
// Outputs
wire bg0, mar_lr, c1, mar_c, rev_out, bln_out;
control c_unit (
.select(select),
.rst_done(rst_done),
.clk(clk),
.bg0(bg0),
.mar_lr(mar_lr),
.c1(c1),
.mar_c(mar_c),
.rev_out(r... | 6.925615 |
module c_wf_alloc (
clk,
reset,
active,
req_pr,
gnt_pr,
gnt,
update
);
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
// number of priority levels
parameter num_priorities = 1;
// when s... | 8.475834 |
module c_xor_and_go_back #(
parameter MOD_WIDTH = 12,
GO_BACK_STAGE = 0,
GO_BACK_POLY = 0,
C_POLY = 0
) (
input clk,
input rst,
input eop_in,
input dval_in,
input [MOD_WIDTH-1:0] mod_in,
input [31:0] din,
output crc_en_... | 7.709553 |
module c_xor_and_go_back_top #(
parameter GO_BACK_STAGE = 0,
PKT_NUM = 0,
GO_BACK_POLY = 0,
C_POLY = 0
) (
input clk,
input rst,
input [ PKT_NUM-1:0] eop_in,
input [ PKT_NUM-1:0] dval_in,
input [12*PKT_NUM-1:0] mod_in,
input [32*PK... | 7.709553 |
module VDFF (
D,
Clk,
reset,
Q
);
input D, Clk, reset;
output Q;
reg Q;
always @(posedge Clk or posedge reset) begin
if (reset) Q <= 1'b0;
else Q <= D;
end
endmodule
| 7.548142 |
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q
); //
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk) begin
q <= d;
end
endmodul... | 7.203305 |
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305 |
module top_module (
input d,
input ena,
output q
);
always @(d or ena) if (ena) q <= d;
endmodule
| 7.203305 |
module dcache(
input clk,
input reset,
input [15:0] addr, // 64 kB of total memory
input en,
input we,
output [31:0] cache_do,
output ack,
output [15:0] main_memory_addr,
output main_memory_en,
output main_memory_we,
output [31:0] main_memory_di,
input main_memory_ack,
input [31:0] main_memory_do
);
/... | 7.418951 |
module D_EX (
input clk,
rst,
input [4:0] src_1,
input [4:0] src_2,
input [4:0] dest_in,
input [31:0] Reg1_in,
input [31:0] Reg2_in,
input [31:0] out_mux_reg_2_o_imm_in,
input Branch_in,
input Jump_in,
input MemtoReg_in,
input [1:0] MemRead_in,
input [1:0] MemWrite_in... | 7.528716 |
module flipflop1 (
d,
clk,
q
);
input d, clk;
output reg q;
always @(posedge clk) begin //posedge : clk -> clk가 0->1될때그 순간저장
q <= d;
end
endmodule
| 6.709308 |
module dff (
q,
d,
wen,
clk,
rst
);
output q; //DFF output
input d; //DFF input
input wen; //Write Enable
input clk; //Clock
input rst; //Reset (used synchronously)
reg state;
assign q = state;
always @(posedge clk) begin
state = rst ? 0 : (wen ? d : state);
end
endmo... | 8.035763 |
module main (
input wire CLOCK_50, //On Board 50 MHz
input wire [9:0] SW, // On board Switches
input wire [3:0] KEY, // On board push buttons
output wire [6:0] HEX0, // HEX displays
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3,
output wire [6:0] HEX4,
ou... | 7.081372 |
module
module main (
input wire CLOCK_50, //On Board 50 MHz
input wire [9:0] SW, // On board Switches
input wire [3:0] KEY, // On board push buttons
output wire [6:0] HEX0, // HEX displays
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3,
output wir... | 9.001229 |
module top (
SW,
LEDR
);
input [9:0] SW;
output [9:0] LEDR;
d_flipflop_enable u1 (
SW[0],
SW[9],
SW[8],
SW[1],
LEDR[0]
);
endmodule
| 6.514573 |
module d_flipflop_enable (
d,
clock,
enable,
resetn,
q
);
input d, clock, resetn, enable;
output reg q;
always @(negedge clock) begin
if (resetn == 0) q <= 0;
else if (enable == 1) q <= d;
end
endmodule
| 6.877434 |
module D_latch_tb;
reg D, enable;
wire Q;
D_latch UUT (
Q,
D,
enable
);
//stimulus block
initial begin
D = 1'b0;
enable = 1'b0;
//#10 Clk = ~Clk;
#10 D = 1'b1;
enable = ~enable;
#10 D = ~D;
enable = ~enable;
#10 enable = ~enable;
end
initial $monitor("... | 6.719464 |
module D009_20131209_ALARMCLK (
clk,
rst,
counterOut,
Borrow
);
//for H:MM:SS
parameter DownFrom = 3;
parameter Bitwidth = 4;
// input/ output
input clk, rst;
output [Bitwidth-1:0] counterOut;
output Borrow;
// wiring
wire clk, rst;
wire [Bitwidth-1:0] counterOut;
// save value... | 6.836152 |
module D009_20131209_ALARMCLKa (
clk,
rst,
counterOut,
Borrow
);
//for H
parameter DownFrom = 10;
parameter Bitwidth = 4;
// input/ output
input clk, rst;
output [Bitwidth-1:0] counterOut;
output Borrow;
// wiring
wire clk, rst;
wire [Bitwidth-1:0] counterOut;
// save value pl... | 6.836152 |
module D0_fifo #(
parameter data_width = 6,
parameter address_width = 2
) (
input clk,
reset_L,
wr_enable,
rd_enable,
init,
input [data_width-1:0] data_in,
input [3:0] Umbral_D0,
output full_fifo_D0,
output empty_fifo_D0,
output almost_full_fifo_D0,
output almost_empt... | 6.93548 |
module invert (
input wire i,
output wire o1
);
assign o1 = !i;
endmodule
| 7.953624 |
module and2 (
input wire i0,
i1,
output wire o2
);
assign o2 = i0 & i1;
endmodule
| 8.35921 |
module or2 (
input wire i0,
i1,
output wire o3
);
assign o3 = i0 | i1;
endmodule
| 8.541431 |
module xor2 (
input wire i0,
i1,
output wire o4
);
assign o4 = i0 ^ i1;
endmodule
| 8.782532 |
module nand2 (
input wire i0,
i1,
output wire o5
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o5
);
endmodule
| 7.360689 |
module d16_aleas (
input sys_clk,
input sys_rst,
input [7:0] di_ex_op,
input [15:0] di_ex_a,
input [7:0] ex_mem_op,
input [15:0] ex_mem_a,
input [7:0] li_di_op,
input [15:0] li_di_a,
input [15:0] li_di_b,
input [15:0] li_di_c,
input jmp,
output [7:0] li_di_op_out,
out... | 8.321263 |
module d16_cpt16 (
input sys_clk,
input sys_rst,
input dir,
input load,
input en,
input [15:0] din,
output [15:0] dout
);
reg [15:0] cpt;
task init;
begin
cpt <= 16'b0;
end
endtask
initial begin
init;
end
assign dout = cpt;
reg len;
always @(posedge sy... | 6.857791 |
module d16_jmp (
input sys_clk,
input sys_rst,
input [7:0] op,
input [15:0] a,
input [15:0] b,
// input z,
output li_di_rst,
output [15:0] mem_addr,
output load
);
`include "d16.vh"
wire [15:0] addr = (op == D16_OP_JMR) ? b : a;
wire jmp =
((op == D16_OP_JMZ && b == 16'b0)... | 8.469108 |
module d16_pipeline (
input [7:0] op,
input [15:0] a,
input [15:0] b,
input [15:0] c,
output reg [7:0] op_out,
output reg [15:0] a_out,
output reg [15:0] b_out,
output reg [15:0] c_out,
input sys_clk,
input en,
input sys_rst
);
task init;
begin
op_out <= 8'b0;
... | 7.171745 |
module d16_registers (
input sys_clk,
input sys_rst,
input [3:0] addr_a,
input [3:0] addr_b,
input [3:0] addr_w,
input w,
input [15:0] data,
output [15:0] qa,
output [15:0] qb
);
reg [15:0] regs[15:0];
task init;
integer i;
begin
for (i = 0; i < 16; i = i + 1) beg... | 7.420527 |
module D1_fifo #(
parameter data_width = 6,
parameter address_width = 2
) (
input clk,
reset_L,
wr_enable,
rd_enable,
init,
input [data_width-1:0] data_in,
input [3:0] Umbral_D1,
output full_fifo_D1,
output empty_fifo_D1,
output almost_full_fifo_D1,
output almost_empt... | 6.893372 |
module fulladdR(input wire [3:0] a, b, input wire cin, output wire [3:0] sum, output wire cout);
// Instantiate full adder modules here.
wire [2:0] c;
write your code here
endmodule
| 8.092984 |
module d24h (
output z0,
output z1,
output z2,
output z3,
input a0,
input a1
);
// from tosh_to_moto.v
wire ab;
wire bb;
wire ai;
wire bi;
assign ab = ~a0;
assign bb = ~a1;
assign ai = ~ab;
assign bi = ~bb;
assign z3 = ~(ab | bb);
assign z2 = ~(ai | bb);
assign z1 ... | 7.242854 |
module INV1_H (
A,
Q
);
parameter delay = 5;
input A;
output Q;
assign #delay Q = !A;
endmodule
| 7.221091 |
module INV10_H (
A,
Q
);
parameter delay = 5;
input A;
output Q;
assign #delay Q = !A;
endmodule
| 7.808974 |
module BUF4_H (
A,
Q
);
parameter delay = 5;
input A;
output Q;
assign #delay Q = A;
endmodule
| 6.660009 |
module XNR21_H (
A,
B,
Q
);
parameter delay = 5;
input A;
input B;
output Q;
assign #delay Q = !(A ^ B);
endmodule
| 7.301385 |
module XOR21_H (
A,
B,
Q
);
parameter delay = 5;
input A;
input B;
output Q;
assign #delay Q = (A ^ B);
endmodule
| 7.169623 |
module NAND21_H (
A,
B,
Q
);
parameter delay = 5;
input A;
input B;
output Q;
assign #delay Q = !(A && B);
endmodule
| 7.011343 |
module NAND31_H (
A,
B,
C,
Q
);
parameter delay = 5;
input A;
input B;
input C;
output Q;
assign #delay Q = !(A && B && C);
endmodule
| 6.809851 |
module NAND41_H (
A,
B,
C,
D,
Q
);
parameter delay = 5;
input A;
input B;
input C;
input D;
output Q;
assign #delay Q = !(A && B && C && D);
endmodule
| 7.097812 |
module NOR21_H (
A,
B,
Q
);
parameter delay = 5;
input A;
input B;
output Q;
assign #delay Q = !(A || B);
endmodule
| 6.746172 |
module DFC1_H (
D,
C,
RN,
Q,
QN
);
parameter delay = 5;
input D, C, RN;
output Q, QN;
reg Q, QN;
always @(posedge C or negedge RN)
if (!RN) begin
Q <= #delay 0;
QN <= #delay 1;
end else begin
Q <= #delay D;
QN <= #delay !D;
end
endmodule
| 6.572838 |
module MUX21_H (
A,
B,
S,
Q
);
parameter delay = 5;
input A;
input B;
input S;
output Q;
assign Q = (B && S) || (A && (!S));
endmodule
| 7.824991 |
module D2STR_B #(
parameter integer len = 16 // Symbols to show
) (
output wire [ 127:0] str,
input wire [len-1:0] d
);
genvar i;
generate
for (i = 0; i < len; i = i + 1) begin
assign str[8*i+7:8*i] = d[i] ? "1" : "0";
end
for (i = len; i < 16; i = i + 1) begin
assign str[8*i+... | 7.047833 |
module top (
input wire ext_clk, // external xtal generator connection
input wire ext_reset_n, // hardware resrt button
output wire [10:1] tn, // for test purposes
output reg MHZ_10
);
/* devboard PS-06 has 50MHz oscillator connected to the pin 23 */
/* we have to obtain 10MHz clock */
reg [3... | 7.233807 |
module D3 (
input [1:0] in
, output out
);
parameter NUM_GATES = 4;
wire [NUM_GATES - 1:0] LW;
wire [NUM_GATES - 1:0] w;
genvar i;
generate
for (i = 0; i < NUM_GATES; i++) begin : L
LCELL lcell_inst (
.in (LW[i])
, .out(w[i])
);
end
endgenerate
nor (LW... | 6.605174 |
module d38gh (
output z0,
output z1,
output z2,
output z3,
output z4,
output z5,
output z6,
output z7,
input a0,
input a1,
input a2,
input gn
);
// from tosh_to_moto.v
wire ab;
wire bb;
wire cb;
wire ai;
wire bi;
wire ci;
wire gg;
assign ab = ~a0;... | 7.303409 |
module d38h (
output z0,
output z1,
output z2,
output z3,
output z4,
output z5,
output z6,
output z7,
input a0,
input a1,
input a2
);
// from tosh_to_moto.v
wire ab;
wire bb;
wire cb;
wire a, b, c;
assign a = a0;
assign b = a1;
assign c = a2;
assign... | 7.478944 |
module d416g2l (
output z0,
output z1,
output z2,
output z3,
output z4,
output z5,
output z6,
output z7,
output z8,
output z9,
output z10,
output z11,
output z12,
output z13,
output z14,
output z15,
input a0,
input a1,
input a2,
input a3,
... | 7.332109 |
module d416gh (
output z0,
output z1,
output z2,
output z3,
output z4,
output z5,
output z6,
output z7,
output z8,
output z9,
output z10,
output z11,
output z12,
output z13,
output z14,
output z15,
input a0,
input a1,
input a2,
input a3,
... | 6.862049 |
module D5M_Detect (
iClk,
iRst_n,
s_read,
s_readdata,
s_cs,
iDetect,
s_write,
s_writedata,
oThreshold
);
input iClk;
input iRst_n;
input iDetect;
input s_cs;
input s_read;
output [31:0] s_readdata;
input s_write;
input [31:0] s_writedata;
output [31:0] oThreshold... | 7.914608 |
module D7seg (
input [3:0] dig,
output wire [6:0] seg
);
//gfedcba
assign seg = (dig == 0) ? 7'b1000000 : //0 a
(dig == 1) ? 7'b1111001 : //1 f| |b
(dig == 2) ? 7'b0100100 : //2 g
(dig == 3) ? 7'b0110000 : //3 e| |c
(dig == 4) ? 7'b0011001 : //4 d
(dig == 5) ? 7... | 6.582163 |
module D8M_WRITE_COUNTER (
input [11:0] iDATA,
input iFVAL,
input iLVAL,
input iCLK,
input iRST,
output reg [15:0] X_Cont,
output reg [15:0] Y_Cont,
output reg [15:0] X_TOTAL,
output reg [15:0] Y_TOTAL,
output reg [15:0] X_WR_C... | 7.554676 |
module da2 (
input clk,
input rst_n,
input [13:0] real_da1,
input [13:0] real_da2,
output [13:0] dadata1,
output [13:0] dadata2
);
reg [13:0] reg_dadata1;
reg [13:0] reg_dadata2;
assign dadata1 = reg_dadata1;
assign dadata2 = reg_dadata2;
always @(posedge clk or negedge rst_n) begin... | 8.079624 |
module DA9767 #(
parameter INPUT_WIDTH = 14,
parameter INPUT_STYLE = "signed",
parameter ALIGNED_STYLE = "LSB"
) (
input clk_in,
input [INPUT_WIDTH - 1 : 0] DA_data,
output DA_clk,
output DA_wrt,
output [ ... | 7.641487 |
module dac #(
parameter MSBI = 7 // Most significant Bit of DAC input
) (
input wire clock,
input wire reset,
input wire [MSBI:0] d, // DAC input (excess 2**MSBI)
output reg q // This is the average output that feeds low pass filter
); // for optimum perfo... | 7.030321 |
module dac081c081_model (
SCL,
SDA,
VOUT
);
input SCL;
inout SDA;
output [15:0] VOUT;
parameter ADR0 = "VA";
localparam [1:0] A = {(ADR0 == "VA"), (ADR0 == "GND")};
localparam [6:0] I2C_ADR = {5'b00011, A};
localparam [7:0] DAC_DEFAULT = {8{1'b0}};
reg [ 7:0] dac_register = DAC_DEFAULT... | 7.271884 |
module DAC121S101 (
// OUTPUTs
vout, // Peripheral data output
// INPUTs
din, // SPI Serial Data
sclk, // SPI Serial Clock
sync_n // SPI Frame synchronization signal (low active)
);
// OUTPUTs
//=========
output [11:0] vout; // Peripheral data output
// INPUTs
//=========
in... | 7.396101 |
module dac1411 #(
parameter ZMOD_DATA_SIZE = 14
) (
input wire i_sys_clock,
input wire i_dac_clock,
input wire i_reset,
input wire [ZMOD_DATA_SIZE - 1 : 0] i_data_ch1,
input wire [ZMOD_DATA_SIZE - 1 : 0] i_... | 6.805422 |
module DAC16 (
input LOAD,
input RESET_N,
input CLK_50,
input [15:0] DATA16,
output reg SYNC,
output reg SCLK,
output reg DIN,
//--test
output reg SYS_CLK,
output reg [7:0] ST,
output reg [7:0] CNT,
output reg [23:0] RDATA,
output DIN_
);
parameter TIM = 4; // ... | 7.36234 |
module DAC3162_driver (
input clk_in,
input clk_div,
input [11:0] DA3162_CH1,
input [11:0] DA3162_CH2,
/*DAC*/
output [11:0] dac_data_p,
output [11:0] dac_data_n,
output dac_clk_p,
output dac_clk_n,
output dac_sleep
);
assign dac_sleep = 1'd1;
reg [1... | 6.847643 |
module dac3484_intf (
input clk250m, // dac module input clk,
input clk500m, // dac module input clk,ȱ500M
input clk500m_90, // dac module input clk,ȱ500M
input rst,
input [15:0] din0, // input data, 250M SPS
input [15:0] din1,
... | 7.295633 |
module can operate with DAC712 IC for Digital to Analog Conversion.
// Dependencies:
// hardware DAC712 IC
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments: simulated file reference dac712_interface_test.v
//
//////////////////////////////////////////////////////////////////////////////////... | 8.399165 |
module dac8551 #(
parameter CLK_DIV = 10 // SPI clock is: f(spi) = f(i_clk)/(2*CLK_DIV)
) (
// SysCon
input i_clk,
input i_rst,
// Data bus: data to be written and WR strobe
input i_wr,
input [23:0] i_wr_data,
// DAC pins
output o_dac_sclk,
output o_dac_mosi,
output o_dac_sy... | 8.281912 |
module DAC8564 (
input nReset,
input Clk, // max 50 MHz
input Sync,
output reg nSync,
output reg SClk,
output Data,
input [63:0] Current
);
//------------------------------------------------------------------------------
reg [ 2:0] state;
reg [ 4:0] count;
reg [23:0] tdata... | 6.774221 |
module DAC8568Bitbang (
input wire clk,
input wire [31:0] data,
input wire wr_en,
output reg busy,
output wire dac_clk_enable,
output wire dac_sync,
output wire dac_din
);
reg [31:0] data_to_send = 32'h0;
reg [7:0] bits_to_send = 8'h0;
reg csb = 0;
assign dac_din = data_to_send[31]... | 6.959292 |
module UseDAC (
input clk,
input [15:0] data, //
output CS,
output SCLK,
output SerialData //
);
integer i;
reg sclk2;
wire SCLK2;
assign SCLK2 = sclk2;
initial sclk2 <= 0;
always @(posedge clk) begin
if (i < 10) i <= i + 1; //control the sclk
else begin
i <= 0;
sc... | 7.188588 |
module daccc (
clk,
reset,
dac_data_in,
adc_data_out,
adcdat,
m_clk,
b_clk,
dac_lr_clk,
adc_lr_clk,
dacdat,
flancadcclk,
dac_fifo_empty,
adc_fifo_full
);
input clk, reset, adcdat;
input [31:0] dac_data_in;
input dac_fifo_empty, adc_fifo_full;
output [31:0] ad... | 7.419273 |
module rx_DACheck_TB;
reg clk;
reg rst;
reg I_en_ck;
reg I_en_mix;
reg [ 3:0] I_da_hf;
reg [11:0] I_rd_cnt;
wire O_da_ok;
wire O_da_err;
parameter CLOCK_PERIOD = 50;
MAC rx_DAC_TB (
//rx_DACheck rx_DAC_TB(
.clk (clk),
.rst (r... | 6.959543 |
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