code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cyclonev_termination (
rzqin,
enserusr,
nclrusr,
clkenusr,
clkusr,
scanen,
serdatafromcore,
scanclk,
otherenser,
serdatain,
serdataout,
enserout,
compoutrup,
compoutrdn,
serdatatocore,
scanin,
scanout,
clkusrdftout
);
paramete... | 6.68849 |
module cyclonev_asmiblock (
dclk,
sce,
oe,
data0out,
data1out,
data2out,
data3out,
data0oe,
data1oe,
data2oe,
data3oe,
data0in,
data1in,
data2in,
data3in
);
parameter lpm_type = "cyclonev_asmiblock";
input dclk;
input sce;
input oe;
input data0out... | 6.590754 |
module cyclonev_crcblock (
clk,
shiftnld,
crcerror,
regout
);
parameter oscillator_divider = 256;
parameter lpm_type = "cyclonev_crcblock";
input clk;
input shiftnld;
output crcerror;
output regout;
cyclonev_crcblock_encrypted inst (
.clk(clk),
.shiftnld(shiftnld),
.c... | 6.751086 |
module cyclonev_tsdblock (
clk,
ce,
clr,
tsdcalo,
tsdcaldone
);
parameter clock_divider_enable = "on";
parameter clock_divider_value = 40;
parameter sim_tsdcalo = 0;
parameter lpm_type = "cyclonev_tsdblock";
input clk;
input ce;
input clr;
output [7:0] tsdcalo;
output tsdcaldone... | 6.666728 |
module cyclonev_lfifo (
input clk, //clock - half-rate
input rstn, //RESET_N
input rdataen, //RDATA_EN from PHY AFI
input rdataenfull, //RDATA_EN_FULL from PHY AFI
input [4:0] rdlatency, //READ Latency Value
output rdatavalid, //RDATA_VALID to... | 6.844523 |
module cyclonev_oscillator (
oscena,
clkout,
clkout1
);
input oscena;
output clkout;
output clkout1;
cyclonev_oscillator_encrypted inst (
.oscena (oscena),
.clkout (clkout),
.clkout1(clkout1)
);
endmodule
| 6.622895 |
module cyclonev_hssi_pma_aux #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter cal_clk_sel = "pm_aux_iqclk_cal_clk_sel_cal_clk", //Valid values: pm_aux_iqclk_cal_clk... | 7.428145 |
module cyclonev_hssi_pma_rx_buf #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter cdrclk_to_cgb = "cdrclk_2cgb_dis", //Valid values: cdrclk_2cgb_dis|cdrclk_2cgb_en
... | 7.428145 |
module cyclonev_hssi_pma_rx_deser #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter auto_negotiation = "false", //Valid values: false|true
parameter channel_num... | 7.428145 |
module cyclonev_hssi_pma_tx_ser #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter auto_negotiation = "false", //Valid values: false|true
parameter channel_numbe... | 7.428145 |
module cyclonev_hssi_rx_pcs_pma_interface #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter selectpcs = "eight_g_pcs", //Valid values: eight_g_pcs|default
param... | 7.428145 |
module cyclonev_hssi_tx_pcs_pma_interface #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter selectpcs = "eight_g_pcs", //Valid values: eight_g_pcs|default
param... | 7.428145 |
module cyclonev_hssi_tx_pld_pcs_interface #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter is_8g_0ppm = "false", //Valid values: false|true
parameter pld_side_... | 7.428145 |
module cyclonev_hssi_refclk_divider #(
parameter lpm_type = "cyclonev_hssi_refclk_divider",
parameter divide_by = 1,
parameter enabled = "true",
parameter refclk_coupling_termination = "normal_100_ohm_termination"
) (
input [0:0] refclkin,
... | 7.428145 |
module cyclonev_hssi_avmm_interface #(
parameter num_ch0_atoms = 0,
parameter num_ch1_atoms = 0,
parameter num_ch2_atoms = 0
) (
//input and output port declaration
input wire avmmrstn,
input wire avmmclk,
input wire avmmwrite,
input wire ... | 7.428145 |
module cyclonev_hssi_pma_hi_pmaif #(
parameter lpm_type = "cyclonev_hssi_pma_hi_pmaif",
parameter tx_pma_direction_sel = "pcs" // valid values pcs|core
) (
input [79:0] datainfromcore,
input [79:0] datainfrompcs,
output [79:0] dataouttopma
// ... avmm and block select ports go here ...
);
... | 7.428145 |
module cyclonev_hssi_pma_hi_xcvrif #(
parameter lpm_type = "cyclonev_hssi_pma_hi_xcvrif",
parameter rx_pma_direction_sel = "pcs" // valid values pcs|core
) (
input [79:0] datainfrompma,
input [79:0] datainfrompcs,
output [79:0] dataouttopld
// ... avmm and block select ports go here ...
);
... | 7.428145 |
module arriav_hssi_pma_aux #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter cal_clk_sel = "pm_aux_iqclk_cal_clk_sel_cal_clk", //Valid values: pm_aux_iqclk_cal_clk_s... | 7.353541 |
module arriav_hssi_pma_rx_buf #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter cdrclk_to_cgb = "cdrclk_2cgb_dis", //Valid values: cdrclk_2cgb_dis|cdrclk_2cgb_en
... | 7.353541 |
module arriav_hssi_pma_rx_deser #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter auto_negotiation = "false", //Valid values: false|true
parameter channel_numbe... | 7.353541 |
module arriav_hssi_pma_tx_ser #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter auto_negotiation = "false", //Valid values: false|true
parameter channel_number ... | 7.353541 |
module arriav_hssi_rx_pcs_pma_interface #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter selectpcs = "eight_g_pcs", //Valid values: eight_g_pcs|default
paramet... | 6.742703 |
module arriav_hssi_tx_pcs_pma_interface #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter selectpcs = "eight_g_pcs", //Valid values: eight_g_pcs|default
paramet... | 9.240384 |
module arriav_hssi_tx_pld_pcs_interface #(
// parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter is_8g_0ppm = "false", //Valid values: false|true
parameter pld_side_da... | 9.240384 |
module arriav_hssi_refclk_divider #(
parameter lpm_type = "arriav_hssi_refclk_divider",
parameter divide_by = 1,
parameter enabled = "true",
parameter refclk_coupling_termination = "normal_100_ohm_termination"
) (
input [0:0] refclkin,
ou... | 6.742703 |
module arriav_hssi_pma_hi_pmaif #(
parameter lpm_type = "arriav_hssi_pma_hi_pmaif",
parameter tx_pma_direction_sel = "pcs" // valid values pcs|core
) (
input [79:0] datainfromcore,
input [79:0] datainfrompcs,
output [79:0] dataouttopma
// ... avmm and block select ports go here ...
);
cy... | 7.353541 |
module arriav_hssi_pma_hi_xcvrif #(
parameter lpm_type = "arriav_hssi_pma_hi_xcvrif",
parameter rx_pma_direction_sel = "pcs" // valid values pcs|core
) (
input [79:0] datainfrompma,
input [79:0] datainfrompcs,
output [79:0] dataouttopld
// ... avmm and block select ports go here ...
);
c... | 7.353541 |
module cyclonev_io_obuf (
i,
o,
obar,
oe,
dynamicterminationcontrol,
parallelterminationcontrol,
seriesterminationcontrol,
devoe
);
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter lpm_type = "cyclonev_io_obuf";
input i;
output o;
output obar;
... | 7.364407 |
module cyclonev_ram_2kx32_dp_bs (
address_a,
address_b,
byteena_a,
byteena_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [10:0] address_a;
input [10:0] address_b;
input [3:0] byteena_a;
input [3:0] byteena_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;... | 6.906289 |
module cyclonev_ram_2kx32_dp_bs (
address_a,
address_b,
byteena_a,
byteena_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [10:0] address_a;
input [10:0] address_b;
input [3:0] byteena_a;
input [3:0] byteena_b;
input clock;
input [31:0] data_a;
inpu... | 6.906289 |
module cyclone_mux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf (A_in, A);
buf (B_in, B);
buf (S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ?... | 6.677752 |
module cyclone_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.440157 |
module cyclone_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.385093 |
module cyclone_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 6.926523 |
module cyclone_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.594761 |
module(s):
// 1. cyclone_asynch_lcell
// 2. cyclone_lcell_register
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_lcell (
clk,
dataa,
datab,
... | 8.08873 |
module cyclone_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter start_delay = 1;
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0, t_access = 0... | 7.115148 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_ram_register (
d,
clk,
aclr,
devclrn,
... | 7.458522 |
module cyclone_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user
);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
o... | 6.663129 |
module cyclone_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 6.869389 |
module cyclone_PLL_top (
clk,
rst_n,
led0,
led1
);
input clk; //25MHz
input rst_n; //low reset signal
output led0, led1;
wire clk_100m; //ʱӵ4Ƶ,100MHz
wire clk_25m; //ʱӵ1Ƶ,25MHz
wire locked; //PLLЧ־λ,Ч
//PLLģ
//һϵͳʱ2/5Ƶ90ȵʱ
PLL_ctrl PLL_ctrl_inst (
.areset(!rst_n), //P... | 6.855153 |
module cyc_shift (
shift,
vtc,
ctv,
c,
v
);
parameter data_w = 8;
parameter ext_w = 3;
parameter mtx_w = 8;
parameter D = 5;
localparam temp_w = data_w + ext_w;
input [mtx_w-1:0] shift;
input [data_w*D-1:0] ctv;
input [temp_w*D-1:0] vtc;
output [data_w*D-1:0] v;
output [temp_w*D... | 7.780546 |
module CylnII_DoubleClick_Btn_LED (
input wire clk,
input wire rstn,
input wire btn,
output wire [2:0] led
);
parameter [16:0] DELAY = 16'd400;
reg clk_r;
reg [15:0] clk_count1;
wire clk_internal;
wire clk_10k;
always @(posedge clk, negedge rstn) begin
if (!rstn) clk_r <= 0;
els... | 7.877465 |
module Cymometer (
Clk,
Rst_n,
Gate_1s,
Gate_Test_o,
Xsig,
Update_Flag,
Freq_Result,
f_result_fp,
f_result_int,
ndege_Gate_sync
);
input Clk;
input Rst_n;
input Gate_1s; //1秒钟标准闸门信号，为了精准，可从外部输入
output Gate_Test_o; //内部1秒钟闸门信号输出，方便临时测试，可在IO上直接将其和Gate_1s接到一起
input Xsig;... | 7.263683 |
module cymometer_direct (
input clk,
input rst_n,
input clk_fx, //ź
output reg [31:0] fre //źƵ
);
parameter TIME_SYS = 10; //ϵͳʱڣ10ns--Ƶ=100MHz
parameter TIME_GATE = 50_000_000; //500msբõʱ䣬λns
localparam N = TIME_GATE / TIME_SYS; //բҪĸ
reg gate ; ... | 7.233078 |
module Cymometer_tb;
reg Clk;
reg Rst_n;
reg Gate_1s; //1秒钟标准闸门信号，为了精准，可从外部输入
wire Gate_Test_o; //内部1秒钟闸门信号输出，方便临时测试，可在IO上直接将其和Gate_1s接到一起
reg Xsig; //外部待测试信号输入，推荐接到全局时钟管脚
wire Update_Flag; //测量结果更新标志，每当该信号产生一个高脉冲，表示测量结果更新了
wire [31:0] Freq_Result; //测量结果
wire [31:0] f_result_fp;
wire [31:0] f_res... | 8.519563 |
module Cymometer_top (
Clk,
Rst_n,
Xsig,
SH_CP,
ST_CP,
cnt,
DS
);
input Clk;
input Rst_n;
input Xsig;
output SH_CP;
output ST_CP;
output DS;
output reg [27:0] cnt;
wire Gate_1s;
wire [31:0] disp_data;
wire [31:0] Freq_Result;
bin_to_BCD bin_to_BCD (
.bin(Freq_R... | 7.117209 |
module FFstd (
output Q,
input C,
input D
);
reg FF;
always @(posedge C) FF <= D;
assign Q = FF;
endmodule
| 6.808315 |
module FFrst (
output Q,
input C,
input D,
input R
);
reg FF;
always @(posedge C) FF <= R ? 0 : D;
assign Q = FF;
endmodule
| 7.648198 |
module FFce (
output Q,
input C,
input D,
input CE
);
reg FF;
always @(posedge C) FF <= CE ? D : FF;
assign Q = FF;
endmodule
| 7.006071 |
module FFrst_s (
output Q,
input C,
input D,
input R,
input INT,
input RI
);
reg FF, FFsave;
always @(posedge C) begin
FF <= R ? 0 : RI ? FFsave : D;
FFsave <= R ? 0 : INT ? D : FFsave;
end
assign Q = FF;
endmodule
| 7.758717 |
module FFstd_s (
output Q,
input C,
input D,
input INT,
input RI
);
reg FF, FFsave;
always @(posedge C) begin
FF <= RI ? FFsave : D;
FFsave <= INT ? D : FFsave;
end
assign Q = FF;
endmodule
| 7.327234 |
module FFce_s (
output Q,
input C,
input D,
input CE,
input INT,
input RI
);
reg FF, FFsave;
always @(posedge C) begin
FF <= RI ? FFsave : CE ? D : FF;
FFsave <= INT ? (CE ? D : FF) : FFsave;
end
assign Q = FF;
endmodule
| 7.756903 |
module FFcerst_s (
output Q,
input C,
input D,
input CE,
input R,
input INT,
input RI
);
reg FF, FFsave;
always @(posedge C) begin
FF <= R ? 0 : RI ? FFsave : CE ? D : FF;
FFsave <= R ? 0 : INT ? (CE ? D : FF) : FFsave;
end
assign Q = FF;
endmodule
| 7.170531 |
module FFrst_sz (
output Q,
input C,
input D,
input R,
input INT,
input RI
);
reg FF, FFsave;
always @(posedge C) begin
FF <= R ? 0 : RI ? FFsave : INT ? 0 : D;
FFsave <= R ? 0 : INT ? D : FFsave;
end
assign Q = FF;
endmodule
| 7.510638 |
module FFrst_sz2 (
output Q,
input C,
input D,
input R,
input INT,
input RI
);
reg FF, FFsave;
always @(posedge C) begin
FF <= R ? 0 : RI ? FFsave : INT ? 0 : D;
FFsave <= R ? 0 : INT ? D : FFsave;
end
assign Q = RI ? FFsave : FF;
endmodule
| 7.287348 |
module rom_style (
clk,
en,
addrA,
dout
);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 16;
input clk;
input en;
input [ADDR_WIDTH-1:0] addrA;
output reg [DATA_WIDTH-1:0] dout;
(* rom_style = "block" *)
reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];
initial $readmemh("pmem.bin", r... | 7.21978 |
module czreg (
CLK,
xREGRA_P,
xREGWA_P,
xREGWE_P,
xREGDI_P,
xREGDO_P
);
input CLK;
input [`SPM_WIDTH-1:0] xREGRA_P;
input [`SPM_WIDTH-1:0] xREGWA_P;
input xREGWE_P;
input [7:0] xREGDI_P;
output [7:0] xREGDO_P;
reg [7:0] DO;
`ifdef USE_XILINX_RAM_STYLE
(* ram_style = "distribut... | 7.231581 |
module c_add_nto1 (
data_in,
data_out
);
`include "c_functions.v"
// width of each input
parameter width = 1;
// number of inputs
parameter num_ports = 2;
// result width
localparam out_width = clogb(num_ports * (1 << width - 1) + 1);
// vector of inputs
input [0:width*num_ports-1] data_i... | 8.48848 |
module c_align (
data_in,
dest_in,
data_out
);
// width of input data
parameter in_width = 32;
// width of destination vector
parameter out_width = 32;
// offset at which to place input data within destination vector
// (portions of the input data that end up to the left or right of the
// ... | 8.402259 |
module c_arbiter (
clk,
reset,
active,
req_pr,
gnt_pr,
gnt,
update
);
`include "c_functions.v"
`include "c_constants.v"
// number of input ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 1;
// number fo bits required to select a port
... | 7.047447 |
module c_binary_op (
data_in,
data_out
);
`include "c_constants.v"
// number of inputs
parameter num_ports = 2;
// width of each input
parameter width = 1;
// select operator
parameter op = `BINARY_OP_XOR;
// vector of inputs
input [0:width*num_ports-1] data_in;
// result
output [0:w... | 8.493257 |
module
//==============================================================================
module c_clkgate
(clk, active, clk_gated);
input clk;
input active;
output clk_gated;
wire clk_gated;
reg active_q;
always @(clk, active)
begin
if(clk == 0)
active_q <= active;
... | 7.574158 |
module CNTS4x14 (
CNSCLK,
WE,
WA,
stkin,
RA,
TopCNT
);
output [13:0] TopCNT;
input [13:0] stkin;
input [1:0] RA, WA;
input CNSCLK, WE;
reg [13:0] CNTcell[3:0];
wire [13:0] TopCNT;
always @(posedge CNSCLK) if (WE) CNTcell[WA] <= #1 stkin[13:0];
assign TopCNT[13:0] = CNTc... | 7.089403 |
module expects a clock of 25 MHz.
// Data_Ready will go low at the same time as read is asserted.
// After a read, Data_Ready will go high again after the next Latch.
// Read should not be asserted when Data_Ready is low.
//
// The 8 button presses are transferred via... | 6.89613 |
module C_Counter (
input clk,
output [7:0] Counter_Address,
output WE,
output [3 : 0] MSB
);
wire [3:0] pre1, pre2;
reg [9 : 0] Counter = 0;
always @(posedge clk) begin
Counter <= Counter + 1;
if (Counter == 1023) begin
Counter <= 1023;
end
end
assign WE = (Counter < 256 ||... | 7.517481 |
module c_counter_binary_0 (
CLK,
CE,
SCLR,
THRESH0,
Q
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF q_intf:thresh0_intf:l_intf:load_intf:up_intf:sinit_intf:sset_intf, ASSOCIATED_RESET SCLR, ASSOCIATED... | 6.898444 |
module c_counter_binary_0_c_counter_binary_v12_0_12 (
CLK,
CE,
SCLR,
SSET,
SINIT,
UP,
LOAD,
L,
THRESH0,
Q
);
input CLK;
input CE;
input SCLR;
input SSET;
input SINIT;
input UP;
input LOAD;
input [3:0] L;
output THRESH0;
output [3:0] Q;
wire CE;
wire CLK;
... | 6.898444 |
module c_counter_binary_1 (
CLK,
CE,
SCLR,
THRESH0,
Q
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF q_intf:thresh0_intf:l_intf:load_intf:up_intf:sinit_intf:sset_intf, ASSOCIATED_RESET SCLR, ASSOCIATED... | 6.898444 |
module c_counter_binary_1_c_counter_binary_v12_0_12 (
CLK,
CE,
SCLR,
SSET,
SINIT,
UP,
LOAD,
L,
THRESH0,
Q
);
input CLK;
input CE;
input SCLR;
input SSET;
input SINIT;
input UP;
input LOAD;
input [3:0] L;
output THRESH0;
output [3:0] Q;
wire CE;
wire CLK;
... | 6.898444 |
module c_counter_binary_2 (
CLK,
CE,
SCLR,
THRESH0,
Q
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF q_intf:thresh0_intf:l_intf:load_intf:up_intf:sinit_intf:sset_intf, ASSOCIATED_RESET SCLR, ASSOCIATED... | 6.898444 |
module c_counter_binary_2_c_counter_binary_v12_0_12 (
CLK,
CE,
SCLR,
SSET,
SINIT,
UP,
LOAD,
L,
THRESH0,
Q
);
input CLK;
input CE;
input SCLR;
input SSET;
input SINIT;
input UP;
input LOAD;
input [3:0] L;
output THRESH0;
output [3:0] Q;
wire CE;
wire CLK;
... | 6.898444 |
module c_counter_binary_3 (
CLK,
CE,
SCLR,
THRESH0,
Q
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF q_intf:thresh0_intf:l_intf:load_intf:up_intf:sinit_intf:sset_intf, ASSOCIATED_RESET SCLR, ASSOCIATED... | 6.898444 |
module c_counter_binary_3_c_counter_binary_v12_0_12 (
CLK,
CE,
SCLR,
SSET,
SINIT,
UP,
LOAD,
L,
THRESH0,
Q
);
input CLK;
input CE;
input SCLR;
input SSET;
input SINIT;
input UP;
input LOAD;
input [3:0] L;
output THRESH0;
output [3:0] Q;
wire CE;
wire CLK;
... | 6.898444 |
module
//==============================================================================
module c_crossbar
(ctrl_ip_op, data_in_ip, data_out_op);
`include "c_constants.v"
// number of input/output ports
parameter num_in_ports = 5;
parameter num_out_ports = 5;
// width per port
parameter wid... | 7.574158 |
module c_decr (
data_in,
data_out
);
`include "c_functions.v"
parameter width = 3;
parameter [0:width-1] min_value = 0;
parameter [0:width-1] max_value = (1 << width) - 1;
localparam num_values = max_value - min_value + 1;
localparam swidth = suffix_length(min_value, max_value);
localparam c... | 9.243064 |
module c_dff (
clk,
reset,
active,
d,
q
);
`include "c_constants.v"
// width of register
parameter width = 32;
// offset (left index) of register
parameter offset = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
parameter [offset:(offset+width)-1] reset_value = {width{1'b0}};
inp... | 9.227826 |
module c_diag_op (
data_in,
data_out
);
// input width
parameter width = 1;
// select operator
parameter op = `BINARY_OP_XOR;
// vector of inputs
input [0:width*width-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar diag;
for (diag ... | 7.476226 |
module c_d_ctrl (
input clk,
input rst,
input inj_err,
input [7:0] ch_out,
input [7:0] ch_out_vld,
input [7:0] ch_out_done,
input serial_busy,
output err_en,
output reg [2:0] err_ctrl,
output c_en,
output [7:0] dump_en,
output serial_en,
output reg [7:0] serial_tx,
... | 6.958351 |
module
//==============================================================================
module c_err_rpt
(clk, reset, active, errors_in, errors_out);
`include "c_constants.v"
// number of error inputs
parameter num_errors = 1;
// select mode of operation
parameter capture_mode = `ERROR_CAPTUR... | 7.574158 |
module c_fbmult (
feedback,
complete,
data_in,
data_out
);
`include "c_constants.v"
// width of register (must be greater than one)
parameter width = 32;
// how many iterations to perform at once
parameter iterations = 1;
// feedback polynomial(s)
input [0:width-1] feedback;
// incl... | 7.211171 |
module c_gate_bits (
select,
data_in,
data_out
);
`include "c_constants.v"
// number of input ports
parameter num_ports = 1;
// width of each port
parameter width = 32;
// operator
parameter op = `BINARY_OP_AND;
// control signal to select active port
input [0:num_ports-1] select;
... | 8.315935 |
module for extracting a set of bits from an input word (result is
// concatenation of these bits)
//==============================================================================
module c_gather
(data_in, data_out);
// width of input word
parameter in_width = 32;
function integer pop_count(input [0... | 7.012113 |
module c_incr (
data_in,
data_out
);
`include "c_functions.v"
parameter width = 3;
parameter [0:width-1] min_value = 0;
parameter [0:width-1] max_value = (1 << width) - 1;
localparam num_values = max_value - min_value + 1;
localparam swidth = suffix_length(min_value, max_value);
localparam c... | 9.202216 |
module c_interleave (
data_in,
data_out
);
// input data width
parameter width = 8;
// number of blocks in input data
parameter num_blocks = 2;
// width of each block
localparam step = width / num_blocks;
// vector of input data
input [0:width-1] data_in;
// vector of output data
output... | 7.537003 |
module c_lfsr (
clk,
reset,
active,
load,
run,
feedback,
complete,
d,
q
);
`include "c_constants.v"
// width of register (must be greater than one)
parameter width = 32;
// offset (left index) of register
parameter offset = 0;
// initial state
parameter [offset:(off... | 8.924147 |
module c_lod (
data_in,
data_out
);
`include "c_functions.v"
// number of input ports
parameter width = 32;
// number of stages
localparam depth = clogb(width);
// vector of requests
input [0:width-1] data_in;
// vector of grants
output [0:width-1] data_out;
wire [0:width-1] data_out;
... | 8.335914 |
module LPstk (/* in */ T_RST, DSPCLK, LPin, PushLP_EN, PopLP_EN,
LPS_CKenb,
`ifdef FD_DFT
SCAN_TEST,
`endif
TopLP, LP_full, LP_empty, LP_has1);
input [21:0] LPin;
input T_RST, DSPCLK, PushLP_EN, PopLP_EN, LPS_CKenb;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [21:0] TopLP;
output LP_empty,
LP_full,
LP_has1;
reg [2... | 6.627382 |
module LPS4x22 (
LPSCLK,
WE,
WA,
stkin,
RA,
TopLP
);
output [21:0] TopLP;
input [21:0] stkin;
input [1:0] RA, WA;
input LPSCLK, WE;
reg [21:0] LPcell[3:0];
wire [21:0] TopLP;
always @(posedge LPSCLK) if (WE) LPcell[WA] <= #1 stkin[21:0];
assign TopLP[21:0] = LPcell[RA];... | 7.152503 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
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