code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module shift_register_group_18_16_18 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
inpu... | 6.854847 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_reg... | 6.854847 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge c... | 7.738783 |
module shift_register_group_18_16_14 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
inpu... | 6.854847 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_group_18_16_6 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module shift_register_group_18_16_10 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
inpu... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_reg... | 6.854847 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge c... | 7.738783 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_reg... | 6.854847 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge c... | 7.738783 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module weight_buffer_18_9_1_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [10:0] index
);
... | 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module weight_buffer_18_9_1_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
input [10:0] index
);
... | 6.6283 |
module counter_31_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 31) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.103667 |
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module shift_register_group_18_16_3 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module weight_buffer_18_9_2_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module weight_buffer_18_9_2_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module counter_31_2 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 2) <= 31) begin
count <= count + 2;
end else begin
count <= 14'd0;
end
... | 7.08126 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module shift_register_group_18_16_3 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module weight_buffer_18_9_3_64_2048_Wym_imag_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 288;
parameter ADDR_WIDTH = 6;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge c... | 8.023817 |
module weight_buffer_18_9_3_64_2048_Wym_real_half_0 (
input clk,
output [17:0] q_0_0,
output [17:0] q_0_1,
output [17:0] q_0_2,
output [17:0] q_0_3,
output [17:0] q_0_4,
output [17:0] q_0_5,
output [17:0] q_0_6,
output [17:0] q_0_7,
output [17:0] q_0_8,
output [17:0] q_1_0,
... | 6.6283 |
module counter_31_3 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 3) <= 31) begin
count <= count + 3;
end else begin
count <= 14'd0;
end
... | 7.299146 |
module counter_63_1 (
input clk,
input reset,
input ena,
output reg [13:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else if (ena) begin
if ((count + 1) <= 63) begin
count <= count + 1;
end else begin
count <= 14'd0;
end
... | 7.034248 |
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module shift_register_group_18_16_3 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module c_mag_estimate #(
parameter DATA_LEN = 32,
parameter ALPHA = 0.9,
parameter BETA = 0.4
) (
input clk,
input [DATA_LEN-1:0] dataI,
input [DATA_LEN-1:0] dataQ,
output [DATA_LEN-1:0] dataMag
);
reg [DATA_LEN-1:0] dataMag_r;
reg [DATA_LEN-1:0] dataI_abs;
reg [DATA_LEN-1:0] dataQ_ab... | 7.134495 |
module c_matrix_arbiter (
clk,
reset,
active,
req_pr,
gnt_pr,
gnt,
update
);
`include "c_constants.v"
// number of inputs ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 1;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input... | 7.017317 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module dsp_signed_mult_18x18_unit_18_18_1 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [36:0] resulta,
output [36:0] resultb
);
reg [17:0] reg_ax, reg_ay, reg_bx, reg_by;
re... | 6.834084 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module addfxp_18_1 (
input [17:0] a,
input [17:0] b,
input clk,
output [17:0] q
);
reg [17:0] res_0;
assign q = res_0;
always @(posedge clk) begin
res_0 <= a + b;
end
endmodule
| 6.553508 |
module dsp_signed_mult_18x18_unit_18_36_0 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [17:0] ay,
input [17:0] bx,
input [17:0] by,
output o_valid,
output [35:0] resulta,
output [35:0] resultb
);
reg [35:0] reg_resa, reg_resb;
always @(posed... | 6.834084 |
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