code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sign_extend (
out,
in
);
// Declare variables to be connected to inputs and outputs
input [3:0] in; // 4-bit input
output reg [15:0] out; // 12-bit output
always @(in) begin
if (in[3] == 1)
out <= {
1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, in
... | 7.581479 |
module alu (
x,
y,
z,
c_in,
c_out,
lt,
eq,
gt,
overflow,
ALUOp
);
// Declare variables to be connected to inputs and outputs
input [15:0] x;
input [15:0] y;
output reg [15:0] z;
input c_in;
output reg c_out = 0;
output reg lt, eq, gt;
output reg overflow;
inpu... | 7.914753 |
module shift_16bits (
out,
in
);
// Declare variables to be connected to inputs and outputs
input [15:0] in;
output reg [15:0] out;
always @(in) begin
out <= {in[14:0], 1'b0}; // left shift
end
endmodule
| 8.416586 |
module add (
out,
in,
value
);
// Declare variables to be connected to inputs and outputs
input [15:0] in; // previous pc
input [15:0] value;
output reg [15:0] out; // next pc
always @(in) out <= in + value; // add value to the pc
endmodule
| 6.843391 |
module shift_12bit (
out,
in
);
input [11:0] in;
output reg [12:0] out;
always @(in) begin
out <= {in, 1'b0}; // left shift to 13 bit
end
endmodule
| 8.481994 |
module for behavioral model for KRUM controller
module controller (RegDest,RegWrite,ALUSrc,ALUOp,MemWrite,MemRead,MemToReg,Branch,Jump,Instruction,clock);
// Declare variables to be connect to outputs
output reg RegDest,RegWrite;
output reg ALUSrc;
output reg [2:0] ALUOp;
output reg MemWrite,MemRead,MemToReg;
output r... | 7.390191 |
module datapath_ctl (
output ALU_B_imm,
immExt_sign,
GPR_write_PC,
GPR_write_MEM,
overflow_aware,
output [1:0] PC_ctl_func,
MEM_data_len,
output MEM_load_signExt,
output reg [3:0] ALU_func,
input [31:0] ins,
input [7:0] ins_flags
);
wire typeR_ALU, typeR_jr, typeI_ALU, typ... | 7.380281 |
module Datapath_Decryption (
output [127:0] Dout,
output count_gt_0,
count_eq_9,
input [127:0] encrypted_text_in,
key_in,
input isRound10,
isRound9,
init,
dec_count,
en_round_out,
en_reg_inv_row_out,
en_reg_inv_sub_out,
en_reg_inv_col_out,
en_Dout,
clock,
... | 6.855164 |
module datapath_fft_controller (
input clock,
input sclr_counter,
input en_counter,
output tc_counter,
output [9:0] addr
);
counter_mod_10 counter_fft (
.clk(clock),
.ce(en_counter),
.sclr(sclr_counter),
.q(addr)
); // Bus [9 : 0]
assign t... | 6.837218 |
module for data packets entering and leaving
// the user logic in an RFNoC block. This module keeps track
// of the packet count for software to detect activity and
// provides a mechanism to flush packets from software. Useful
// to prevent slow-moving or misbehaving noc blocks from clogging
// up the infra... | 7.325883 |
module mdr_mux (
out8_to_mdr,
inout16_mdr,
dr_out,
from_store_mux,
to_dr_in,
to_ir,
ctrl
);
output reg [7:0] out8_to_mdr;
inout reg [15:0] inout16_mdr;
input wire [1:0] ctrl;
input wire [7:0] from_store_mux;
input wire [15:0] dr_out;
output reg [15:0] to_dr_in;
output reg [15... | 6.644162 |
module mdr8_16 (
mem8,
mem16,
inout16_mdr,
in8_mdr,
load_mdr
);
output reg [7:0] mem8;
inout reg [15:0] mem16;
inout reg [15:0] inout16_mdr;
input wire [7:0] in8_mdr;
input wire load_mdr;
always @(posedge load_mdr) begin
mem8 <= in8_mdr;
mem16 <= inout16_mdr;
inout16_mdr <= ... | 7.350951 |
module sext8 (
in,
out,
sext8_ctrl
);
input wire [15:0] in;
input wire sext8_ctrl;
output reg [15:0] out;
always @(*) begin
out[7:0] <= in[7:0];
out[8] <= (sext8_ctrl == 1) ? in[7] : in[8];
out[9] <= (sext8_ctrl == 1) ? in[7] : in[9];
out[10] <= (sext8_ctrl == 1) ? in[7] : in[1... | 6.86116 |
module sext5 (
in,
out
);
input wire [4:0] in;
output wire [15:0] out;
assign out = {
in[4], in[4], in[4], in[4], in[4], in[4], in[4], in[4], in[4], in[4], in[4], in[4:0]
};
endmodule
| 7.3888 |
module sext6 (
in,
out
);
input wire [5:0] in;
output wire [15:0] out;
assign out = {in[5], in[5], in[5], in[5], in[5], in[5], in[5], in[5], in[5], in[5], in[5:0]};
endmodule
| 7.073939 |
module sext9 (
in,
out
);
input wire [8:0] in;
output wire [15:0] out;
assign out = {in[8], in[8], in[8], in[8], in[8], in[8], in[8], in[8:0]};
endmodule
| 7.028358 |
module sext11 (
in,
out
);
input wire [10:0] in;
output wire [15:0] out;
assign out = {in[10], in[10], in[10], in[10], in[10], in[10:0]};
endmodule
| 7.295522 |
module sx_mux (
in6,
in9,
in11,
sext_mux,
to_lshft
);
input wire [15:0] in6;
input wire [15:0] in9;
input wire [15:0] in11;
input wire [1:0] sext_mux;
output wire [15:0] to_lshft;
assign to_lshft = (sext_mux == 2'b00) ? 16'd0 :
(sext_mux == 2'b01) ? in6 :
(sext_mux == 2'b10... | 6.725465 |
module lshft (
in,
out
);
input wire [15:0] in;
output wire [15:0] out;
assign out = 2 * in;
endmodule
| 7.382292 |
module Datapath (
input reset_n,
input clk,
input [`opcode_loc_r - 1 : 0] opinstruction,
input [`WORD_SIZE - 1 : 0] MemData,
input [`WORD_SIZE - 1 : 0] inst_seq_next_addr,
input [`WORD_SIZE - 1 : 0] inst_addr,
input [3 : 0] ALU_OP,
input RegDst,
input RegWrite,
input [1:0] RegWri... | 7.439732 |
module Datapath_Multiplier (
//define inputs
input _clk,
_clear,
_loadA,
_loadB,
_countDown,
_loadHoldA,
_loadProduct,
input [7:0] _dataInA,
_dataInB,
//define outputs
output _countZero,
output [15:0] _product
);
//define wires
wire [15:0] _loadRegisterAOut, _p... | 6.673712 |
module ALU_32bit (
output reg [31:0] Out,
output reg N,
Z,
C_Out,
V,
input [31:0] In_A,
In_B,
input [4:0] OP,
input C_In
);
always @ (In_A, In_B, OP) //Cada vez que cambie In_A, In_B o OP
begin
case (OP)
5'b00000: Out = In_A & In_B;
5'b00001: Out = In_A ^ In_B... | 7.299764 |
module ConditionTester (
output reg cond,
input [3:0] cond_code,
input N,
Z,
C,
V
);
always @(cond_code, N, Z, C, V) begin
cond = 0;
case (cond_code)
4'b0000: if (Z == 1) cond = 1; // EQ Equal
4'b0001: if (Z == 0) cond = 1; // NE Not Equal
4'b0010: if (C == 1) cond ... | 7.053074 |
module Flag_Register (
output reg N_out,
Z_out,
C_out,
V_out,
input N_in,
Z_in,
C_in,
V_in,
FR_Ld,
Clk
);
always @(posedge Clk) begin
if (FR_Ld == 1'b1) begin
N_out = N_in;
Z_out = Z_in;
C_out = C_in;
V_out = V_in;
end
end
endmodule
| 6.60613 |
module MAR (
output reg [31:0] Out_MAR,
input [31:0] In_MAR,
input MAR_Ld,
Clk
);
always @(posedge Clk) begin
if (MAR_Ld == 1'b1) begin
Out_MAR = In_MAR;
end
end
endmodule
| 6.650005 |
module MDR (
output reg [31:0] Out_MDR,
input [31:0] In_MDR,
input MDR_Ld,
Clk
);
always @(posedge Clk) begin
if (MDR_Ld == 1'b1) begin
Out_MDR = In_MDR;
end
end
endmodule
| 7.032216 |
module Mux_A (
output reg [3:0] Out_A,
input [3:0] In_A0,
In_A1,
In_A2,
In_A3,
input [1:0] S_A
);
always @(S_A) begin
case (S_A)
2'b00: Out_A = In_A0;
2'b01: Out_A = In_A1;
2'b10: Out_A = In_A2;
2'b11: Out_A = In_A3;
endcase
end
endmodule
| 6.563285 |
module Mux_B (
output reg [31:0] Out_B,
input [31:0] In_B0,
In_B1,
In_B2,
In_B3,
input [1:0] S_B
);
always @(S_B) begin
case (S_B)
2'b00: Out_B = In_B0;
2'b01: Out_B = In_B1;
2'b10: Out_B = In_B2;
2'b11: Out_B = In_B3;
endcase
end
endmodule
| 6.567214 |
module Mux_C (
output reg [3:0] Out_C,
input [3:0] IReg12_15,
Ones,
In_C3,
IReg16_19,
input [1:0] S_C
);
always @(S_C) begin
case (S_C)
2'b00: Out_C = IReg12_15;
2'b01: Out_C = Ones;
2'b10: Out_C = IReg16_19;
2'b11: Out_C = In_C3;
endcase
end
endmodule
| 7.196164 |
module Mux_D (
output reg [4:0] Out_D,
input [4:0] In_D0,
input [3:0] In_D1,
input In_D2,
S_D
);
always @(S_D) begin
case (S_D)
1'b0: Out_D = In_D0;
1'b1: Out_D = {In_D2, In_D1};
endcase
end
endmodule
| 7.023732 |
module Mux_E (
output reg [31:0] Out_E,
input [31:0] In_E0,
In_E1,
input S_E
);
always @(S_E) begin
case (S_E)
1'b0: Out_E = In_E0;
1'b1: Out_E = In_E1;
endcase
end
endmodule
| 7.741986 |
module ram512x8 (
output reg MOC,
output reg [31:0] DataOut,
input MOV,
ReadWrite,
input [31:0] Address,
input [31:0] DataIn,
input [1:0] datatype
); //se incluyo datatype para determinar el tamano del dato
//00: byte(8 bits) 01: half-word(16 bits) 10: word(32 bits) 11: doubleword ... | 7.826383 |
module Register (
output reg [31:0] Q,
input [31:0] D,
input Ld,
Clk
);
always @(posedge Clk, posedge Ld) // Edge trigger
if (Ld == 1 && Clk == 1) begin // Two-gate Register
Q = D;
// $display("New data at register:\nClk = %d Ld = %b D = %b Q = %b t=%d", Clk, Ld,... | 7.117303 |
module Bin_Decoder_4x16 (
output reg E15,
E14,
E13,
E12,
E11,
E10,
E9,
E8,
E7,
E6,
E5,
E4,
E3,
E2,
E1,
E0,
input [3:0] C,
input Ld
);
always @(posedge Ld, C) begin
E15 = 0;
E14 = 0;
E13 = 0;
E12 = 0;
E11 = 0;
E10 = 0;
... | 6.611992 |
module Mux_16x1 (
output reg [31:0] Y,
input [3:0] S,
input [31:0] R0,
R1,
R2,
R3,
R4,
R5,
R6,
R7,
R8,
R9,
R10,
R11,
R12,
R13,
R14,
R15
);
always @(Y, S, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15) begin
case (S)
... | 7.562822 |
module RegisterFile (
output [31:0] PA,
PB,
ProgamCounter,
input [31:0] PC,
input [3:0] C,
input [3:0] A,
input [3:0] B,
input Ld,
Clk
);
wire [31:0] R0M, R1M, R2M, R3M, R4M, R5M,
R6M, R7M, R8M, R9M, R10M,
R11M, R12M, R13M, R14M, R15M; ... | 8.108491 |
module NextStateAddressSelector (
output reg [1:0] M,
input [2:0] N,
input Sts
);
always @(N, Sts) begin
case (N)
3'b000: M = 2'b00; // Encoder
3'b001: if (Sts == 0) M = 2'b01; // 1
else M = 2'b10; // Control Register
3'b010: M = 2'b10; // Control Register
3'b011: M = 2'b1... | 7.265287 |
module Adder (
output reg [5:0] Out,
input [5:0] In
);
always @(In) begin
Out = In + 6'b000001;
end
endmodule
| 6.893856 |
module IncrementRegister (
output reg [5:0] Out,
input [5:0] In,
input Clk
);
always @(posedge Clk) begin
Out = In;
end
endmodule
| 6.680637 |
module Inverter (
output reg InvOut,
input In,
VarInv
);
always @(In, VarInv)
case (VarInv)
1'b0: if (In == 0) InvOut = 0;
else InvOut = 1;
1'b1: if (In == 1) InvOut = 0;
else InvOut = 1;
endcase
endmodule
| 7.198219 |
module InverterMux (
output reg InvIn,
input MOC,
Cond,
unsignee,
double,
load,
EntrySix,
Entryseven,
Entryeight,
input [2:0] S
);
always @(S, MOC, Cond) begin
case (S)
3'b000: InvIn = MOC;
3'b001: InvIn = Cond;
3'b010: InvIn = unsignee;
3'b011: InvI... | 7.278959 |
module ControlRegister (
output reg [5:0] state,
output reg FR,
RF,
IR,
MAR,
MDR,
ReadWrite,
MOV,
MD,
ME,
Inv,
output reg [1:0] MA,
output reg [1:0] MB,
output reg [1:0] MC,
output reg [4:0] OP,
output reg [5:0] CR,
output reg [2:0] N,
output reg [... | 6.822423 |
module datapath (
input clk,
reset,
input memtoregE,
memtoregM,
memtoregW,
pcsrc,
input branch,
alusrc,
regdstE,
input regwriteE,
regwriteM,
regwriteW,
jump,
input [2:0] alucontrol,
output zero,
output [31:0] pc,
input [31:0] instr,
output [31:0] a... | 6.91752 |
module Instruction_Register (
clk,
memory_data,
IRWrite,
instruc3,
instruc2,
instruc1,
instruc0
);
input clk;
input [31:0] memory_data;
input IRWrite;
output reg [5:0] instruc3;
output reg [4:0] instruc2, instruc1;
output reg [15:0] instruc0;
always @(posedge clk) begin
if... | 6.510365 |
module Registers (
clk,
reset,
RegWrite,
read_reg1,
read_reg2,
write_reg,
write_data,
read_data1,
read_data2
);
input clk, reset, RegWrite;
input [4:0] read_reg1, read_reg2, write_reg;
input [31:0] write_data;
output [31:0] read_data1, read_data2;
reg [31:0] registers[31:0... | 7.405039 |
module blockFD (
input clk, //blocks for sending inputs to next pipeline phases
input [31:0] InstrF,
input [31:0] PCPlus4F,
PCF,
input EntryFoundF,
PredictNTakenF,
TakePredictF,
Cache_Stall,
Stall,
reset,
input clear,
... | 6.836088 |
module blockDE (
input clk,
input [31:0] RD1D,
RD2D,
input [ 4:0] RsD,
RtD,
RdD,
input [ 5:0] FuncD,
input [31:0] SignImmD,
ZeroImmD,
PCBranchD,
PCPlus4D,
PCD,
input RegWriteD,
MemtoRegD,
MemWriteD,
input [ ... | 7.532292 |
module blockEM (
input clk,
input [31:0] ALUOutE,
WriteDataE,
input [ 4:0] WriteRegE,
input RegWriteE,
MemtoRegE,
MemWriteE,
MfloE,
MfhiE,
stall,
output reg [31:0] ALUOutM,
WriteDataM,
output reg [ 4:0] WriteRegM,
output reg ... | 6.516911 |
module blockMW (
input clk,
input [31:0] ReadDataM,
ALUOutM,
input [ 4:0] WriteRegM,
input RegWriteM,
MemtoRegM,
MfloM,
MfhiM,
stall,
output reg [31:0] ReadDataW,
ALUOutW,
output reg [ 4:0] WriteRegW,
output reg RegWriteW,
... | 6.640705 |
module Memory (
Address,
WriteData,
MemWrite,
MemRead,
clk,
ReadData
);
input [4:0] Address, WriteData;
input MemWrite, MemRead, clk;
output [7:0] ReadData;
reg [7:0] memory[0:31];
always @(posedge clk) begin
if (MemWrite) memory[Address] <= WriteData;
end
initial begin
$re... | 7.051739 |
module ALU (
input [2:0] ALUOperation,
input [7:0] A,
B,
output zero,
output reg [7:0] ALUResult
);
always @(ALUOperation, A, B) begin
ALUResult <= 8'd0;
case (ALUOperation)
3'b000: ALUResult <= A + B; //add
3'b001: ALUResult <= B - A; //sub
3'b010: ALUResult <= A & B... | 7.960621 |
module register8b_ld (
input clk,
rst,
ld,
input [7:0] in,
output reg [7:0] out
);
always @(posedge clk, posedge rst) begin
if (rst) out <= 8'd0;
else if (ld) out <= in;
end
endmodule
| 7.536294 |
module register8b (
input clk,
rst,
input [7:0] in,
output reg [7:0] out
);
always @(posedge clk, posedge rst) begin
if (rst) out <= 8'd0;
else out <= in;
end
endmodule
| 7.779435 |
module signExtend (
input [15:0] in,
output [31:0] out
);
assign out = in[15] ? {16'b1111111111111111, in} : {16'b0000000000000000, in};
endmodule
| 7.397526 |
module mux5b (
input s,
input [4:0] A,
B,
output [4:0] out
); //0 -> A ; 1 -> B
assign out = (s == 1'b0) ? A : B;
endmodule
| 8.21788 |
module mux8b (
input s,
input [7:0] A,
B,
output [7:0] out
); //0 -> A ; 1 -> B
assign out = (s == 1'b0) ? A : B;
endmodule
| 8.493508 |
module InstMem (
input [4:0] Address,
output [7:0] Instruction
);
reg [7:0] mem[0:31];
initial begin
$readmemb("stack_test.data", mem);
end
assign Instruction = mem[Address];
endmodule
| 6.646235 |
module PC (
input clk,
rst,
ld,
input [4:0] in,
output reg [4:0] out
);
always @(posedge rst, posedge clk) begin
if (rst) out <= 5'd0;
else if (ld) out <= in;
end
endmodule
| 7.578567 |
module datapath (
input clk,
rst,
PCSrc,
pc_write,
pc_write_con,
Z,
mem_sel,
Mem_read,
Mem_write,
IR_write,
stack_sel,
load_A,
A_sel,
B_sel,
push,
pop,
tos,
input [2:0] ALUOP,
output ALUZero,
output [2:0] opcode
);
wire [4:0] nextPC, PCA... | 6.91752 |
module DataPath_tb;
`include "../src/utils/Assert.vh"
`include "../src/Parameters.vh"
// Input stimulus
reg clk;
reg rst;
integer i;
DataPath #(
.INSTRUCTION_FILE_NAME("./test/datapath_tb2.ASM")
) DUT (
.clk(clk),
.rst(rst)
);
// Test initialization
initial begin
clk <= 0;
... | 6.593051 |
modules used in the PIC10 datapath.
*
****************************************************************************/
// These constants determine the signals on the status_bus (output from ALU)
// as well as on the status_reg_bus (output from STATUS register).
`define STATUS_C 0
`define STATUS_DC 1
`define STATUS_Z 2
... | 6.989144 |
module test_pic10_w_reg;
// These are the output signals from the Device Under Test:
wire [7:0] w_reg_bus; // Output: The output from the W register. Used as 1st ALU operand.
// These are the input signals to the Device Under Test:
reg [7:0] alu_bus; // Input: The output from the ALU. This can either be
/... | 6.796756 |
module test_pic10_alu_mux;
// These are the output signals from the Device Under Test:
wire [7:0] alu_mux_bus; // Output: This is the bus that drives the ALUs 2nd operand.
// These are the input signals to the Device Under Test:
reg [7:0] sfr_data_bus = 8'h55; // Input: Operand data from the special functio... | 10.082185 |
module test_pic10_ram_registers;
// These are the output signals from the Device Under Test:
wire [7:0] ram_data_bus; // Output: Always outputs the data in the addressed register.
// These are the input signals to the Device Under Test:
reg [7:0] alu_bus = 0; // Input: The output from the ALU. Loaded into t... | 7.665858 |
module test_pic10_register_address_mux;
// These are the output signals from the Device Under Test:
wire [4:0] reg_addr_bus; // Output: This is the currently selected register address (either
// a direct address or an indirect address selected by the Register
// Address Mux).
// These are the input signals... | 9.218152 |
module test_pic10_sfr_data_mux;
// These are the output signals from the Device Under Test:
wire [7:0] sfr_data_bus; // Output: Operand data from the special function registers 0..7.
// These are the input signals to the Device Under Test:
reg [2:0] sfr_data_mux_sel = 0; // Input: This is the currently sele... | 7.431364 |
module test_pic10_status_reg;
// These are the output signals from the Device Under Test:
wire [7:0] status_reg_bus; // Output: The current status is always driven.
wire carry_bit; // Output: The carry bit from the STATUS register.
// These are the input signals to the Device Under Test:
reg [7:0] alu_bus... | 6.586782 |
module test_pic10_fsr;
// These are the output signals from the Device Under Test:
wire [7:0] fsr_reg_bus; // Output: Contains the indirect register address in the FSR register.
// These are the input signals to the Device Under Test:
reg [7:0] alu_bus; // Input: The output from the ALU. Loaded into the FSR... | 6.841582 |
module test_pic10_pc;
// These are the output signals from the Device Under Test:
wire [8:0] pc_bus; // Output: Drives the current value in the Program Counter.
// These are the input signals to the Device Under Test:
reg [8:0] pc_mux_bus = 0; // Input: Data to be loaded into PC when 'load_pc_reg' is assert... | 8.357211 |
module test_pic10_pc_mux;
// These are the output signals from the Device Under Test:
wire [8:0] pc_mux_bus; // Output: The PC will be loaded from this bus.
// These are the input signals to the Device Under Test:
reg [8:0] stack_bus = 9'h111; // Input: Used to load stacked values into PC.
reg [7:0] alu_b... | 8.357211 |
module test_pic10_stack;
// These are the output signals from the Device Under Test:
wire [8:0] stack_bus; // Output: Current stack location data.
// These are the input signals to the Device Under Test:
reg [8:0] pc_bus = 0; // Input: Data to be loaded when asserting load_stack.
reg load_stack = 0; // I... | 6.586782 |
module datapath(instr);
input [31:0] instr;
registers registers (read_A, read_B, write_reg, write_data, reg_writercra, A, B);
mux mux1(alu_ctrl, {B, imm}, alu_B);
alu alu(A, alu_B, alu_op, alu_result);
memory memory(alu_result, write_data, read_data, mem_write, mem_read);
mux mux2(mem_to_reg,... | 7.228365 |
module datapath_with_control_unit #(
parameter d = 16
) (
input clk,
reset,
en,
output [d-1:0] cu_data,
ac_data
);
wire ar_we, ar_inc;
wire [11:0] ar_idat, ar_odat;
wire pc_we, pc_inc;
wire [7:0] pc_idat, pc_odat;
wire ir_inc;
wire [d-1:0] ir_idat, ir_odat;
wire ac_we, ac_inc;
w... | 7.279403 |
module dataprocess (
clk,
rst_n,
enable,
datain,
dataout,
dir,
feedback
);
input clk, rst_n, enable;
input [31:0] datain, feedback;
output [31:0] dataout;
output dir;
wire [31:0] dataout;
//integer buffer;
//integer max;
//integer min;
reg signed [31:0] buffer, buffer1, buf... | 6.644879 |
module dataprocess_db (
clk,
rst_n,
enable,
datain,
dataout,
dir,
feedback
);
input clk, rst_n, enable;
//input infrain; // add for dribbling
input [31:0] datain, feedback;
output [31:0] dataout;
output dir;
wire [31:0] dataout;
//integer buffer;
//integer max;
//integer mi... | 7.012466 |
module datapath (
input clk,
reset,
input memtoreg,
pcsrc,
input alusrc,
regdst,
input regwrite,
jump,
input [2:0] alucontrol,
output zero,
output [31:0] pc,
input [31:0] instr,
output [31:0] aluout,
writedata,
input [31:0] readdata
);
wire [4:0] writereg;
... | 6.91752 |
module dataram2 #(
parameter SIZE = 1024,
parameter AWIDTH = 10,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input we,
input [DWIDTH-1:0] din,
output reg [DWIDTH-1:0] dout
);
reg [DWIDTH-1:0] mem[0:SIZE-1];
always @(posedge clk) begin
if (we) mem[addr] <= di... | 8.488123 |
module dataram3 (
clk,
addr,
we,
din,
dout
);
parameter ADDR_WIDTH = 12;
parameter COL_WIDTH = 8;
parameter N_COLS = 2;
localparam DATA_WIDTH = (COL_WIDTH * N_COLS);
localparam RAM_DEPTH = 1 << ADDR_WIDTH;
input clk;
input [(ADDR_WIDTH-1):0] addr;
input [(N_COLS-1):0] we;
input [(... | 7.933841 |
module dataram_1k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
rd_mask,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [7:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write St... | 6.572446 |
module dataram_2k1way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
rd_mask,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [8:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Str... | 7.035861 |
module dataram_2k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
rd_mask,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [8:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write St... | 6.774038 |
module dataram_2k4way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
rd_mask,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [8:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Str... | 6.526277 |
module dataram_4k1way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
rd_mask,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [9:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Str... | 7.17078 |
module dataram_4k2way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
rd_mask,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [9:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write St... | 6.934539 |
module dataram_4k4way_xilinx (
clk,
line_idx,
rd_str,
wr_str,
early_ce,
rd_mask,
wr_mask,
wr_data,
rd_data,
bist_to,
bist_from
);
/* Inputs */
input clk; // Clock
input [9:0] line_idx; // Read Array Index
input rd_str; // Read Strobe
input wr_str; // Write Str... | 6.67582 |
module dataRAM
(a,
d,
clk,
we,
spo);
input [5:0]a;
input [31:0]d;
input clk;
input we;
output [31:0]spo;
wire [5:0]a;
wire clk;
wire [31:0]d;
wire [31:0]spo;
wire we;
wire [31:0]NLW_U0_dpo_UNCONNECTED;
wire [31:0]NLW_U0_qdpo_UNCONNECTED;
wire [31:0]NLW_U0_qspo_UNCONNECTED;
... | 6.975103 |
module test #(
parameter DATA_WIDTH = 32,
BUS_WIDTH = 17
) ();
reg clk;
reg memwrite;
reg [ BUS_WIDTH-1:0] adr;
reg [DATA_WIDTH-1:0] writedata;
wire [DATA_WIDTH-1:0] readdata;
// 10nsec --> 100MHz
parameter STEP = 10;
// generate clock to sequence tests
... | 7.534723 |
module dataRDSM (
clk,
Rempty,
rst_n,
Rdata,
Rinc,
data_out
);
input clk, Rempty, rst_n; //entradas al modulo, memoria vacia y reset
input [15:0] Rdata; //datos de entrada al modulo, provienen de la fifo
output reg Rinc; //salida para habilitar la lectura de memoria
output reg [15:0]... | 7.390831 |
module dataRead (
input clk190hz,
input rst,
input leftMove,
input rightMove,
input inc,
output [3:0] pos,
output [7:0] seg,
output [31:0] myID,
output [2:0] temp
);
reg [31:0] msgArray = 0;
reg [ 2:0] cur = 7;
reg [15:0] dataBus;
reg lmv_delay = 0, rmv_delay = 0, inc_delay ... | 6.689123 |
module is asynchronous(no clock needed)
`timescale 1ns/100ps
module dataRefine(LOAD,STORE,from_Dmem,DATA_IN,DATA_OUT,FUNCT3); //module for Data refine for Data memory
input LOAD,STORE; //control signals for load or store
input [31:0] from_Dmem,DATA_IN; ... | 6.912269 |
module DataReg (
DataIn,
DataOut,
CLK
);
input wire [31:0] DataIn;
output reg [31:0] DataOut;
input CLK;
always @(posedge CLK) begin
DataOut = DataIn;
end
endmodule
| 7.711258 |
module DataRegister (
input CLK,
input [31:0] Datain,
output reg [31:0] Dataout
);
reg [31:0] DataRegisterMem;
initial DataRegisterMem <= 0;
//negedge save posedge out
always @(negedge CLK) begin
DataRegisterMem <= Datain;
end
always @(posedge CLK) begin
Dataout <= DataRegisterMem;
en... | 8.262983 |
module DataRegisterFile #(
parameter reg_width = 32
) (
input CLK,
input [2:0] REG_SEL_A,
input [2:0] REG_SEL_B,
input S,
input [reg_width-1:0] D,
output [reg_width-1:0] Q_A,
output [reg_width-1:0] Q_B
);
wire [7:0] en_a;
wire [7:0] en_b;
Decoder #(3) reg_sel_a (
REG_SEL_A,... | 7.143786 |
module DataRegisterFile_test (
output TEST
);
assign TEST = 1;
reg [2:0] reg_sel_a;
reg [2:0] reg_sel_b;
reg s;
reg [31:0] d;
wire [31:0] q_a;
wire [31:0] q_b;
DataRegisterFile ds (
reg_sel_a,
reg_sel_b,
s,
d,
q_a,
q_b
);
initial begin
// we can set vi... | 7.143786 |
module DataSelect32 (
input [31:0] A,
input [31:0] B,
input Control,
output [31:0] S
);
assign S = (Control == 1'b0 ? A : B);
endmodule
| 7.530193 |
module DataSelect32_plus (
input [31:0] in0,
input [31:0] in1,
input [31:0] in2,
input [ 1:0] PCSrc,
input [31:0] out
);
assign out = (PCSrc[0] == 1) ? in1 : ((PCSrc[1] == 1) ? in2 : in0);
endmodule
| 8.312858 |
module DataSelect5 (
input [4:0] A,
input [4:0] B,
input Control,
output [4:0] S
);
assign S = (Control == 1'b0 ? A : B);
endmodule
| 7.160285 |
modules and getting use to vectors.
// I'd like to recognize Simon Monk. THis is his book/code that I'm learning from
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dataSelector(
... | 7.473839 |
module DataSelector_2to1 (
A,
B,
Control,
Result
);
input [31:0] A, B;
input Control;
output [31:0] Result;
assign Result = (Control == 1'b0 ? A : B);
endmodule
| 7.477673 |
module DataSelector_2to1_sa (
A,
B,
Control,
Result
);
input [31:0] A;
input [4:0] B;
input Control;
output [31:0] Result;
assign Result = (Control == 1'b0 ? A : {{27'o000000000}, B[4:0]});
endmodule
| 7.477673 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.