code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module data2ascii (
input [7:0] data,
input uppercase,
output [7:0] ascii
);
(* ram_init_file = "scancode.mif" *)reg [7:0] myrom1[255:0];
(* ram_init_file = "capscode.mif" *)reg [7:0] myrom2[255:0];
assign ascii = uppercase ? myrom2[data] : myrom1[data];
endmodule
| 8.062998 |
module data32to512_flow_control_loop_pipe_sequential_init (
ap_clk,
ap_rst,
ap_start,
ap_ready,
ap_done,
ap_start_int,
ap_ready_int,
ap_done_int,
ap_continue_int,
ap_loop_init,
ap_loop_exit_ready,
ap_loop_exit_done
);
input ap_clk;
input ap_rst;
//Block level hand... | 8.059735 |
module data32to512_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire ... | 6.919436 |
module data32to512_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
r... | 6.919436 |
module data32_to_data16 (
input wire sys_clk, //系统时钟
input wire sys_rst_n, //复位信号,低有效
input wire rec_en_in, //输入32位数据使能信号
input wire [31:0] rec_data_in, //输入32位数据
output reg rec_en_out, //输出16位数据使能信号
output reg [15:0] rec_data_out //输出16位数据
);
//******... | 8.64195 |
module DCell (
input clk,
input rst,
input Din,
input WriteEnable,
input Enable,
output Dout
);
wire q;
assign Dout = (Enable & ~WriteEnable) ? q : 'bz;
dff dffd (
.q (q),
.d (Din),
.wen(Enable & WriteEnable),
.clk(clk),
.rst(rst)
);
endmodule
| 7.556534 |
module DataBridge (
DataOut,
DV,
DL
);
input DataOut; // DV -> DL
input [7:0] DV; // ALU Operand2
inout [7:0] DL; // Internal databus
bridge_comb bridge_bits[7:0] (
.dl_bit (DL),
.dv_bit (DV),
.DataOut({8{DataOut}})
);
endmodule
| 8.312854 |
module bridge_comb (
dl_bit,
dv_bit,
DataOut
);
inout dl_bit;
input dv_bit;
input DataOut;
assign dl_bit = DataOut && ~dv_bit ? 1'b0 : 1'bz;
endmodule
| 7.710301 |
module dataBuffer (
dataControl,
dataIO,
dataMemory,
readEnable,
writeEnable
);
output reg [7:0] dataControl;
inout [7:0] dataIO;
inout [7:0] dataMemory;
input wire readEnable;
input wire writeEnable;
//if writing, data is fed from IO device
//if reading, dataIO should equal data ... | 7.219059 |
module DataCache_tb;
`include "Utility.v"
reg [ 31:0] readPtrA;
wire [ 31:0] readValueA;
wire readSuccessA;
reg [ 31:0] readPtrB;
wire [ 31:0] readValueB;
wire ... | 6.923064 |
module DataCombin2 (
i0,
i1,
o
);
parameter data_width = 1;
input [data_width - 1 : 0] i0, i1;
output [2 * data_width - 1 : 0] o;
assign o = {i1, i0};
endmodule
| 7.532094 |
module DataCombin3 (
i0,
i1,
i2,
o
);
parameter data_width = 1;
input [data_width - 1 : 0] i0, i1, i2;
output [3 * data_width - 1 : 0] o;
assign o = {i2, i1, i0};
endmodule
| 7.268724 |
module DataCompare4 (
input [3:0] iData_a,
input [3:0] iData_b,
input [2:0] iData,
output reg [2:0] oData
);
always @(*)
if (iData_a > iData_b) oData = 3'b100;
else if (iData_a < iData_b) oData = 3'b001;
else if (iData_a == iData_b) begin
if (iData == 3'b100) oData = 3'b100;
el... | 6.897477 |
module DataCompare8 (
input [7:0] iData_a,
input [7:0] iData_b,
output [2:0] oData
);
wire [2:0] fff;
DataCompare8_low ddd (
.iData_a(iData_a[3:0]),
.iData_b(iData_b[3:0]),
.oData (fff)
);
DataCompare8_high ggg (
.iData_a(iData_a[7:4]),
.iData_b(iData_b[7:4]),
... | 6.94835 |
module DataCompare8_low (
input [3:0] iData_a,
input [3:0] iData_b,
output reg [2:0] oData
);
always @(*)
if (iData_a > iData_b) oData = 3'b100;
else if (iData_a < iData_b) oData = 3'b001;
else if (iData_a == iData_b) oData = 3'b010;
endmodule
| 6.955637 |
module DataCompare8_high (
input [3:0] iData_a,
input [3:0] iData_b,
input [2:0] iData,
output reg [2:0] oData
);
always @(*)
if (iData_a > iData_b) oData = 3'b100;
else if (iData_a < iData_b) oData = 3'b001;
else if (iData_a == iData_b) begin
if (iData == 3'b100) oData = 3'b100;
... | 6.955637 |
module DataCompare8_tb ();
reg [7:0] iData_a;
reg [7:0] iData_b;
wire [2:0] oData;
DataCompare8 uut (
.iData_a(iData_a),
.iData_b(iData_b),
.oData (oData)
);
initial begin
#50 iData_a = 8'b10101011;
iData_b = 8'b01111101;
#50 iData_a = 8'b00101011;
iData_b = 8'b11111101;... | 6.955637 |
module yub2rgb (
input wire pclk, //74.25 MHZ pixel clock
input wire rst,
input wire [ 1:0] format,
input wire [11:0] vcnt, //vertical counter from video timing generator
input wire [11:0] hcnt, //horizontal counter from video timing generator
output wire ... | 6.968432 |
module dataConv (
input [7:0] dataIN,
input sign,
output [7:0] dataOUT
);
reg [7:0] dataOUT;
always @(*) begin
if (sign == 0) dataOUT = dataIN;
else dataOUT = ~dataIN + 1;
end
endmodule
| 8.439348 |
module dataCor (
input CLK,
input RSTn,
input ERROR,
input [63:0] PLS_DATA,
output [63:0] PLS_DATA_IND
);
//data pipe for time adjusment
reg [63:0] pls_data_pipe = 0;
assign PLS_DATA_IND = pls_data_pipe;
always @(posedge CLK, negedge RSTn) begin
if (~RSTn) begin
pls_data_pipe <=... | 7.031709 |
module for data[7:0] , crc[7:0]=1+x^2+x^7+x^8;
//-----------------------------------------------------------------------------
`default_nettype none
module datacrc(
input [7:0] data_in,
input crc_en,
output [7:0] crc_out,
input rst,
input clk);
reg [7:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
alw... | 7.303673 |
module datactl (
in,
data_ena,
data
);
output [7:0] data;
input [7:0] in;
input data_ena;
assign data = data_ena ? in : 8'bxxxx_xxxx;
endmodule
| 7.10198 |
module datactrl (
input wire clk_in,
input wire rst_in,
input wire rdy_in,
input wire rob_rst_in,
//from & to reorder buffer
input wire rob_datactrl_en_in,
input wire [2 : 0] rob_datactrl_width_in,
input wire [`AddressWidth - 1 : 0] rob_datactrl_addr_in,
input wire [`IDWidth - 1 : 0... | 6.883244 |
module DataDelay (
clk,
in_data,
out_data
);
parameter data_width = 8;
parameter delay = 1;
input clk;
input [data_width - 1 : 0] in_data;
output [data_width - 1 : 0] out_data;
genvar i;
generate
for (i = 0; i < delay; i = i + 1) begin : pip
reg [data_width - 1 : 0] tmp;
if ... | 6.660438 |
module datadelayer32 (
input clk,
input [31:0] in,
output reg [31:0] out
);
always @(negedge clk) begin
out <= in;
end
endmodule
| 6.727713 |
module DataExt (
input wire [31:0] IN,
input wire [ 1:0] ADDR,
input wire [ 2:0] WE3,
output reg [31:0] OUT
);
`include "Parameters.v"
wire [31:0] LB_IN;
wire [31:0] LH_IN;
assign LB_IN = (IN >> (ADDR * 32'h08)) & 32'h000000ff;
assign LH_IN = (IN >> (ADDR * 32'h08)) & 32'h0000ffff;
alway... | 8.591096 |
module DataExtend(
input wire [31:0] data,
input wire [1:0] addr,
input wire [2:0] load_type,
output reg [31:0] dealt_data
);
// TODO: Complete this module
/* addr的作用是在取半字或取一个字节时决定取的是32位中的那一部分 */
always @ (*)
begin
if (load_type == `LHU)
begin
case(a... | 8.95179 |
module HA (
a,
b,
sum,
carry
);
input a, b;
output sum, carry;
reg sum, carry;
always @(a or b) begin
sum = a ^ b;
carry = a & b;
end
endmodule
| 7.123396 |
module FA (
x,
y,
c_in,
sum,
c_out
);
input x, y, c_in;
output sum, c_out;
assign {c_out, sum} = x + y + c_in;
endmodule
| 7.58914 |
module mux3 (
select,
I,
O
);
input [1:0] select;
input [3:0] I;
output O;
wire O;
wire [1:0] select;
wire [3:0] I;
wire [3:0] op;
assign op[0] = I[0] & !select[1] & !select[0];
assign op[1] = I[1] & select[0] & !select[1];
assign op[2] = I[2] & !select[0] & select[1];
assign op[3]... | 6.811061 |
module logic_gates (
a,
b,
c,
d,
e,
f,
g,
h
);
input a, b;
output c, d, e, f, g, h;
assign c = a & b;
assign d = a | b;
assign e = a~&b;
assign f = a~|b;
assign g = a ^ b;
assign h = ~a;
endmodule
| 6.832568 |
module dataflow_fulladder (
input a,
b,
c,
d,
s2,
s1,
output x
);
assign x = s1 ? (s2 ? d : c) : (s2 ? b : a);
endmodule
| 8.308154 |
module dataflow_in_loop_bDo_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 4;
parameter MEM_SIZE = 15;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
in... | 6.973242 |
module dataflow_in_loop_bDo_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd15;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;... | 6.973242 |
module dataflow_in_loop_hist_0161_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distri... | 6.973242 |
module dataflow_in_loop_hist_0161 (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4;
parameter AddressWidth = 32'd2;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth -... | 6.973242 |
module dataflow_in_loop_pline_0 #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 4,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
input wire ... | 6.973242 |
module dataflow_in_loop_pline_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DW... | 6.973242 |
module dataflow_in_loop_pline_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] a... | 6.973242 |
module dataflow_in_loop_pre_hist_0 #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 2,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
input wire ... | 6.973242 |
module dataflow_in_loop_pre_hist_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [... | 6.973242 |
module dataflow_in_loop_pre_hist_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input [AddressWidth - 1:0]... | 6.973242 |
module dataflow (
input sub_sra, // sub sra alu
input insn_clk,
pc_clk,
rd_clk, // Sinais de clock gerados na CU
input reset, // reset
input pc_next_sel, // seletor pc next
input pc_alu_sel, // seletor pc alu
input alu_sel_a,
alu_sel_b, // seletor alu
input addr_sel, // se... | 8.706571 |
module datafmt6432 (
input wire [63:0] in_data,
input wire [ 1:0] size,
input wire [ 2:0] address,
output wire [31:0] out_data
);
reg [31:0] data /*verilator public*/; // Wire
// Format read data:
always @(*) begin
case (size)
2'b00: begin // 8
case (address[2:0])
... | 9.437592 |
module datagene (
clk,
rst_n,
wrf_din,
wrf_wrreq,
moni_addr,
syswr_done,
sdram_rd_ack
);
input clk; //FPAGʱź25MHz
input rst_n; //FPGA븴λź
//wrFIFOƽӿ
output [15:0] wrf_din; //sdramд뻺FIFO
output wrf_wrreq; //sdramд뻺FIFOЧ
output [21:0] moni_addr; //sdramдַ
output syswr_do... | 7.102271 |
module DataHazard (
input wire [31:0] IDinst,
input wire [31:0] EXinst,
input wire [31:0] MEMinst,
input wire [31:0] WBinst,
input wire EXrf_we,
input wire MEMrf_we,
input wire WBrf_we,
input wire [31:0] IDpc,
input wire [31:0] EXpc,
input wire re1,
input wire re2,
inp... | 6.781689 |
module dir (
inout [7:0] dataio,
input [7:0] datain,
input clk,
cs1,
cs2,
cs3,
rw,
reset,
output [7:0] dataout
);
reg [7:0] store;
tri [7:0] dataio;
wire [7:0] data_out, data_in;
assign dataio = rw ? data_out : 8'hzz;
assign data_in = ~rw ? dataio : 8'hzz;
assign datai... | 6.872143 |
module DataLatch (
CLK,
DL_Control1,
DL_Control2,
DataBus,
DL,
Res
);
input CLK;
input DL_Control1; // 1: Bus disable
input DL_Control2; // x37. ALU Result -> DL.
inout [7:0] DataBus; // External databus
/* verilator lint_off UNOPTFLAT */
inout [7:0] DL; // Internal databus
in... | 6.916649 |
module DataLate (
input [31:0] in,
output reg [31:0] out,
input clk
);
always @(negedge clk) out <= in;
endmodule
| 6.678969 |
module dataLoader #(
parameter DW = 256,
AW = 8
) (
input clk,
input rst,
input [2:0] top_level_state,
input [AW-1:0] base_a_ra, // base address for SRAM
input [AW-1:0] num_a_rd, // read data number - 1
input t_valid, // axi-stream
input [ 255:0] t_data, // axi-stre... | 8.313618 |
module datamem16 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [31:0] data;
input [8:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock... | 6.869183 |
module test_datamemory (
dutpassed
);
reg clk;
reg [31:0] address;
reg write_en;
reg read_en;
reg [31:0] data_in;
wire [31:0] data_out;
output reg dutpassed;
datamemory dut (
.clk(clk),
.address(address),
.write_en(write_en),
.read_en(read_en),
... | 6.778864 |
module datamemory (
rd_data,
rd_addr,
wr_data,
wr_addr,
wen,
ren,
clk
);
output reg [31:0] rd_data;
input [31:0] rd_addr, wr_addr;
input [31:0] wr_data;
input wen, ren;
input clk;
reg [31:0] datamemory[0:31];
always @(posedge clk) begin
if (wen) begin
datamemory[w... | 7.533611 |
module DataMemoryBlock (
ans_dm,
ans_ex,
DM_data,
mem_rw_ex,
mem_en_ex,
mem_mux_sel_dm,
reset,
clk
);
input [7 : 0] ans_ex;
input [7 : 0] DM_data;
input mem_rw_ex, mem_en_ex, mem_mux_sel_dm, reset, clk;
output wire [7 : 0] ans_dm;
reg [7 : 0] Ex_out;
wire [7 : 0] DM_out;
... | 6.667246 |
module: DataMemoryBlock
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DataMemoryBlock_TB;
// Inputs
reg [7:0] ans_ex;
reg [7:0] DM_data;
reg mem_rw_ex;
reg mem_en_ex;
reg me... | 6.731873 |
module DataMemoryMUX (
input [63:0] readData,
input [63:0] ALUresult,
input memToReg,
output reg [63:0] dataMemoryMUXout
);
always @(*)
case (memToReg)
0: dataMemoryMUXout = ALUresult;
1: dataMemoryMUXout = readData;
default: dataMemoryMUXout = ALUresult;
endcase
endmodule
| 8.863905 |
module DataMemoryPipline (
zero,
branch,
memRead,
memWrite,
readData2Reg,
aluRes,
clk,
pc_src,
readData,
aluResOut
);
input zero;
input branch;
input memRead;
input memWrite;
input [31:0] readData2Reg;
input [31:0] aluRes;
input clk;
output pc_src;
output reg [3... | 7.716123 |
module DataMemoryTest_v;
task passTest;
input [31:0] actualOut, expectedOut;
input [`STRLEN*8:0] testType;
inout [7:0] passed;
if (actualOut == expectedOut) begin
$display("%s passed", testType);
passed = passed + 1;
end else $display("%s failed: %d should be %d", testType, actualOu... | 6.894818 |
module DataMemoryTester;
// Inputs
reg [7:0] Address;
reg [63:0] WriteData;
reg MemWrite;
reg MemRead;
reg Clock;
// Outputs
wire [63:0] ReadData;
// Instantiate the Unit Under Test (UUT)
DataMemory uut (
.Address(Address),
.WriteData(WriteData),
.MemWrite(MemWrite),
.MemR... | 6.894818 |
module Data_Memory (
Clock,
MemRead,
ReadAddress,
ReadData,
MemWrite,
WriteAddress,
WriteData
);
input MemRead, MemWrite, Clock;
input [31:0] ReadAddress, WriteAddress;
input [31:0] WriteData;
output reg [31:0] ReadData;
reg [31:0] memory[0:31];
integer raddr, waddr;
initial be... | 7.239913 |
module DataMemory_Interface (
input iCLK,
iCLKMem,
// Barramento de IO
input wReadEnable,
wWriteEnable,
input [ 3:0] wByteEnable,
input [31:0] wAddress,
wWriteData,
output [31:0] wReadData
// input [31:0] wAddressS,
// output [31:0] wReadDataS
);
User... | 7.166151 |
module.
////////////////////////////////////////////////////////////////////////////////
module DataMemory_tb();
reg Clk;
reg [31:0] Address;
reg [31:0] WriteData;
reg MemWrite;
reg MemRead;
wire [31:0] ReadData;
DataMemory u0(
.Addr... | 6.641851 |
module dataMemory_tb ();
reg Clk;
reg [31:0] address;
reg [31:0] writeData;
reg memWrite;
reg memRead;
wire [31:0] readData;
dataMemory u0 (
Clk,
address,
writeData,
memWrite,
memRead,
readData
);
parameter PERIOD = 50;
always #(PERIOD * 2) Clk = !Clk;
initia... | 6.641942 |
module DataMemory_Test ();
reg Clock, MemWrite, MemRead;
reg [15:0] Adresa;
reg [15:0] WriteData;
wire [15:0] ReadData;
initial begin
#0 Clock = 1'b0;
#5 MemWrite = 1'b1;
Adresa = 16'b0000000000001001;
WriteData = 16'b0011001100110011;
MemRead = 1'b0;
#5 Clock = 1'b1;
#5 Clock =... | 6.980642 |
module: DataMemory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module dataMemory_tf;
// Inputs
reg RW;
reg [31:0] DAddr;
reg [31:0] Datain;
// Outputs
wire [31:0] DataOut;
// ... | 7.205301 |
module sign_mask_gen (
func3,
sign_mask
);
input [2:0] func3;
output [3:0] sign_mask;
reg [2:0] mask;
/*
* sign - for LBU and LHU the sign bit is 0, indicating read data should be zero extended, otherwise sign extended
* mask - for determining if the load/store operation is on word, halfword or by... | 6.970291 |
module datamem_mock #(
parameter SZ_LOG2 = 16,
parameter INITFILE = "datamem.txt"
) (
input clk,
input ce,
input we,
input [SZ_LOG2-1:0] addr,
input [7:0] din,
output reg [7:0] dout
);
localparam SIZE = 1 << SZ_LOG2;
wire [SZ_LOG2-1:0] addr_int;
wire [7:0] din_int;
reg [7:0] ... | 7.376225 |
module DataMem_tb;
`include "../src/utils/Assert.vh"
`include "../src/Parameters.vh"
// Input stimulus
reg clk;
reg [XLEN - 1 : 0] address;
reg [XLEN - 1 : 0] writeData;
reg writeEnable;
reg readEnable;
wire [XLEN - 1 : 0] readData;
integer i;
DataMem DUT (
.readData(readData),
.clk(... | 7.114892 |
module dataMem_Test ();
parameter IN_BUS_WIDTH = 32;
parameter MEMORY_WIDTH = 32; // Bits of Memory accessed at a time
reg CLK, writeEn, readEn;
reg [IN_BUS_WIDTH-1:0] ALUMemAdd;
reg [MEMORY_WIDTH-1:0] writeDataM; // 32bit data value
wire [MEMORY_WIDTH-1:0] readDataW;
initial begin
CLK = 0;
e... | 6.868562 |
module: dataMem
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module dataMem_tf;
// Inputs
reg clk;
reg we;
reg [31:0] addr;
reg [31:0] wd;
reg [31:0] entradas;
// Outputs
wire ... | 6.773898 |
module datamover_bram_sim_tb;
localparam FMC_TCLK_PERIOD = 4069; // 245.76 MHz
localparam RESET_PERIOD = 16276; //in pSec
reg fmc_tresetn_i;
reg fmc_tclk_i;
wire fmc_tclk;
wire fmc_tresetn;
initial begin
fmc_tclk_i = 1'b0;
end
initial begin
fmc_tresetn_i = 1'b0;
#RESET_PERIOD fmc_t... | 7.394979 |
module dataMuxRead (
dataOut,
sel00,
selAA,
sel55,
SCL
);
output reg [7:0] dataOut;
input wire sel00, selAA, sel55, SCL;
initial begin
sel00 = 0;
selAA = 0;
sel55 = 0;
end
always @(sel00 or selAA or sel55) begin
if (sel00) begin
dataOut <= 'h00;
end else if (se... | 6.744574 |
module dataMuxWrite (
dataOut,
dataIn,
selData,
selAA,
sel55,
SCL
);
output reg [7:0] dataOut;
input wire [7:0] dataIn;
input wire selData, selAA, sel55, selB0, selC0, selD0, selE0, SCL;
always @(negedge SCL) begin
if (selData) begin
dataOut <= dataIn;
end else if (selAA)... | 6.538704 |
module DATAP #(
parameter bits = 32
) (
input clk,
input [1:0] func,
input [bits-1:0] A,
B,
C,
output [bits*2-1:0] result, //needs to be as big as mult result
output reg [1:0] func_reg,
output reg [bits*2-1:0] mult_out_reg,
output reg [bits-1:0] c_reg
);
//Pipeline stage reg... | 6.610643 |
module test_dataPath;
reg [15:0] address;
reg clock;
reg regDst, regWrite, aluSrc, MemWrite, MemRead, memToReg, branch, Jump;
reg [ 2:0] ALUOp;
wire [15:0] next_address;
dataPath dp (
next_address,
address,
clock,
regDst,
regWrite,
aluSrc,
ALUOp,
MemWrite,... | 7.431269 |
module dataPath (
next_address,
address,
clock,
regDst,
regWrite,
aluSrc,
ALUOp,
MemWrite,
MemRead,
memToReg,
branch,
Jump
);
input [15:0] address;
input clock;
input regDst, regWrite, aluSrc, MemWrite, MemRead, memToReg, branch, Jump;
input [2:0] ALUOp;
outpu... | 7.068132 |
module instruction_memory (
readAddress,
i1,
i2,
i3,
i4,
jump
);
reg [7:0] instruction_mem[256:0];
input [15:0] readAddress;
output reg [3:0] i1;
output reg [3:0] i2;
output reg [3:0] i3;
output reg [3:0] i4;
output reg [11:0] jump;
// initialize values for instruction memory... | 7.714331 |
module register_file (
read_data1,
read_data2,
read_reg1,
read_reg2,
write_reg,
write_data,
regWrite,
clock
);
// Declare variables to be connected
// to inputs
reg [15:0] reg_file[15:0];
// output and input registers
output reg [15:0] read_data1;
output reg [15:0] read_da... | 6.605344 |
module bit16_mux2_to_1 (
out,
i0,
i1,
s
);
// Port declarations from the I/O diagram
output reg [15:0] out;
input [15:0] i0;
input [15:0] i1;
input s;
always @(s, i0, i1) begin
case (s)
1'b0: out = i0;
1'b1: out = i1;
default: $display("Invalid signal");
endcase... | 7.790561 |
module bit4_mux2_to_1 (
out,
i0,
i1,
s
);
// Port declarations from the I/O diagram
output reg [3:0] out;
input [3:0] i0;
input [3:0] i1;
input s;
always @(s, i0, i1) begin
case (s)
1'b0: out = i0;
1'b1: out = i1;
default: $display("Invalid signal");
endcase
e... | 7.372866 |
module sign_extend (
out,
in
);
// Declare variables to be connected to inputs and outputs
input [3:0] in; // 4-bit input
output reg [15:0] out; // 12-bit output
always @(in) begin
if (in[3] == 1)
out <= {
1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, in
... | 7.581479 |
module alu (
x,
y,
z,
c_in,
c_out,
lt,
eq,
gt,
overflow,
ALUOp
);
// Declare variables to be connected to inputs and outputs
input [15:0] x;
input [15:0] y;
output reg [15:0] z;
input c_in;
output reg c_out = 0;
output reg lt, eq, gt;
output reg overflow;
inpu... | 7.914753 |
module shift_16bits (
out,
in
);
// Declare variables to be connected to inputs and outputs
input [15:0] in;
output reg [15:0] out;
always @(in) begin
out <= {in[14:0], 1'b0}; // left shift
end
endmodule
| 8.416586 |
module add (
out,
in,
value
);
// Declare variables to be connected to inputs and outputs
input [15:0] in; // previous pc
input [15:0] value;
output reg [15:0] out; // next pc
always @(in) out <= in + value; // add value to the pc
endmodule
| 6.843391 |
module shift_12bit (
out,
in
);
input [11:0] in;
output reg [12:0] out;
always @(in) begin
out <= {in, 1'b0}; // left shift to 13 bit
end
endmodule
| 8.481994 |
module, replase magic number with pre-defined macros
*/
module DataPath
(PC, ALUResult, writeData, zero,
srcRegister1, srcRegister2, desRegister, imm, readData, clk, rst,
PCSrc, regWrite, immSrc, ALUSrc, ALUControl, memWrite, resultSrc);
`include "Parameters.vh"
input clk;
input rst;
//... | 8.375445 |
module Datapath (
input clk,
reset,
input memtoreg,
pcsrc,
input alusrc,
regdst,
input regwrite,
jump,
input [2:0] alucontrol,
output zero,
input [`datawidth-1:0] instr,
input [`datawidth-1:0] readdata,
output [`datawidth-1:0] pc,
aluout,
writedata
);
wire [... | 7.439732 |
module DatapathControl (
PCsrc,
EnW,
IMMSel,
ALUsrc,
Write,
WB,
Read,
Zero,
OP
);
output reg [1:0] IMMSel;
output reg PCsrc, EnW, ALUsrc, Write, WB, Read;
input Zero;
input [6:0] OP;
always @(OP) begin
case (OP)
7'b0110011: begin
PCsrc <= 0;
EnW... | 6.691536 |
module DatapathLEGv8 ( /*ControlWord, status, data,*/
clock,
reset
);
// input [96:0] ControlWord;
// inout [63:0] data;
input clock, reset;
// output [4:0] status;
wire [4:0] status;
wire [63:0] data;
wire [96:0] ControlWord;
wire [63:0] address;
wire EN_B;
wire [63:0] PC4;
wire [63:0] ... | 6.717409 |
module DataPathR (
input clk
);
wire [31:0] instOut; //Memoria de instrucciones a UC, BR, MUXBR,
wire regWrite; //Unidad de Control a Banco de Registro
wire [31:0] RData1, RData2; //Banco de Registro a ALU y Mem, el segundo va al mux
wire [31:0] MuxBrOut; //MUX21BR a ALU
wire [2:0] UALUOp; //Unidad... | 7.465234 |
module Datapaths (
input [25:0] j_path1,
input [20:0] j_path2,
input [31:0] j_path3,
input [31:0] read_data1,
input [2:0] flags,
input [2:0] jmp_type,
input [1:0] flag_select,
input j_select,
input jmp_reg,
input jmp_instr,
input [1:0] w_select,
input [4:0] Read_addr1,
... | 8.634252 |
module Datapath_32 (
input clk,
input RegDst,
Jump,
Branch,
MemRead,
MemtoReg,
MemWrite,
ALUSrc,
RegWrite,
input [1:0] ALUOp,
output [5:0] opcode
);
reg [31:0] pc_current;
wire [31:0] pc_next, pc2;
wire [31:0] instruction;
wire [4:0] rs_addr, rt_addr, rd_addr;
wire... | 8.292225 |
module datapath (
input clk,
input start,
input [6:0] a,
input [6:0] b,
input done,
output reg [12:0] product
);
reg [11:0] p, a_temp, b_temp, p_temp;
reg carry;
always @(posedge clk or posedge start) begin
if (start) begin
p <= 0;
carry <= 0;
a_temp <= a[5:0];
... | 6.91752 |
modules:
// 1. shift register A(SHIFTREG1)
// 2. shift register Q(SHIFTREG2)
// 3. dff(DFF)
// 4. PIPO M(PIPO)
// 5. ALU(ALU)
// 6. COUNTER(COUNTER)
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//... | 6.815306 |
module test_dataPath_with_controller;
reg [15:0] address;
reg clock;
wire [15:0] next_address;
dataPath_with_controller dp (
next_address,
address,
clock
);
initial begin
// check ADD operation
address = 16'b0;
clock = 0;
#1 $display("address=%b next_address=%b", addr... | 7.431269 |
module dataPath_with_controller (
next_address,
address,
clock
);
input [15:0] address;
input clock;
output wire [15:0] next_address;
wire [15:0] read_address;
wire [ 3:0] i1;
wire [ 3:0] i2;
wire [ 3:0] i3;
wire [ 3:0] i4;
wire [11:0] jump;
wire regDst, regWrite, aluSrc, MemWrite, Me... | 6.557964 |
module instruction_memory (
readAddress,
i1,
i2,
i3,
i4,
jump
);
reg [7:0] instruction_mem[256:0];
input [15:0] readAddress;
output reg [3:0] i1;
output reg [3:0] i2;
output reg [3:0] i3;
output reg [3:0] i4;
output reg [11:0] jump;
// initialize values for instruction memory... | 7.714331 |
module register_file (
read_data1,
read_data2,
read_reg1,
read_reg2,
write_reg,
write_data,
regWrite,
clock
);
// Declare variables to be connected
// to inputs
reg [15:0] reg_file[15:0];
// output and input registers
output reg [15:0] read_data1;
output reg [15:0] read_da... | 6.605344 |
module bit16_mux2_to_1 (
out,
i0,
i1,
s
);
// Port declarations from the I/O diagram
output reg [15:0] out;
input [15:0] i0;
input [15:0] i1;
input s;
always @(s, i0, i1) begin
case (s)
1'b0: out = i0;
1'b1: out = i1;
endcase
end
endmodule
| 7.790561 |
module bit4_mux2_to_1 (
out,
i0,
i1,
s
);
// Port declarations from the I/O diagram
output reg [3:0] out;
input [3:0] i0;
input [3:0] i1;
input s;
always @(s, i0, i1) begin
case (s)
1'b0: out = i0;
1'b1: out = i1;
endcase
end
endmodule
| 7.372866 |
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