code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DataSelector_3to1 (
A,
B,
C,
Control,
Result
);
input [4:0] A, B, C;
input [1:0] Control;
output reg [4:0] Result;
always @(Control or A or B or C) begin
case (Control)
2'b00: Result = A;
2'b01: Result = B;
2'b10: Result = C;
default: Result = 0;
... | 7.477673 |
module DataSelector_4bit (
//define inputs
input [7:0] _dataInA,
input [7:0] _dataInB,
input _select,
//define outputs
output [7:0] _dataOut
);
assign _dataOut = (_select == 1'b1) ? _dataInB : _dataInA;
endmodule
| 7.477673 |
module DataSelector_4to1 (
A,
B,
C,
D,
Control,
Result
);
input [31:0] A, B, C, D;
input [1:0] Control;
output reg [31:0] Result;
always @(Control or A or B or C or D) begin
case (Control)
2'b00: Result = A;
2'b01: Result = B;
2'b10: Result = C;
2'b11: ... | 7.477673 |
module DataSelector_nBit (
//define inputs
input [15:0] _dataInA,
_dataInB,
input _selectLine,
//define outputs
output [15:0] _dataOut
);
assign _dataOut = (_selectLine == 1'b0) ? _dataInA : _dataInB;
endmodule
| 7.477673 |
module DataSend #(
parameter CLKFREQ = 100_000_000,
parameter BAUDRATE = 115200,
parameter BYTENUM = 7
) (
input clk,
input reset,
input enable,
input [8*BYTENUM-1:0] dataIn,
output uartTx,
output dataTxDone
);
wire nextByteEnable;
parameter WIDTH = 8; //8254ֽڵݣĿǰãԺ
reg ... | 7.478474 |
module DataSend_tb;
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg reset;
initial begin
reset = 1'b0;
#50 reset = 1'b1;
#34567 reset = 1'b0;
#20 reset = 1'b1;
#300 reset = 1'b0;
#2000 reset = 1'b1;
end
reg enable;
initial enable = 1'b0;
always #500900 enable = 1'b1;
... | 6.625028 |
module DataSeparator (
MASTER_CLK,
CLKEN,
FD_RDDATA_IN,
SHAPED_DATA,
DWIN
);
input MASTER_CLK; // Master Clock -- Data rate * PJL_COUNTER_MAX
input CLKEN; // Clock Enable -- allows input clock to be divided down
input FD_RDDATA_IN; // L->H on flux transition
output SHAPED_DATA; // Resha... | 8.79775 |
module dataset #(
parameter NEURON_NUM = 5,
ACTIVATION_WIDTH = 9,
DATASET_ADDR_WIDTH = 10,
MAX_SAMPLES = 1000,
INPUT_SAMPLES_FILE = "inputs.list",
OUTPUT_SAMPLES_FILE = "outputs.list"
) (
input ... | 6.619 |
module dataShifter (
data,
offset,
shiftedData
);
input [15:0] data;
input [4:0] offset;
output reg [15:0] shiftedData;
// Considerando shift para a esquerda negativo e para a direita positivo
always @(*) begin
if (offset[4]) begin
shiftedData = data << offset[3:0];
end else begin
... | 7.154049 |
module DataSplit4 (
i,
o0,
o1,
o2,
o3
);
parameter data_width = 1;
input [4 * data_width - 1 : 0] i;
output [data_width - 1 : 0] o0, o1, o2, o3;
assign o0 = i[1*data_width-1 : 0*data_width];
assign o1 = i[2*data_width-1 : 1*data_width];
assign o2 = i[3*data_width-1 : 2*data_width];
... | 7.947558 |
module dataStorer (
input clk,
input rst,
input [2:0] top_level_state,
input pre_state_finish_flg, // transfer to 4 flg
output reg state_finish_flg,
input [7:0] tile_size, //tile_size -> real_size - 1
input [7:0] pb_addr,
input t_ready,
output t_valid,
output [63:0] t_data,
... | 7.480207 |
module DataSync (
input clk,
input [31:0] iData,
output [31:0] oData
);
reg [31:0] oData;
always @(negedge clk) begin
oData = iData;
end
endmodule
| 7.972967 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module DataTransmitter (
input wire clock,
// Assert to run.
input wire run,
// Configuration settings
input wire [15:0] flags,
input wire [10:0] read_count_x4,
input wire [12:0] last_sample_address,
// Reading memory.
input wire [ 7:0] read_data,
output reg [12:0] read_add... | 7.75225 |
module DataTransmitter_TB ();
parameter CLOCKS_PER_BIT = 5;
parameter CLOCK_PERIOD_NS = 10;
reg clock = 0;
// Run the data transmitter
reg run = 0;
reg [15:0] flags = 0;
// The final write address.
reg [12:0] last_sample_address = 100;
// If the buffer is full (i.e. looped round).
reg full = 0;... | 7.75225 |
module DataTxMux (
output UARTRequestToSend,
output ReadyToRead,
output [7:0] DataOut,
input Clk,
input Reset,
input [31:0] FIFOData,
input FIFODataValid,
input UARTDataLoaded
);
localparam IDLE = 1'b0, TRANSMIT = 1'b1;
reg CurrentState = IDLE;
reg NextState = IDLE;
reg [31:0]... | 8.513174 |
module DataUnitTest;
reg [3:0] Multiplicant;
reg [3:0] Multiplier;
reg [2:0] Shift1;
reg [2:0] Shift0;
reg reset, clock;
wire [7:0] Product;
DataUnit uut (
Product,
Multiplicant,
Multiplier,
Shift1,
Shift0,
reset,
clock
);
always #5 clock = ~clock;
initia... | 6.940409 |
module DataWidthConvert (
i,
o
);
parameter data_width_in = 32;
parameter data_width_out = 4;
input [data_width_in - 1 : 0] i;
output [data_width_out - 1 : 0] o;
generate
if (data_width_in >= data_width_out) begin
assign o = i[data_width_in-1 : 0];
end else begin
assign o = {{da... | 6.985189 |
module datawr (
input clk,
input rst_n,
output [3:0] we_wr,
output en_wr,
output reg [11:0] addr_rd_o
);
reg [4:0] counter;
assign we_wr = 4'hF;
assign en_wr = 1'b1;
always @(posedge clk) begin
if (rst_n == 1'b0) counter <= 1'b0;
else if (counter == 5'd19) counter <= 1'b0;
else... | 6.624931 |
module dataWRSM (
clk,
Wfull,
rst_n,
Winc,
cont_out
);
parameter WIDTH = 16;
input clk, Wfull, rst_n;
output Winc;
wire en;
output wire [WIDTH-1:0] cont_out;
UC mod_UC (
.clk(clk),
.rst_n(rst_n),
.data_in(cont_out),
.wfull(Wfull),
.winc(Winc),
.en(en... | 7.825019 |
module data_1r1w (
input clk,
input [11:0] ram_radr,
output [31:0] ram_rdata,
input [11:0] ram_wadr,
input [31:0] ram_wdata,
input [3:0] ram_wen
);
// 4x1024 1r1w RAM
reg [ 7:0] ram0 [0:4095];
reg [ 7:0] ram1 [0:4095];
reg [ 7:0] ram2 [0:4095];
reg [ 7:0] ram3 [0:4095];
reg [11:0] ... | 6.760905 |
module data_2_1_theta_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg ... | 6.555694 |
module data_2_1_theta (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0... | 6.555694 |
module data_access (
clk,
rst_n,
mem_addr,
mem_wr,
mem_byte_en,
mem_req,
mem_wr_data,
mem_rd_data,
mem_rdy,
core_mem_addr,
core_mem_addr_vld,
core_mwr_mrd,
d_mhaddr,
d_mhtrans,
d_mhwrite,
d_mhwdata,
d_mhsize,
d_mhburst,
d_mhprot,
d_mhmast... | 7.685015 |
module fifo_8x2048_fifo_generator_ramfifo (
dout,
empty,
full,
rd_en,
wr_en,
clk,
srst,
din,
lopt,
pwropt,
pwropt_1,
pwropt_2,
lopt_1
);
output [7:0] dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input srst;
input [7:0] din;
i... | 6.701436 |
module fifo_8x2048_fifo_generator_ramfifo_HD6 (
empty,
full,
rd_en,
wr_en,
clk,
srst,
dout,
din
);
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input srst;
output [7:0] dout;
input [7:0] din;
wire clk;
wire [7:0] din;
wire [7:0] dout;
wire empt... | 6.701436 |
module fifo_8x2048_fifo_generator_top (
dout,
empty,
full,
rd_en,
wr_en,
clk,
srst,
din,
lopt,
pwropt,
pwropt_1,
pwropt_2,
lopt_1
);
output [7:0] dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input srst;
input [7:0] din;
input... | 6.701436 |
module fifo_8x2048_fifo_generator_top_HD5 (
empty,
full,
rd_en,
wr_en,
clk,
srst,
dout,
din
);
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input srst;
output [7:0] dout;
input [7:0] din;
wire clk;
wire [7:0] din;
wire [7:0] dout;
wire empty;
... | 6.701436 |
module fifo_8x2048_fifo_generator_v12_0_synth (
dout,
empty,
full,
rd_en,
wr_en,
clk,
srst,
din,
lopt,
pwropt,
pwropt_1,
pwropt_2,
lopt_1
);
output [7:0] dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input srst;
input [7:0] din;... | 6.701436 |
module fifo_8x2048_fifo_generator_v12_0_synth_HD4 (
empty,
full,
rd_en,
wr_en,
clk,
srst,
dout,
din
);
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input srst;
output [7:0] dout;
input [7:0] din;
wire clk;
wire [7:0] din;
wire [7:0] dout;
wire ... | 6.701436 |
module upcnt_n (
D,
Q,
seq_cnt_en,
seq_clr,
slowest_sync_clk
);
output [0:0] D;
output [2:0] Q;
input seq_cnt_en;
input seq_clr;
input slowest_sync_clk;
wire [0:0] D;
wire [2:0] Q;
wire clear;
wire [5:0] q_int0;
wire \q_int_reg_n_0_[0] ;
wire \q_int_reg_n_0_[1] ;
wire \q_int... | 7.07605 |
module vga_fifo_fifo_generator_ramfifo (
dout,
empty,
full,
prog_full,
rd_clk,
wr_clk,
din,
rst,
rd_en,
wr_en
);
output [35:0] dout;
output empty;
output full;
output prog_full;
input rd_clk;
input wr_clk;
input [35:0] din;
input rst;
input rd_en;
input wr_en;... | 6.658047 |
module vga_fifo_fifo_generator_top (
dout,
empty,
full,
prog_full,
rd_clk,
wr_clk,
din,
rst,
rd_en,
wr_en
);
output [35:0] dout;
output empty;
output full;
output prog_full;
input rd_clk;
input wr_clk;
input [35:0] din;
input rst;
input rd_en;
input wr_en;
... | 6.658047 |
module vga_fifo_fifo_generator_v12_0_synth (
dout,
empty,
full,
prog_full,
rd_clk,
wr_clk,
din,
rst,
rd_en,
wr_en
);
output [35:0] dout;
output empty;
output full;
output prog_full;
input rd_clk;
input wr_clk;
input [35:0] din;
input rst;
input rd_en;
input wr... | 6.658047 |
module cdc_sync (
scndry_out,
aux_reset_in,
slowest_sync_clk
);
output scndry_out;
input aux_reset_in;
input slowest_sync_clk;
wire D;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2_n_0 ;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d... | 6.556666 |
module fifo_32x512 (
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input srst;
input [31:0] din;
input wr_en;
input rd_en;
output [31:0] dout;
output full;
output empty;
endmodule
| 6.748765 |
module upcnt_n (
D,
Q,
seq_cnt_en,
seq_clr,
slowest_sync_clk
);
output [0:0] D;
output [2:0] Q;
input seq_cnt_en;
input seq_clr;
input slowest_sync_clk;
wire [0:0] D;
wire [2:0] Q;
wire clear;
wire [5:0] q_int0;
wire \q_int_reg_n_0_[0] ;
wire \q_int_reg_n_0_[1] ;
wire \q_int... | 7.07605 |
module cdc_sync (
scndry_out,
aux_reset_in,
slowest_sync_clk
);
output scndry_out;
input aux_reset_in;
input slowest_sync_clk;
wire D;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2_n_0 ;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d... | 6.556666 |
module fifo_32x512 (
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input srst;
input [31:0] din;
input wr_en;
input rd_en;
output [31:0] dout;
output full;
output empty;
endmodule
| 6.748765 |
module upcnt_n (
D,
Q,
seq_cnt_en,
seq_clr,
slowest_sync_clk
);
output [0:0] D;
output [2:0] Q;
input seq_cnt_en;
input seq_clr;
input slowest_sync_clk;
wire [0:0] D;
wire [2:0] Q;
wire clear;
wire [5:0] q_int0;
wire \q_int_reg_n_0_[0] ;
wire \q_int_reg_n_0_[1] ;
wire \q_int... | 7.07605 |
module Data_arrange (
clk,
data_in,
buf_empty,
rst,
PE_empty,
rd_en,
data_out,
arrange_ready
);
parameter IN_WIDTH = 4;
parameter OUT_WIDTH = 252;
parameter PE_NUM = 4;
input clk;
input [IN_WIDTH - 1:0] data_in;
input buf_empty; // 0:not empty, 1:empty
input rst;
inp... | 7.16718 |
module data_bank #(
parameter addr_width = 8,
data_width = 14,
depth = 256
) (
input clk,
input [addr_width-1:0] A1,
input [addr_width-1:0] A2,
input [data_width-1:0] D,
input WEN,
input REN,
input EN,
output reg [data_width-1:0] Q
);
(*ram_style = "block"*) reg [data_width... | 6.636722 |
module data_buf (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q
);
input aclr;
input clock;
input [7:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [7:0] q;
wire sub_wire0;
wire sub_wire1;
wire [7:0] sub_wire2;
wire empty = sub_wire0;
w... | 6.80542 |
module fifo
#(
parameter WIDTH = 8;
parameter DEPTH = 9;
)
(
input wr_clk,
input rst_n,
input wr_en,
input [WSIZE-1 : 0]din,
input rd_clk,
input rd_en,
output [WSIZE-1 : 0]dout,
output reg rempty,
output reg wfull
);
//定义变量
reg [WSIZE-1 : 0] mem [0 : (2**(D... | 7.606316 |
module Data_Buffer_tb;
reg clk, rst, enable, start_read, r_ack, stop;
wire [7:0] w_time, w_channels;
reg [19:0] count;
wire buffer_full, w_sample_clk_posedge, w_rollover, w_triggered_state, w_event, finished_read, post_read, t_rdy;
wire [15:0] data;
Pulse_Sync #(
.DATA_WIDTH(8)
) PS (
.i_sy... | 7.629433 |
module data_buf (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q
);
input aclr;
input clock;
input [7:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [7:0] q;
endmodule
| 6.80542 |
module io #(
parameter ram_width = 14,
parameter bus_width = 3
) (
input clk,
input rw,
input [63:0] addr,
input [63:0] write,
output [63:0] read,
output reg [7:0] led = 0,
output exception
);
//assign read = exception | rw? 0: ram_array[addr >> bus_width]; //Each cell have 8 byte... | 6.974532 |
module data_bus (
input clk,
input rw,
input [63:0] addr,
input [63:0] write,
output [63:0] read,
output [7:0] led,
output exception
);
reg [63:0] read_csr = 3; //just for debug
reg exception_csr = 0; //just for debug
wire [63:0] write_io;
io core0_io (
.clk(clk),
.rw(... | 6.593467 |
module Data_bus_buffer (
input control_logic,
inout [7:0] bus_cpu,
inout [7:0] bus
);
assign bus = (control_logic)? bus_cpu : 8'bzzzz_zzzz ; // if control = 1 A processor write on ports
assign bus_cpu = (control_logic)? 8'bzzzz_zzzz : bus; // if control = 0 processor read from ports
endmodule
| 6.551795 |
module data_bus_test
//
// Dependencies: data_bus_test
//
////////////////////////////////////////////////////////////////////////////////
module data_bus_test_tb;
// INPUTS //////////////////////////////////////////////////////////////////////
reg clk;
reg rst;
reg en;
reg ready;
... | 6.733991 |
module data_cache_0 (
input wire csi_clockreset_clk, // clockreset.clk
input wire csi_clockreset_reset_n, // clockreset_reset.reset_n
output wire [ 7:0] aso_PROC_data, // PROC.data
input wire avs_CACHE0_beg... | 6.781413 |
module/data_memory.v"
module data_cache_tb;
reg CLK, RESET;
reg[3:0] READ_WRITE;
reg [31:0] WRITEDATA, ADDRESS;
wire BUSYWAIT, MEM_BUSYWAIT, MEM_READ, MEM_WRITE;
wire [127:0] MEM_READDATA, MEM_WRITEDATA;
wire [27:0] MEM_ADDRESS;
wire [31:0] READDATA;
data_cache my_data_cache(CLK, RESET, BUSYWAIT, READ_WRITE, WRITEDA... | 7.077241 |
module data_cache_test;
reg clk;
reg rst;
reg [31:0] data_addr;
reg [31:0] data_out;
reg data_we;
reg data_rd;
reg [3:0] data_sel;
reg data_sign_ext;
reg [31:0] data_i;
reg ack_i;
reg fence;
wire [31:0] data_in;
wire data_ready;
wire [31:0] addr_o;
wire [31:0] data_o;
wire we_o;
wire ... | 6.894964 |
module data_cache_way0 (
A,
CLK,
D,
WE,
SPO
); // synthesis black_box
input [4 : 0] A;
input CLK;
input [52 : 0] D;
input WE;
output [52 : 0] SPO;
// synopsys translate_off
C_DIST_MEM_V4_1 #(5, // c_addr_width
"0", // c_default_data
1, // c_default_data_radix
32, // c_dep... | 7.128303 |
module data_cache_way1 (
A,
CLK,
D,
WE,
SPO
); // synthesis black_box
input [4 : 0] A;
input CLK;
input [52 : 0] D;
input WE;
output [52 : 0] SPO;
// synopsys translate_off
C_DIST_MEM_V4_1 #(5, // c_addr_width
"0", // c_default_data
1, // c_default_data_radix
32, // c_dep... | 7.128303 |
module data_cache_way2 (
A,
CLK,
D,
WE,
SPO
); // synthesis black_box
input [4 : 0] A;
input CLK;
input [52 : 0] D;
input WE;
output [52 : 0] SPO;
// synopsys translate_off
C_DIST_MEM_V4_1 #(5, // c_addr_width
"0", // c_default_data
1, // c_default_data_radix
32, // c_dep... | 7.128303 |
module data_cache_way3 (
A,
CLK,
D,
WE,
SPO
); // synthesis black_box
input [4 : 0] A;
input CLK;
input [52 : 0] D;
input WE;
output [52 : 0] SPO;
// synopsys translate_off
C_DIST_MEM_V4_1 #(5, // c_addr_width
"0", // c_default_data
1, // c_default_data_radix
32, // c_dep... | 7.128303 |
module data_cap #(
parameter WIDTH = 8
) (
// The parallel video input data
input wire [WIDTH-1:0] red,
input wire [WIDTH-1:0] grn,
input wire [WIDTH-1:0] blu,
// The master video clock
input wire clk,
// The HSYNC video signal
input wire hsync,
// The VSYNC video signal
i... | 8.896442 |
module data_cell (
clk,
reset_n,
fsm,
sin,
din,
vtc_en,
dvtc_a,
dvtc_b,
dvtc_c,
ram_d
);
parameter D_WID = 8;
input clk;
input reset_n;
input [D_WID-1:0] din; // LLR input
input sin;
input [3:0] fsm;
input [2:0] vtc_en;
input [D_WID-1:0] dvtc_a;
input [D_WID... | 7.586388 |
module data_cell1 (
clk,
reset_n,
fsm,
sin,
din,
vtc_en,
dvtc_a,
dvtc_b,
dvtc_c,
d_last,
ram_d
);
parameter D_WID = 8;
input clk;
input reset_n;
input [D_WID-1:0] din; // LLR input
input sin;
input [3:0] fsm;
input [2:0] vtc_en;
input [D_WID-1:0] dvtc_a;
... | 6.533034 |
module data_cell2 (
clk,
reset_n,
fsm,
sin,
din,
vtc_en,
dvtc_a,
dvtc_b,
dvtc_c,
d_last,
ram_d
);
parameter D_WID = 8;
input clk;
input reset_n;
input [D_WID-1:0] din; // LLR input
input sin;
input [3:0] fsm;
input [2:0] vtc_en;
input [D_WID-1:0] dvtc_a;
... | 6.638247 |
module Data_Choose (
input [2:0] display_type,
input [31:0] memory,
input [31:0] total,
input [31:0] conditional_jmp,
input [31:0] unconditional_jmp,
input [31:0] successful_conditional_jmp,
input [31:0] syscall,
input [31:0] PC,
input clk,
output [7:0] AN,
output [7:0] SEG
)... | 6.996256 |
module Data_collect (
input clk,
input rst,
input [7:0] data_input,
input data_ready,
output reg MEM_write_enable,
output reg [13:0] MEM_write_addr,
output reg [7:0] MEM_write_data,
output finish,
output reg collect_finish_display
);
parameter NUM_DATA = 2500;
reg [13:0] delaye... | 6.521435 |
module: Data_collect
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Data_collect_tb;
// Inputs
reg clk;
reg rst;
reg [7:0] data_input;
reg data_ready;
// Outputs
wire MEM_w... | 6.961222 |
module comm_clock (
int_clk,
send,
send_id,
trigger_id
);
input int_clk;
output reg [2:0] send_id;
output reg send, trigger_id;
reg [26:0] counter;
reg [26:0] data1byte1 = 27'b101_1110_1110_0000_0010_1111_1000; // @1Hz
reg [26:0] data1byte2 = 27'b101_1110_1110_1110_0010_1100_0000; // @... | 6.527921 |
module data_comparator (
bist_data_in,
mem_data_in,
passfail_out
);
//-----------------------------------------------
// Parameters and Definitions
//-----------------------------------------------
parameter dw = `DATA_WIDTH;
parameter aw = `ADDR_WIDTH;
//--------------------------------------... | 8.916948 |
module data_control #(
parameter WIDTH = 1
) (
addr,
mem_write_in,
mem_write_out,
d_out_addr
);
localparam ADDR_WIDTH = $clog2(WIDTH);
input [WIDTH-1:0] addr;
input mem_write_in;
output [WIDTH-1:0] mem_write_out;
output reg [ADDR_WIDTH-1:0] d_out_addr;
decod dec_0 (
d_out_addr,... | 8.915991 |
module data_convert(
input wire reset_n,
start,
clk,
byte,
input reg [7 : 0] data_in,
output reg [7 : 0] data_o,
output reg data_en
);
reg [3 : 0] buffer;
reg flag;
always@(posedge clk)
begin
if(!reset_n)
begin
buffer = 0;
data_en = 0;
flag = 0;
end
else
begin
... | 7.303201 |
module data_create (
clk,
reset_n,
out
);
input clk, reset_n;
output wire out;
reg [0:15] CODE = 16'b1010_0111_1101_0001;
reg [ 3:0] address = 4'b0000;
assign out = CODE[address];
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
address <= 4'b0000;
end else be... | 6.562012 |
module data_cross (
input clkIn,
input clkOut,
input [WIDTH-1:0] dataIn,
output wire [WIDTH-1:0] dataOut
);
parameter WIDTH = 24;
reg wrreq = 0;
reg rdreq = 0;
wire rdempty = |rdempty8;
wire [WIDTH/8-1:0] rdempty8;
reg [WIDTH-1:0] dataIn_reg = 0;
/*
data_fifo #(
.WIDTH(WIDTH)... | 7.004385 |
module Data_CrossDomain (
input clkA,
input FlagIn_clkA,
input clkB,
output FlagOut_clkB,
input [7:0] dataA,
output [7:0] dataB
);
// this changes level when the FlagIn_clkA is seen in clkA
reg FlagToggle_clkA;
initial FlagToggle_clkA <= 0;
always @(posedge clkA) FlagToggle_clkA <= Flag... | 8.018569 |
module data_deal (
clk,
rst_n,
data_in,
data_in_sign,
data_out,
data_out_sign,
data_valid,
data_ok
);
input clk;
input rst_n;
input [6:0] data_in;
input data_in_sign;
output [6:0] data_out;
output data_out_sign;
input data_valid;
output data_ok;
reg [6:0] data_... | 6.852356 |
module data_demux (
adress,
in0,
in1,
in2,
in3,
in4,
out
);
input [3:0] adress;
input [7:0] in0, in1, in2, in3, in4;
output [7:0] out;
wire [7:0] in0, in1, in2, in3, in4;
reg [7:0] out;
always @(adress or in0 or in1 or in2 or in3 or in4) begin
case (adress)
4'b0001:... | 7.072261 |
module data_demux_2 (
input clk,
input [ 7:0] adr,
input [ 7:0] n_data,
input [15:0] data_in,
input data_strb,
input crc_validate,
input reset,
output reg [15:0] data_340_2,
output reg [15:0] data_341_2,
output reg [1... | 6.607228 |
module data_dependency_block (
imm,
op_dec,
RW_dm,
mux_sel_A,
mux_sel_B,
imm_sel,
mem_en_ex,
mem_rw_ex,
mem_mux_sel_dm,
ins,
clk,
reset
);
output reg [15:0] imm;
output reg [5:0] op_dec;
output reg [4:0] RW_dm;
output [1:0] mux_sel_A, mux_sel_B;
output mem_en_ex... | 7.153067 |
module d_flip_flop(Q,D,clk,reset);
// output reg Q;
// input D, clk, reset;
// always@(posedge clk)
// begin
// if(reset)
// Q <= D;
// else
// Q <= 1'b0;
// end
// endmodule
| 7.577826 |
module: data_dependency_block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module data_dependency_block_tb;
// Inputs
reg [31:0] ins;
reg clk;
reg reset;
// Outputs
wire [15:0] i... | 7.23841 |
module data_dispatcher (
clk,
FSM_data,
write_halt,
ctrl2pe,
pe2ctrl,
ifmap_din,
wght_din,
ofmap_dout
);
parameter idle=4'd0, load_wght_req=4'd1, load_wght_burst=4'd2, load_wght_cmplt=4'd3, load_ifmap_req=4'd4, load_ifmap_burst=4'd5, load_ifmap_cmplt=4'd6, ifmap_filling_zero=4'd7, off... | 6.809904 |
module data_distributor (
input dat,
input [1:0] addr,
output [3:0] out
);
// 数据分配器的输出逻辑式
assign out[0] = dat & (!addr[1]) & (!addr[0]);
assign out[1] = dat & (!addr[1]) & (addr[0]);
assign out[2] = dat & (addr[1]) & (!addr[0]);
assign out[3] = dat & (addr[1]) & (addr[0]);
endmodule
| 7.505496 |
module data_dqpsk_generator (
clock,
reset,
trigger,
data_output
);
input clock, reset, trigger;
output reg [1:0] data_output;
reg preamble;
reg [7:0] counter;
always @(posedge clock or negedge reset) begin
if (!reset) begin
data_output <= 0;
preamble <= 1;
counter <= 0... | 7.033068 |
module data_drive (
input wire clk,
input wire vga_clk,
input wire rst_n,
input wire [11:0] addr_h,
input wire [11:0] addr_v,
input wire data_vld,
input wire [23:0] distance_data,
output wire [15:0] rgb_data
);
localparam red = 16'd63488;
localpara... | 7.077048 |
module with a UART. I ran into some UART issues with my first board (which no
* longer works, so I'd rather avoid UART for now).
*/
module data_exporter #(parameter WIDTH=26, VAL=48000000) (
input wire clk,
input wire en,
input wire [27:0] data,
output reg [7:0] leds
);
reg [2:0] state;
reg [27:0] data_to_se... | 6.610616 |
module data_ext (
data_in,
funt3,
data_out
);
input [31:0] data_in;
input [2:0] funt3;
output [31:0] data_out;
reg [31:0] data_out_temp;
always @(*) begin
case (funt3)
3'b000: data_out_temp = {{24{data_in[7]}}, data_in[7:0]}; //LB
3'b001: data_out_temp = {{16{data_in[15]}}, d... | 8.160565 |
module data_ext (
input wire [ 2:0] opcode,
input wire [31:0] d_in,
output wire [31:0] d_out
);
reg [31:0] data_out;
always @(*) begin
case (opcode)
`LB: data_out = {{24{d_in[7]}}, d_in[7:0]};
`LH: data_out = {{16{d_in[15]}}, d_in[15:0]};
`LBU: data_out = {{24{1'b0}}, d_in[7:0]... | 8.160565 |
module data_extract (
in,
rc,
regime,
exp,
mant,
Lshift
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 16;
parameter Bs = log2(N);
parameter... | 7.155904 |
module data_extractor (
input [31:0] instruction,
output reg [63:0] imm_data
);
wire [11:0] data1;
wire [11:0] data2;
wire [11:0] data3;
wire [ 1:0] mode;
assign data1 = instruction[31:20];
assign data2[4:0] = instruction[11:7];
assign data2[11:5] = instruction[31:25];
assign data3[3:0] = inst... | 7.289865 |
module data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_of... | 7.149438 |
module data_fifo_dist (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
overflow,
prog_full,
underflow
);
input [161 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [161 : 0] dout;
output empty;
output full;... | 6.931822 |
module data_fifo_tb;
parameter MASTER_PERIOD = 4;
// clocks
wire rd_clk, wr_clk;
clock_gen #(10) mclka (rd_clk);
clock_gen #(10) mclkb (wr_clk);
// Inputs
reg rst;
reg [15:0] din;
reg wr_en, rd_en;
// Outputs
wire full, empty;
wire [63:0] dout;
wire [12:0] wr_data_count;
// Instantiate t... | 6.680481 |
module data_fir (
clk,
rst_n,
data_out,
clk_data,
fir_out,
clk_fir
);
`define OUT_WIDTH 8
`define FIR_OUT_SIZE 23
input clk; //定义系统时钟
input rst_n; //复位信号
output [`OUT_WIDTH-1:0] data_out; //输出波形数据
output [`OUT_WIDTH-1:0] fir_out; //输出波形数据
output clk_data; //输出波形数据时钟
output ... | 7.83588 |
module data_flow_example (
input a,
input b,
input c,
input d,
output out
);
assign out = ~(((a & b) | (~c)) & d);
endmodule
| 8.428496 |
module data_formatter (
input wire GCLK,
input wire RST,
input wire dec,
input wire [7:0] temp_data_in,
input wire [15:0] x_axis_in,
input wire [15:0] y_axis_in,
input wire [15:0] z_axis_in,
output wire [15:0] x_axis_out,
output wire [15:0] y_axis_out,
output wire [15:0] z_axis_o... | 7.431966 |
module Data_Forward (
input [4:0] RA,
input [4:0] RB,
input MB,
input [4:0] RD_MEM,
input [4:0] RD_WB,
input WE_MEM,
input WE_WB,
output [1:0] A_sel,
output [1:0] B_sel
);
wire RA_RD_MEM; //1 means different, 0 means same
wire RA_RD_WB;
wire RB_RD_MEM;
wi... | 7.487888 |
module Data_Forwarding (
input ex_mem_reg_write,
input [4:0] ex_mem_write_reg_addr, // EX MEM Register Rd
input [4:0] id_ex_instr_rs,
input [4:0] id_ex_instr_rt,
input mem_wb_reg_write,
input [4:0] mem_wb_write_reg_addr, // Mem WB Register Rd
output reg [1:0] Forward_A,
output reg [1:0... | 9.506768 |
module Data_From_L2_Buffer_Control #(
// Primary parameters
parameter L2_BUS_WIDTH = 64,
parameter BUFFER_WIDTH = 128
) (
input CLK,
input ENB,
input DATA_FROM_L2_VALID,
output DATA_FROM_L2_READY,
input DATA_FROM_L2_BUFFER_READY,
output DATA_FROM_L2_BUFFER_VALID,
output [(BU... | 8.253799 |
module data_gen (
input clk,
input rst_n,
input [DATA_WIDH-1:00] data_in[0:1024-1],
output fs,
output hs,
output [DATA_WIDH-1:00] data,
output [ 10:0] hang_cnt_out,
output [ 10:0] lie_cnt_out
);
para... | 8.555288 |
module DataGenerator #(
parameter DATA_WIDTH = 128
) (
input wire clk,
input wire i_rst,
input wire i_get_write_data,
input wire i_get_validation_data,
output wire [DATA_WIDTH-1 : 0] o_write_data,
output wire [DA... | 7.984731 |
module data_gen_tb;
initial begin
$dumpfile("data_gen_tb.vcd");
$dumpvars(0, data_gen_tb);
end
reg rst = 0;
initial begin
#20 rst = 1;
end
reg clk = 1;
always #5 clk = ~clk;
wire [7:0] data_out;
data_gen dg (
.clk(clk),
.rst(rst),
.data_out(data_out)
);
initial ... | 7.220048 |
module data_handle (
input clk,
input rst_n,
input [39:0] din, //温湿度数据
input din_vld,
output [23:0] dout, //输出到数码管数据
input busy, //串口发送忙标志
output tx_byte_vld, //数据有效标志
output [ 7:0] tx_byte //发送到串口数据
);
reg [39:0] data;
wire [30:0]... | 7.042491 |
module DATA_HAZARD (
input wire ID_EX_MemRead, // MemRead from ID/EX
input wire [`REG_ADDR_WIDTH - 1:0] ID_EX_rd, // rd from ID/EX
input wire [`REG_ADDR_WIDTH - 1:0] IF_ID_rs1, // rs1 from IF/ID
input wire [`REG_ADDR_WIDTH - 1:0] IF_ID_rs2, // rs2 from IF/ID
... | 6.696738 |
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