code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module DE0_DIGITAL_AUTO (
input CLOCK_50, // CLOCK //
output [7:0] LED, // LED //
output [33:0] GPIO_0_D, // GPIO_0, GPIO_0 connect to GPIO Default //
inout [33:0] GPIO_1_D // GPIO_0, GPIO_0 connect to GPIO Default //
);
wire VSW_R_CLRTO1;
wire VK_SEND;
wire tdo;
wire tdi;
wire tck;
... | 6.53445 |
module DE0_DIGITAL_AUTO (
input CLOCK_50, // CLOCK //
output [7:0] LED, // LED //
output [33:0] GPIO_0_D, // GPIO_0, GPIO_0 connect to GPIO Default //
output [33:0] GPIO_1_D // GPIO_0, GPIO_0 connect to GPIO Default //
);
wire VSW_R_CLRTO1;
wire VK_SEND;
wire tdo;
wire tdi;
wire tck;
... | 6.53445 |
module DE0_DIGITAL_II (
input CLOCK_50, // CLOCK //
output [7:0] LED, // LED //
inout [33:0] GPIO_0_D, // GPIO_0, GPIO_0 connect to GPIO Default //
output [33:0] GPIO_1_D // GPIO_0, GPIO_0 connect to GPIO Default //
);
assign GPIO_0_D[33:0] = 34'b11111_11111_11111_11111_11111_11111_1111;
assi... | 7.252051 |
module DE0_DIGITAL_WCLR (
input CLOCK_50, // CLOCK //
output [7:0] LED, // LED //
input [1:0] KEY, // KEY //
output [33:0] GPIO_0_D, // GPIO_0, GPIO_0 connect to GPIO Default //
output [33:0] GPIO_1_D // GPIO_0, GPIO_0 connect to GPIO Default //
);
wire CLOCK_1;
assign GPIO_0_D[33:4] = ... | 7.258007 |
module DE0_DIGITAL (
input CLOCK_50, // CLOCK //
output [7:0] LED, // LED //
input [1:0] KEY, // KEY //
output [33:0] GPIO_0_D, // GPIO_0, GPIO_0 connect to GPIO Default //
output [33:0] GPIO_1_D // GPIO_0, GPIO_0 connect to GPIO Default //
);
wire CLOCK_1;
assign GPIO_0_D[33:4] = 30'b0... | 6.630678 |
module DE0_DIGITAL (
input CLOCK_50, // CLOCK //
output [7:0] LED, // LED //
input [1:0] KEY, // KEY //
output [33:0] GPIO_0_D, // GPIO_0, GPIO_0 connect to GPIO Default //
output [33:0] GPIO_1_D // GPIO_0, GPIO_0 connect to GPIO Default //
);
wire CLOCK_1;
assign GPIO_0_D[33:4] = 30'b0... | 6.630678 |
module de0_nano
(
input CLOCK_50,
output [ 7:0] LED,
input [ 1:0] KEY,
input [ 3:0] SW,
`ifdef UNUSED
output [12:0] DRAM_ADDR,
output [ 1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:... | 6.584742 |
module de0_nano_bootrom #(
parameter DEPTH = 1024, // Memory size in bytes
parameter WB_AW = $clog2(DEPTH), // Wishbone address width
parameter MEMFILE = "../src/de0_nano_bootrom/sw/spi_uimage_loader.vh"
) // Initializatio... | 8.193388 |
module de0_nano_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output wire o_rst
);
wire locked;
reg [9:0] r;
assign o_rst = r[9];
always @(posedge o_clk)
if (locked) r <= {r[8:0], 1'b0};
else r <= 10'b1111111111;
wire [5:0] clk;
assign o_clk = clk[0... | 7.220966 |
module DE0_NANO_G_Sensor (
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// Accelerometer and EEPROM //////////
G_SENSOR_CS_N,
G_SENSOR_INT,
I2C_SCLK,
I2C_SDAT
);
//==================================... | 7.071798 |
module de0_nano_picorv32_wb_soc (
input CLOCK_50,
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_RAS_N,
output DRAM_CLK,
output DRAM_CKE,
output DRAM_CS_N,
output DRAM_WE_N,
output [1:0] DRAM_DQM,
inout [15:0] DRAM_DQ,
output EPCS_DCLK,
... | 7.298768 |
module loopback (
vjtag_byteenable,
vjtag_writedata,
vjtag_address,
sdram_readdatavalid,
sdram_waitrequest,
sdram_readdata,
vjtag_write,
vjtag_read,
rst,
clk,
leds,
vjtag_readdata,
vjtag_waitrequest,
vjtag_readdatavalid,
sdram_address,
sdram_read,
sdra... | 6.908116 |
module DE0_NANO_SOC_ADC (
//////////// ADC //////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
//////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
`ifdef ENABLE_HPS
//////////// HPS //////////
inout HP... | 7.217107 |
module DE0_NANO_SOC_Default (
//////////// ADC //////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
//////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
`ifdef ENABLE_HPS
//////////// HPS //////////
inout ... | 7.217107 |
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo... | 7.217107 |
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo... | 7.217107 |
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
... | 7.217107 |
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk... | 7.217107 |
module DE0_NANO_SOC_QSYS_nios2_qsys_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
);
input [29:0] dct_buffer;
input [3:0] dct_count;
input test_ending;
input test_has_ended;
endmodule
| 7.217107 |
module DE0_NANO_SOC_QSYS_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "DE0_NANO_SOC_QSYS_onchip_memory2.hex";
output [31:0] readdata;
input [15:0] addre... | 7.217107 |
module DE0_NANO_SOC_QSYS_pll_sys (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
... | 7.217107 |
module DE0_NANO_SOC_QSYS_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1418889131 : 0;
end... | 7.217107 |
module DE0_Nano_SOPC_altpll_sys_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys tra... | 6.845029 |
module DE0_Nano_SOPC_altpll_sys_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
DE0_Nano_SOPC_altpll_sys_dffpipe_l2c dffpipe3 (
.clock(clk),
.clrn(reset_n),
.d(din... | 6.845029 |
module DE0_Nano_SOPC_altpll_sys (
address,
areset,
c0,
c1,
c2,
c3,
c4,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata
) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
outp... | 6.845029 |
module DE0_Nano_SOPC_clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 6.845029 |
module DE0_Nano_SOPC_clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 6.845029 |
module DE0_Nano_SOPC_clock_1_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 6.845029 |
module DE0_Nano_SOPC_clock_1_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 6.845029 |
module DE0_Nano_SOPC_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0... | 6.845029 |
module DE0_Nano_SOPC_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0... | 6.845029 |
module DE0_Nano_SOPC_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_re... | 6.845029 |
module DE0_Nano_SOPC_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action... | 6.845029 |
module DE0_Nano_SOPC_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b0... | 6.845029 |
module DE0_Nano_SOPC_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [26:0] cpu_d_add... | 6.845029 |
module DE0_Nano_SOPC_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mu... | 6.845029 |
module DE0_Nano_SOPC_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm... | 6.845029 |
module DE0_Nano_SOPC_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_f... | 6.845029 |
module DE0_Nano_SOPC_cpu_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* s... | 6.845029 |
module DE0_Nano_SOPC_cpu_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
... | 6.845029 |
module DE0_Nano_SOPC_cpu_nios2_performance_monitors;
endmodule
| 6.845029 |
module DE0_Nano_SOPC_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
);
input [29:0] dct_buffer;
input [3:0] dct_count;
input test_ending;
input test_has_ended;
endmodule
| 6.845029 |
module DE0_Nano_SOPC_g_sensor_int (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
in... | 6.845029 |
module DE0_Nano_SOPC_i2c_scl (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:... | 6.845029 |
module DE0_Nano_SOPC_i2c_sda (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
);
inout bidir_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [... | 6.845029 |
module DE0_Nano_SOPC_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;... | 6.845029 |
module DE0_Nano_SOPC_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_cle... | 6.845029 |
module DE0_Nano_SOPC_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg ... | 6.845029 |
module DE0_Nano_SOPC_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
... | 6.845029 |
module DE0_Nano_SOPC_key (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [1:0] in_port;
input reset_n;
input... | 6.845029 |
module DE0_Nano_SOPC_led (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [3... | 6.845029 |
module DE0_Nano_SOPC_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [42:0] rd_data;
input clk;
i... | 6.845029 |
module DE0_Nano_SOPC_sdram_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [15:0] q;
input [15:0] data;
input [23:0] rdaddress;
input rdclken;
input [23:0] wraddress;
input wrclock;
input wren;
reg ... | 6.845029 |
module DE0_Nano_SOPC_select_i2c_clk (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
inp... | 6.845029 |
module DE0_Nano_SOPC_sw (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input ... | 6.845029 |
module DE0_Nano_SOPC_sysid (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1435703700 : 0;
endmodule
| 6.845029 |
module DE0_NANO_TEMPLATE (
//////////// CLOCK //////////
input CLOCK_50,
//////////// LED //////////
output [7:0] LED,
//////////// KEY //////////
input [1:0] KEY,
//////////// SW //////////
input [3:0] SW,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [ ... | 6.620834 |
module cpu_custom_instruction_master_arbitrator (
// inputs:
clk,
cpu_altera_nios_custom_instr_floating_point_inst_s1_done_from_sa,
cpu_altera_nios_custom_instr_floating_point_inst_s1_result_from_sa,
cpu_custom_instruction_master_multi_start,
reset_n,
// outputs:
cpu_altera_nios_custom_... | 8.157253 |
module switches_s1_irq_from_sa_clock_crossing_cpu_data_master_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" *... | 6.557409 |
module DE0_SOPC_reset_pll_io_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_... | 7.218944 |
module DE0_SOPC_reset_pll_cpu_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS... | 7.218944 |
module DE0_SOPC_reset_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_... | 7.218944 |
module mem29 (
input [11:0] a,
output reg [11:0] d
);
reg [11:0] mem[0:4095];
always @(a) begin
d = mem[a];
end
initial begin
$readmemh("../../tbe/vec_2901.vec", mem);
end
endmodule
| 6.809674 |
module for DE0 board based system
//______________________________________________________________________________
//
// External oscillator clock, feeds the PLLs
//
`define OSC_CLOCK 50000000
//
// Global system clock
//
//`define SYS_CLOCK 50000000
`define SYS_CLOCK ... | 7.111041 |
module de0_tutorial (
SW,
KEY,
CLOCK_50,
LEDG
);
input [7:0] SW;
input [0:0] KEY;
input CLOCK_50;
output [7:0] LEDG;
// Instantiate the Nios II system module generated by the SOPC Builder:
// nios_system (clk_0, reset_n, out_port_from_the_LEDs, in_port_to_the_Switches)
nios_system NiosII (... | 6.784683 |
module DE0_VGA (
clk_50,
pixel_color,
VGA_BUS_R,
VGA_BUS_G,
VGA_BUS_B,
VGA_HS,
VGA_VS,
X_pix,
Y_pix,
H_visible,
V_visible,
pixel_clk,
pixel_cnt
);
input wire clk_50;
input wire [11:0] pixel_color;
output reg [3:0] VGA_BUS_R;
output reg [3:0] VGA_BUS_G;
ou... | 7.683343 |
module DE0_VGA_Test (
clk_50,
INPUT_SWS,
INPUT_BTN,
VGA_BUS_R,
VGA_BUS_G,
VGA_BUS_B,
VGA_HS,
VGA_VS
);
input wire clk_50;
input wire [9:0] INPUT_SWS;
input wire [2:0] INPUT_BTN;
output reg [3:0] VGA_BUS_R; //Output Red
output reg [3:0] VGA_BUS_G; //Output Green
output re... | 7.320895 |
module DE0_vJTAG_DEMO (
input CLOCK_50, // CLOCK //
output [7:0] LED // LED //
);
wire VSW_R_CLRTO1;
wire VK_SEND;
wire tdo;
wire tdi;
wire tck;
wire td_a;
wire [2:0] ir_in;
wire [1024:0] out_reg;
wire VSW_R_CLEAR;
wire virtual_state_sdr;
wire virtual_state_udr;
wire virtual_state_... | 6.699653 |
module de10_nano_picorv32_wb_soc (
input CLOCK_50,
input [1:0] KEY,
output [7:0] LED,
inout [7:0] GPIO_0,
inout [7:0] GPIO_1
);
wire spi0_sck;
wire spi0_miso;
wire spi0_mosi;
wire spi0_cs0;
assign GPIO_0[0] = spi0_sck;
assign spi0_miso = GPIO_0[2];
assign GPIO_0[4] = spi0_mosi;
ass... | 7.419096 |
module wbc_mem (
input wb_clk_i,
input [15:0] wb_adr_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
output wb_ack_o
);
wire [1:0] ena;
reg [1:0] ack;
de10_ram16k... | 6.731494 |
module wbc_mem_32k (
input wb_clk_i,
input [15:0] wb_adr_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
output wb_ack_o
);
wire [1:0] ena;
reg [1:0] ack;
de10_ra... | 7.187448 |
module hello_world (
//////////// ADC CLOCK: 3.3-V LVTTL //////////
`ifdef ENABLE_ADC_CLOCK
input ADC_CLK_10,
`endif
//////////// CLOCK 1: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK1
input MAX10_CLK1_50,
`endif
//////////// CLOCK 2: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK2
input MAX10_CLK2_5... | 7.26323 |
module DE10_LITE_Reaction_Timer (
//////////// CLOCK //////////
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
//////////// SEG7 //////////
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,
//... | 7.124816 |
module DE10_LITE_Small (
//////////// CLOCK //////////
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
//////////// SEG7 //////////
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,
//////////... | 7.355927 |
module DE10_LITE_VGA_Pattern (
//////////// CLOCK //////////
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [ 1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
o... | 6.513832 |
module de10_standard (
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
input [3:0] KEY,
input [9:0] SW,
output [9:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5
);
// ... | 7.780745 |
module de1soc_pipeline_irq_mips ();
// --------------------------------------- //
// REG/WIRE declarations //
// --------------------------------------- //
wire clk;
wire clkIn = CLK100MHZ;
wire rst_n = KEY0;
wire clkEnable = ~KEY1;
wire [31:0] regData;
// ----------------------... | 7.404409 |
module wbc_mem (
input wb_clk_i,
input [15:0] wb_adr_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
output wb_ack_o
);
wire [1:0] ena;
reg [1:0] ack;
de1_ram16k ... | 6.731494 |
module wbc_mem_32k (
input wb_clk_i,
input [15:0] wb_adr_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
output wb_ack_o
);
wire [1:0] ena;
reg [1:0] ack;
de1_ram... | 7.187448 |
module DE1_blink (
// Clock Input
input [ 1:0] CLOCK_24, // 24 MHz
input [ 1:0] CLOCK_27, // 27 MHz
input CLOCK_50, // 50 MHz
input EXT_CLOCK, // External Clock
// Push Button
input [ 3:0] KEY, // Pushbutton[3:0]
// DPDT Switch
input [ 9:0]... | 7.800087 |
module ////
module de1_clk_rst (
output reg CLOCK24,
output reg CLOCK27,
output reg CLOCK50,
output reg CLOCKEXT,
output reg RST
);
//// clocks & async reset ////
initial begin
CLOCK24 = 1'b1;
#2;
forever #`HP_24 CLOCK24 = ~CLOCK24;
end
initial begin
CLOCK27 = 1'b1;
#3;
forever #`HP_27 C... | 7.094309 |
module de1_picorv32_wb_soc (
input CLOCK_50,
inout [7:0] GPIO_1,
output [1:0] sdram_ba_pad_o,
output [11:0] sdram_a_pad_o,
output sdram_cs_n_pad_o,
output sdram_ras_pad_o,
output sdram_cas_pad_o,
output sdram_we_pad_o,
inout [15:0] sdram_dq_pad_io,
output [1:0] sdram_dqm_pad_o,... | 7.628075 |
module DE1_SoC_Audio_Example (
// Inputs
CLOCK_50,
KEY,
AUD_ADCDAT,
// Bidirectionals
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
FPGA_I2C_SDAT,
// Outputs
AUD_XCK,
AUD_DACDAT,
FPGA_I2C_SCLK,
SW
);
/*****************************************************************... | 7.010442 |
module de1_soc_example (
//////////// ADC //////////
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
//////////// SEG7 //////////
output [6:0] HEX0,
... | 7.977223 |
module de1_soc_picorv32_wb_soc (
input CLOCK_50,
output [ 9:0] LEDR,
inout [35:0] GPIO_0
);
wire wb_clk;
wire wb_rst;
altera_pll_wb_clkgen #(
.INPUT_FREQUENCY ("50.0 MHz"),
.WB_CLK_FREQUENCY("24.0 MHz")
) clkgen (
.sys_clk_pad_i(CLOCK_50),
.rst_n_pad_i(1),
.wb_clk_o... | 7.353311 |
module de1_soc_proc (
///////// CLOCK2 /////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
///////// GPIO /////////
inout [35:0] GPIO_0,
///////// HEX0 /////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
ou... | 6.79067 |
module DE1_SoC_QSYS_alt_vip_avst_video_monitor_0_monitor_capture_mux_1stage_pipeline #(
parameter PAYLOAD_WIDTH = 8
) (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [PAYLOA... | 6.788578 |
module DE1_SoC_QSYS_alt_vip_cl_scl_0_scaler_core (
input wire av_st_din_valid,
input wire av_st_din_startofpacket,
input wire av_st_din_endofpacket,
input wire [224 - 1 : 0] av_st_din_data,
input wire av_st_cmd_valid,
input wire av_st_cmd_startofpacket,
input wire av_st_cmd_endofpacket,
... | 6.788578 |
module DE1_SoC_QSYS_avalon_st_adapter_001_timing_adapter_0 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [23:0] in_data,
input in_startofpacket... | 6.788578 |
module DE1_SoC_QSYS_avalon_st_adapter_data_format_adapter_0 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [23:0] in_data,
input in_startofpacke... | 6.788578 |
module DE1_SoC_QSYS_avalon_st_adapter_timing_adapter_0 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [23:0] in_data,
input in_startofpacket,
... | 6.788578 |
module DE1_SoC_QSYS_avalon_st_adapter_timing_adapter_0_fifo (
output reg [3:0] fill_level,
// Interface: clock
input clk,
input reset_n,
// Interface: data_in
output reg in_ready,
input in_valid,
input [27:0] in_data,
// Interface: dat... | 6.788578 |
module DE1_SoC_QSYS (
clk_clk,
reset_reset_n,
key_external_connection_export,
clk_sdram_clk,
pll_locked_export,
sdram_wire_addr,
sdram_wire_ba,
sdram_wire_cas_n,
sdram_wire_cke,
sdram_wire_cs_n,
sdram_wire_dq,
sdram_wire_dqm,
sdram_wire_ras_n,
sdram_wire_we_n
);
... | 6.706568 |
module DE1_SoC_QSYS_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
);
input [29:0] dct_buffer;
input [3:0] dct_count;
input test_ending;
input test_has_ended;
endmodule
| 6.788578 |
module DE1_SoC_QSYS_data_format_adapter_IN (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [23:0] in_data,
input in_startofpacket,
input ... | 6.788578 |
module DE1_SoC_QSYS_data_format_adapter_OUT (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [23:0] in_data,
input in_startofpacket,
input ... | 6.788578 |
module DE1_SoC_QSYS_epcq (
// inputs:
address,
chipselect,
clk,
read_n,
reset_n,
write_n,
writedata,
// outputs:
dataavailable,
endofpacket,
irq,
readdata,
readyfordata
);
parameter INIT_FILE = "DE1_SoC_QSYS_epcq_boot_rom.hex";
output dataavailable;
outp... | 6.788578 |
module DE1_SoC_QSYS_i2c_scl (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0... | 6.788578 |
module DE1_SoC_QSYS_i2c_sda (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
);
inout bidir_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [3... | 6.788578 |
module DE1_SoC_QSYS_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 6.788578 |
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