code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ddr_dma_0_byteenables (
// inputs:
byte_access,
doubleword,
hw,
word,
write_address,
// outputs:
write_byteenable
);
output [7:0] write_byteenable;
input byte_access;
input doubleword;
input hw;
input word;
input [26:0] write_address;
wire wa_2_is_0;
wire... | 6.538379 |
module ddr_dma_0_fifo_module_fifo_ram_module (
// inputs:
clk,
data,
rdaddress,
rdclken,
reset_n,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [63:0] q;
input clk;
input [63:0] data;
input [6:0] rdaddress;
input rdclken;
input reset_n;
input [6:0] wraddre... | 6.571633 |
module ddr_example_if0_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_dif... | 7.395123 |
module ddr_example_if0_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter R... | 7.395123 |
module ddr_example_if0_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have the... | 7.395123 |
module ddr_example_if0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
.ir_out(),
... | 7.395123 |
module ddr_example_if0_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0]... | 7.395123 |
module ddr_example_if0_p0_reset_m10 (
pll_afi_clk,
pll_write_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_resync_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input pll_afi_clk;
input p... | 7.395123 |
module ddr_example_if0_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Sin... | 7.395123 |
module ddr_example_sim_e0_if0_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pse... | 7.461371 |
module ddr_example_sim_e0_if0_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
para... | 7.461371 |
module ddr_example_sim_e0_if0_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will h... | 7.461371 |
module ddr_example_sim_e0_if0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
.ir_o... | 7.461371 |
module ddr_example_sim_e0_if0_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_N... | 7.461371 |
module ddr_example_sim_e0_if0_p0_reset_m10 (
pll_afi_clk,
pll_write_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_resync_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input pll_afi_clk;
... | 7.461371 |
module ddr_example_sim_e0_if0_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
... | 7.461371 |
module ddr_ex_lfsr8 (
clk,
reset_n,
enable,
pause,
load,
data,
ldata
);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output [8 - 1:0] data;
wire [8 - 1:0] data;
input [8 - 1:0] ldata;
reg [8 - 1:0] lfsr_data;
assign data = lfs... | 8.252623 |
module generate the write enable signal to the fifos,
// which are driven by negedge data strobe.
//*****************************************************************************
`timescale 1ns/100ps
module ddr_fifo_0_wr_en_0
(
input clk,
input reset,
input din,
output rst_dqs_delay_n,
... | 7.972229 |
module generate the write enable signal to the fifos,
// which are driven by posedge data strobe.
//*****************************************************************************
`timescale 1ns/100ps
module ddr_fifo_1_wr_en_0
(
input clk,
input rst_dqs_delay_n,
input reset,
input din,
output do... | 7.972229 |
module ddr_full_mem_model_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [31:0] q;
input [31:0] data;
input [22:0] rdaddress;
input rdclken;
input [22:0] wraddress;
input wrclock;
input wren;
reg [31:0] mem_arra... | 7.080875 |
module DDRGrayCounter #(
parameter COUNTER_WIDTH = 2
) (
output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk
);
/////////Internal connections & variables///////
reg [COUNTER_WIDT... | 7.515433 |
module DDR_I (
datain,
inclock,
dataout_h,
dataout_l
);
input [4:0] datain;
input inclock;
output [4:0] dataout_h;
output [4:0] dataout_l;
wire [4:0] sub_wire0;
wire [4:0] sub_wire1;
wire [4:0] dataout_h = sub_wire0[4:0];
wire [4:0] dataout_l = sub_wire1[4:0];
altddio_in altddio_in_... | 7.147149 |
module DDR_in_buf #(
parameter size = 16
) (
input [size-1:0] D,
output [size-1:0] Q0,
input C0,
input C1,
input CE,
input R,
input S,
output [size-1:0] Q1
);
genvar i;
generate
for (i = 0; i < size; i = i + 1) begin : ddr_gen
DDR_in_reg ddr_reg (
.D (D[i])... | 7.370046 |
module ddr_io (
clk_i,
clk_ni,
send_i,
cap_i,
dqs_i,
data_i,
data_o,
ddr_io
);
input clk_i;
input clk_ni;
input send_i;
input cap_i;
input dqs_i;
input [1:0] data_i;
output [1:0] data_o;
inout ddr_io; // synthesis attribute iob of ddr_io is true ;
wire ddr_dq_w;... | 6.679045 |
module DDR_I (
datain,
inclock,
dataout_h,
dataout_l
);
input [4:0] datain;
input inclock;
output [4:0] dataout_h;
output [4:0] dataout_l;
endmodule
| 7.147149 |
module ddr_mem_if_ddr3_emif_0_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pse... | 7.947366 |
module ddr_mem_if_ddr3_emif_0_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
para... | 7.947366 |
module ddr_mem_if_ddr3_emif_0_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will h... | 7.947366 |
module ddr_mem_if_ddr3_emif_0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
.ir_o... | 7.947366 |
module ddr_mem_if_ddr3_emif_0_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_N... | 7.947366 |
module ddr_mem_if_ddr3_emif_0_p0_reset_m10 (
pll_afi_clk,
pll_write_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_resync_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input pll_afi_clk;
... | 7.947366 |
module ddr_mem_if_ddr3_emif_0_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
... | 7.947366 |
module DDR_O (
datain_h,
datain_l,
outclock,
dataout
);
input [5:0] datain_h;
input [5:0] datain_l;
input outclock;
output [5:0] dataout;
wire [5:0] sub_wire0;
wire [5:0] dataout = sub_wire0[5:0];
altddio_out altddio_out_component (
.outclock(outclock),
.datain_h(datain_h),
... | 7.056149 |
module DDR_O (
datain_h,
datain_l,
outclock,
dataout
);
input [5:0] datain_h;
input [5:0] datain_l;
input outclock;
output [5:0] dataout;
endmodule
| 7.056149 |
module ddr_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WID... | 8.10896 |
module ddr_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values pa... | 7.31267 |
module ddr_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_s... | 7.020985 |
module ddr_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shi... | 7.001775 |
module ddr_p0_reset_m10 (
pll_afi_clk,
pll_write_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_resync_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input pll_afi_clk;
input pll_write_clk... | 7.62673 |
module ddr_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these res... | 7.62673 |
module ddr_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] wri... | 6.679193 |
module ddr_pulse78 #(
parameter clk_freq = 50000000
) (
input clk,
input reset,
//
output reg pulse78
);
//----------------------------------------------------------------------------
//
//----------------------------------------------------------------------------
`define PULSE78... | 7.770629 |
module instantiates RAM16X1 premitives. There will be
// 8 or 4 RAM16X1 instances depending on the number of data bits
// per strobe.
//*****************************************************************************
`timescale 1ns/100ps
`include "../rtl/ddr_parameters_0.v"
module ddr_ram8d_0
(
output [(`DAT... | 7.670485 |
module ddr_rd_ctrl (
input wire ui_clk,
input wire rst,
input wire rd_start,
output wire rd_req,
input wire rd_ack,
output wire rd_done,
output wire rd_busy,
output wire [ 2:0] app_cmd,
output wire app_en,
output wire [28:0] app_addr,
input wire app_rdy,
... | 7.613713 |
module ddr_rd_data_sync #(
parameter BANDWIDTH = 512,
BITWIDTH = 32
) (
input ddr_clk_afi,
input sys_clk_200M,
input sys_rst_n,
input ddr_vld_afi,
input [BANDWIDTH-1:0] ddr_data_out_afi,
input ddr_rd_en,
output reg ddr_rd_fifo_half,
... | 7.624366 |
module ddr_rd_gray_cntr (
input clk90,
input reset90,
input cnt_en,
output [3:0] rgc_gcnt
);
wire [3:0] gc_int;
reg [3:0] d_in;
reg reset90_r;
assign rgc_gcnt = gc_int;
always @(posedge clk90) reset90_r <= reset90;
always @(gc_int) begin
case (gc_int)
4'b0... | 6.538826 |
module ddr2_read_control (
input clk,
input reset,
input enable,
//ddr2 signals
input app_rdy,
output reg app_en,
output reg [2:0] app_cmd
);
parameter idle = 2'b01;
parameter read = 2'b10;
reg [1:0] state;
always @(posedge clk) begin
if (reset) begin
app_en <= 0;
... | 7.332932 |
module
*
* @copyright Copyright (c) 2014 Elphel, Inc.
*
* <b>License:</b>
*
* ddr_refresh.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any l... | 6.995459 |
module generates outputs that can directly
// connect to these pins, given a single reset signal and a clock.
//
// The module also generates a "done" status signal, to inform user system
// when reset + DDR-reinitialization is completed, and read/write operations
// to the DDR AXI interfaces may resume. The user shou... | 9.084686 |
module ddr_rpath (
input clk,
input reset,
// sample activate
input sample,
// RDATA async fifo
input rfifo_clk,
output rfifo_empty,
output [`RFIFO_RNG] rfifo_dout,
input rfifo_next,
// DDR
in... | 7.380977 |
module has instantiation DDR IOB output flip-flops,
// and an output buffer for the data mask bits.
//*****************************************************************************
`timescale 1ns/100ps
module ddr_s3_dm_iob
(
input mask_falling,
input mask_rising,
input clk90,
output ddr... | 6.954893 |
module instantiates DDR IOB output flip-flops, an
// output buffer with registered tri-state, and an input buffer
// for a single strobe/dqs bit. The DDR IOB output flip-flops
// are used to forward strobe to memory during a write. During
// a read, the output of ... | 7.670485 |
module instantiate DDR IOB output flip-flops, an
// output buffer with registered tri-state, and an input buffer
// for a single data/dq bit. The DDR IOB output flip-flops
// are used to forward data to memory during a write.
//***********************************************... | 8.225049 |
module clock_generator_ddr_wrapper (
CLKIN,
CLKFBIN,
CLKOUT0,
CLKOUT1,
CLKOUT2,
CLKOUT3,
CLKOUT4,
CLKOUT5,
CLKOUT6,
CLKOUT7,
CLKOUT8,
CLKOUT9,
CLKOUT10,
CLKOUT11,
CLKOUT12,
CLKOUT13,
CLKOUT14,
CLKOUT15,
CLKFBOUT,
RST,
LOCKED
);
input ... | 6.801817 |
module make ddr signal syncnous with user signal
* */
module ddr_sync
#(
parameter DW = 512
)
(
input rstn_i,
input clk_i,
input ddr_rd_data_valid_i,
input ddr_rdy_i,
input [ DW-1:0 ] ddr_rd_data_i,
output reg ddr_rd_data_valid_sync_o,
output reg ddr_rdy_sync_o,
output reg [ DW-1:0 ] ddr_... | 7.718916 |
module ddr_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1533005593 : 305419896;
endmodu... | 6.956242 |
module ddr_veri_ins_gen (
input clk_200M,
input rst_n,
input ddr_veri_ins_gen_vld,
output reg ddr_veri_ins_vld,
output reg [31:0] ddr_veri_ins
);
reg [15:0] conv_data_veri_cnt;
reg conv_data_veri_finish;
always @(posedge clk_200M or negedge rst_n) begin
if (!rst_n) begin
... | 7.521415 |
module ddr2_write_control (
input clk,
input reset,
input [26:0] write_addr,
input [127:0] write_data,
input write_stb,
output reg write_ack,
output reg read_enable,
//ddr2 signals
input app_rdy,
input app_wdf_rdy,
output reg app_en,
output reg app_wdf_wren,
output re... | 6.972716 |
module ddr_wr_gray_cntr (
input clk,
input reset,
input cnt_en,
output [3:0] wgc_gcnt
);
reg [3:0] d_in;
wire [3:0] gc_int;
assign wgc_gcnt = gc_int;
always @(gc_int) begin
case (gc_int)
4'b0000: d_in <= 4'b0001; //1
4'b0001: d_in <= 4'b0011; //3
4'... | 6.95706 |
module DDS (
dds_load,
dds_choice,
clk_sys,
rst_n,
state_start,
reset,
fq_ud,
w_clk,
data,
dds_para
);
input dds_load;
input dds_choice;
input clk_sys;
input rst_n;
input state_start;
output reset;
output fq_ud;
output w_clk;
output data;
input [15:0] dds_para... | 7.332298 |
module dds2k24 (
output [23:0] doxy, // DDS sequential I and Q amplitude output
input dclk, // master clock
input iq, // data tag (0 when sclk rising, 1 when sclk falling)
input rst, // reset accumulator
input [31:0] frq // frequency input - must be synchronized to SCLK
);
// internal signals... | 6.643641 |
module dds32 (
clk,
add,
sout
);
input wire clk;
input [31:0] add;
output reg [31:0] sout;
initial begin
sout <= 0;
end
always @(posedge clk) begin
sout <= sout + add;
end
endmodule
| 6.821398 |
module ddsgeneric (
input clock,
input reset,
input enable,
input enableclk,
input [31:0] phaseinc,
input signed [31:0] phaseoffset, // phase offset
output reg [17:0] outsine
);
// Always define the LUT with 32 bits
reg signed [17:0] sineLUT[0:4095];
initial begin
$readmemh(".... | 7.128936 |
module DDSs #(
parameter n = 12
) (
input nReset,
input Clk,
input [24*n-1:0] Frequency, // 2's Compliment
input [16*n-1:0] Phase, // Unsigned
input [16*n-1:0] Skew, // Unsigned
input [16*n-1:0] Amplitude, // Unsigned
input [16*n-1:0] Offset, // 2's Compliment
inp... | 7.307894 |
module mux_16x4 (
in,
sel,
out
);
input wire [15:0] in;
input wire [1:0] sel;
output wire [3:0] out;
wire [3:0] w0 = {in[15], in[11], in[7], in[3]};
mux_4x1 m0 (
.in (w0[3:0]),
.sel(sel[1:0]),
.out(out[3])
);
wire [3:0] w1 = {in[14], in[10], in[6], in[2]};
mux_4x1 m1 (
... | 7.032216 |
module mux_8x1 (
in,
sel,
out
);
input wire [7:0] in;
input wire [2:0] sel;
output wire out;
wire [1:0] bus;
mux_4x1 m1 (
.in (in[7:4]),
.sel(sel[1:0]),
.out(bus[1])
);
mux_4x1 m2 (
.in (in[3:0]),
.sel(sel[1:0]),
.out(bus[0])
);
//the input wires must ... | 7.358788 |
module mux_4x1 (
in,
sel,
out
);
input wire [3:0] in;
input wire [1:0] sel;
output reg out;
always @(in or sel)
case (sel)
2'b00: out <= in[3]; //the input wires must be parsed backwards
2'b01: out <= in[2];
2'b10: out <= in[1];
2'b11: out <= in[0];
default... | 8.288733 |
module dds (
phi_inc_i,
clk,
reset_n,
clken,
freq_mod_i,
fsin_o,
fcos_o,
out_valid
);
input [33:0] phi_inc_i;
input clk;
input reset_n;
input clken;
input [33:0] freq_mod_i;
output [9:0] fsin_o;
output [9:0] fcos_o;
output out_valid;
endmodule
| 6.624191 |
module DDS_Buffer (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [15:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`if... | 6.686494 |
module dds_cap_top_tb;
reg clk, rst, rxd;
wire txd;
always #5 clk = ~clk;
initial begin
{clk, rst, rxd} = 0;
rst = 1;
#100 rst = 0;
end
dds_cap_top dds_cap_top (
.clk(clk),
.rst(rst),
.txd(txd),
.rxd(rxd)
);
initial begin
$dumpfile("dds_cap_top_tb.vcd");
$d... | 6.956908 |
module dds_cap #(
parameter ClkFrequency = 100 * 1000 * 1000, // 100MHz
parameter aw = 12,
parameter Baud = 115200
) (
input bb_clk,
rst,
input [11:0] i1,
q1,
i2,
q2,
input if_clk,
output txd,
input rxd
);
wire [47:0] w48;
wire [1:0] rd_level;
reg dc_rd = 0;
al... | 6.706006 |
module dds_change (
rst_n,
clk_sys,
change,
dds_rst,
ddsrstin1,
ddsrstin2,
ddsrstin3,
dds_conf,
dds_confin1,
dds_confin2,
dds_confin3
);
input rst_n;
input clk_sys;
input [1:0] change;
output dds_rst;
input ddsrstin1;
input ddsrstin2;
input ddsrstin3;
reg d... | 7.339178 |
module DDS_CORDIC #(
parameter ADDRESS_WIDTH = 8,
//Bit width for phase counter and step
parameter INITIAL_STEP = 1,
//Initial step value
parameter VALUE_WIDTH = 8,
//Output value's bit width
parameter VALUETABEL_DELAY = 10
)
//The input-output delay for value table
//Parameters fixed by th... | 8.423704 |
modules
`define FILE_NAME "DDS_value_one_circle.txt"
module DDS_CORDIC_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] step;
reg set;
reg set_delay;
//Set step value flag
//_delay: wait for step increase
wire signed[7:0] value;
reg signed[7:0] value_delay;
wire zero;
time old_time, now_time;
time ga... | 7.325235 |
module dds_ctrl (
input wire clk,
input wire rst_n,
input wire [2:0] flag,
output reg [19:0] freq
// output reg [1:0] wave_sel,
// output reg [1:0] amp_sel
);
reg [19:0] freq_sin;
reg [ 1:0] function_sel;
always @(posedge clk or negedge rst_n)
if (!rst_n) function... | 7.732632 |
module dds_fifo_fir_tb ();
reg clk;
reg rst;
// Generating A 100MHz CLK to dirve module
always begin
#5 clk <= ~clk;
end
initial begin
clk <= 0;
rst <= 1;
#50 rst <= 0;
end
// -----------MAIN LOGIC ---------------------
// -------FIFO 2 AXI4 -----------------------
// Write ... | 6.81411 |
module top_dds (
input wire ref_clk,
input wire button,
//output wire [15:0] debug_bus,
output reg signed [15:0] dac_out,
output wire [7:0] leds_0_b,
output reg [7:0] leds_1_b,
output reg [7:0] leds_2_b
);
//wire clk;
wire reset;
assign reset = ~button;
reg [1:0] pipeline_state;
... | 6.71743 |
module DDS_Line #(
parameter ADDRESS_WIDTH = 8,
//Bit width for phase counter and step
parameter INITIAL_STEP = 1,
//Initial step value
parameter VALUE_WIDTH = 8,
//Output value's bit width
parameter VALUETABEL_DELAY = 3
)
//The input-output delay for value table
//Parameters fixed by the R... | 8.772553 |
modules
`define FILE_NAME "DDS_value_one_circle.txt"
module DDS_Line_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] step;
reg set;
reg set_delay;
//Set step value flag
//_delay: wait for step increase
wire signed[7:0] value;
reg signed[7:0] value_delay;
wire zero;
time old_time, now_time;
time gap;... | 7.325235 |
module DDS (
input CLK,
input RST,
input [31:0] fcw, // Frequency Controlled Word to control the frequency of the DDS output
output [15 : 0] sine, // output will use a 16-bit Reg to contain sin val
output [15 : 0] sine_2, // output will use a 16-bit Reg to contain sin val
output [15 : 0] sine... | 6.926635 |
module dds_quarter #(
parameter N = 24,
M = 12,
W = 10
) (
input clk,
input rst_n,
input [N-1:0] FreqWord,
input [N-1:0] PhaseWord,
output reg [W-1:0] q_sin
);
reg [N-1:0] acc, phase;
reg [W-2:0] sinrom[2**(M-2)-1:0];
wire [M-3:0] romaddr = phase[N-3:N-M];
reg [W-1:0] romdata;
... | 7.01973 |
modules
`define FILE_NAME "DDS_value_one_circle.txt"
module DDS_ROM_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] step;
reg set;
reg set_delay;
//Set step value flag
//_delay: wait for step increase
wire signed[7:0] value;
reg signed[7:0] value_delay;
wire zero;
time old_time, now_time;
time gap;
... | 7.325235 |
module dds_sin #(
parameter N = 24,
M = 12,
W = 10
) (
input clk,
input rst_n,
input [N-1:0] FreqWord,
output reg [W-1:0] q_sin
);
reg [N-1:0] acc;
reg [W-1:0] sinrom[2**M-1:0];
always @(posedge clk, negedge rst_n)
if (!rst_n) acc <= 0;
else acc <= acc + FreqWord;
initi... | 6.78043 |
module dds_timer (
clk_sys,
rst_n,
state_start,
state_over,
count
);
input clk_sys;
input rst_n;
input state_start;
input state_over;
output [7:0] count;
reg [7:0] count;
wire en;
assign en = state_over & state_start;
always @(posedge clk_sys) begin
if (rst_n == 1'b0) coun... | 6.518662 |
module DDS_top (
input clk,
input rst_n,
input key0_in,
input key1_in,
input key2_in,
output wire [11:0] dac_data
);
wire [ 1:0] wave_c;
wire [25:0] f_word;
wire [ 4:0] amplitude;
DDS inst_DDS (
.clk (clk),
.rst_n (rst_n),
.f_word (f_word),
.wave_c ... | 6.990403 |
module DDS_top_tb ();
reg clk;
reg rst_n;
reg key0_in;
reg key1_in;
reg key2_in;
wire [11:0] dac_data;
localparam clk_period = 20;
DDS_top inst_DDS_top (
.clk (clk),
.rst_n (rst_n),
.key0_in (key0_in),
.key1_in (key1_in),
.k... | 7.492842 |
module dds_write (
clk,
send,
cs,
sclk,
sdio,
cfr1,
cfr2,
asf,
ftw0,
pow,
ftw1,
nlscw,
plscw
);
input clk;
input [4:0] send; // triggers a data write, and indicates which data to write
input [31:0] cfr1; // CFR1 (control function register) to be sent to the D... | 7.553715 |
module DDU_tb ();
reg clk;
reg rst_n;
reg cont;
reg step;
reg mem;
reg inc;
reg dec;
reg [7:0] initaddr;
reg IR;
reg [8:0] row;
reg [9:0] col;
reg UART_TXD_IN;
wire ru;
wire [7:0] an;
wire [6:0] seg;
wire dp;
wire [7:0] ascii;
wire [15:0] led;
integer i;
integer j;
DDU my_DDU_... | 6.63284 |
module dd_buf (
datain_h,
datain_l,
outclock,
dataout
);
input [0:0] datain_h;
input [0:0] datain_l;
input outclock;
output [0:0] dataout;
wire [0:0] sub_wire0;
wire [0:0] dataout = sub_wire0[0:0];
altddio_out ALTDDIO_OUT_component (
.datain_h(datain_h),
.datain_l(datain_l),... | 7.306917 |
module dd_buf (
datain_h,
datain_l,
outclock,
dataout
);
input [0:0] datain_h;
input [0:0] datain_l;
input outclock;
output [0:0] dataout;
endmodule
| 7.306917 |
modules:
-- Function : Basic 2xDFLOP synchronizer
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- $Header$
-- $Log$
-----------------------------------------------------------------------... | 7.517477 |
module de0board (
input CLOCK_50,
output [9:0] LEDG,
output [6:0] HEX0_D,
output [6:0] HEX1_D,
output [6:0] HEX2_D,
output [6:0] HEX3_D,
output HEX0_DP,
output HEX1_DP,
output HEX2_DP,
output HEX3_DP,
input [2:0] ORG_BUTTON,
output [3:0] VGA_R,
output [3:0] VGA_G,
... | 7.375084 |
module de0cv (
input wire clk_clk, // clk.clk
input wire reset_reset_n // reset.reset_n
);
endmodule
| 7.030036 |
module DE0FlippyBit (
CLOCK_50,
SW,
VGA_R,
VGA_G,
VGA_HS,
VGA_VS,
LEDG
);
input CLOCK_50;
input [9:0] SW;
output [9:0] LEDG;
output [3:0] VGA_R, VGA_G;
output VGA_HS, VGA_VS;
wire [1200:0] framebuffer;
Display display (
.clock(CLOCK_50),
.xpos(1'b1),
.ypos... | 7.010068 |
module de0nano_iic (
input CLOCK_50,
input [1:0] KEY,
output G_SENSOR_CS_N,
inout I2C_SCLK,
inout I2C_SDAT
);
wire clk;
wire rst_n;
wire scl_in_w;
wire scl_out_w;
wire sda_in_w;
wire sda_out_w;
assign clk = CLOCK_50;
assign rst_n = KEY[0];
assign G_SE... | 8.165988 |
module DE0NANO_SOPC_reset_clk_50_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPR... | 7.229358 |
module_tck.v"
`include "cpu_jtag_debug_module_sysclk.v"
`include "cpu_jtag_debug_module_wrapper.v"
`include "cpu.v"
`include "jtag_uart.v"
`timescale 1ns / 1ps
module test_bench
;
wire clk;
reg clk_50;
wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
wire ... | 6.847645 |
module wbc_mem (
input wb_clk_i,
input [15:0] wb_adr_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
output wb_ack_o
);
wire [1:0] ena;
reg [1:0] ack;
de0_ram16k ... | 6.731494 |
module wbc_mem_32k (
input wb_clk_i,
input [15:0] wb_adr_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
output wb_ack_o
);
wire [1:0] ena;
reg [1:0] ack;
de0_ram... | 7.187448 |
module DE0_CV_top (
input wire RESET_N,
//////////////////// Clock Input ////////////////////
input wire CLOCK_50, // 50 MHz
input wire CLOCK2_50, // 50 MHz
input wire CLOCK3_50, // 50 MHz
input wire CLOCK4_50, // 50 MHz
//////////////////// Push Button ////////////////////
input ... | 6.752836 |
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