code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wr... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component_module (
// inputs:
address_... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_m... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begi... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
alw... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component_module (
// inputs:
ad... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_nios2_performance_monitors;
endmodule
| 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
);
input [29:0] dct_buffer;
input [3:0] dct_count;
input test_ending;
input test_has_ended;
endmodule
| 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "../ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_sequencer_ram.hex";
outp... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_sequencer_rom (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
reset,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "ddr3_s4_uniphy_example_if0_p0_sequencer_rom.hex";
outpu... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATEN... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastabilit... | 6.60431 |
module ddr3_s4_uniphy_example_if0_p0_write_datapath (
pll_afi_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask
);
parameter MEM_ADDRESS_WIDTH = "";
p... | 6.60431 |
module ddr3_s4_uniphy_example_sim (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
input wire oct_rdn, // oct.rdn
input wire oct_rup, // ... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy_altdll_5s51 (
dll_clk,
dll_delayctrlout
);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] wire_dll_wys_m_delayctrlout;
stratixiv_dll dll_wys_m (
.clk(dll_clk),
.delayctrlout(wire_dll_wys_m_del... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dll_memphy (
dll_clk,
dll_delayctrlout
);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] sub_wire0;
wire [5:0] dll_delayctrlout = sub_wire0[5:0];
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_dl... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_flop_mem (
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_hr_to_fr (
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_oct_control (
parallelterminationcontrol,
rdn,
rup,
seriesterminationcontrol
) /* synthesis synthesis_clearbox=1 */;
output [13:0] parallelterminationcontrol;
input [0:0] rdn;
input [0:0] rup;
output [13:0] seriestermination... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
alwa... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
r... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always ... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
w... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_nios2_performance_monitors
;
endmodule
| 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
);
input [29:0] dct_buffer;
input [3:0] dct_count;
input test_ending;
input test_has_ended;
endmodule
| 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "../ddr3_s4_uniphy_example_sim_ddr3_s4_unip... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_res... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so tha... | 6.60431 |
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_write_datapath (
pll_afi_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask
);
par... | 6.60431 |
module ddr3_s4_uniphy_example_sim_tb ();
reg clk;
reg reset_n;
ddr3_s4_uniphy_example_sim dut (
.oct_rdn(),
.oct_rup(),
.pll_ref_clk(clk),
.global_reset_n(reset_n),
.soft_reset_n(1'b1)
);
always #(10000 / 2) clk <= ~clk;
initial begin
clk <= 1'b0;
reset_n <= 0;
... | 6.60431 |
module ddr3_s4_uniphy_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diff... | 6.60431 |
module ddr3_s4_uniphy_p0_dll_memphy_altdll_5s51 (
dll_clk,
dll_delayctrlout
);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] wire_dll_wys_m_delayctrlout;
stratixiv_dll dll_wys_m (
.clk(dll_clk),
.delayctrlout(wire_dll_wys_m_delayctrlout),
.dqsupdate(),
.offsetd... | 6.60431 |
module ddr3_s4_uniphy_p0_dll_memphy (
dll_clk,
dll_delayctrlout
);
input [0:0] dll_clk;
output [5:0] dll_delayctrlout;
wire [5:0] sub_wire0;
wire [5:0] dll_delayctrlout = sub_wire0[5:0];
ddr3_s4_uniphy_p0_dll_memphy_altdll_5s51 ddr3_s4_uniphy_p0_dll_memphy_altdll_5s51_component (
.dll_clk(dll... | 6.60431 |
module ddr3_s4_uniphy_p0_flop_mem (
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = ... | 6.60431 |
module ddr3_s4_uniphy_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have thei... | 6.60431 |
module ddr3_s4_uniphy_p0_hr_to_fr (
clk,
d_h0,
d_h1,
d_l0,
d_l1,
q0,
q1
);
input clk;
input d_h0;
input d_h1;
input d_l0;
input d_l1;
output q0;
output q1;
reg q_h0;
reg q_h1;
reg q_l0;
reg q_l1;
reg q_l0_neg;
reg q_l1_neg;
always @(posedge clk) begin
q_h0 ... | 6.60431 |
module ddr3_s4_uniphy_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_out(),
... | 6.60431 |
module ddr3_s4_uniphy_p0_oct_control (
parallelterminationcontrol,
rdn,
rup,
seriesterminationcontrol
) /* synthesis synthesis_clearbox=1 */;
output [13:0] parallelterminationcontrol;
input [0:0] rdn;
input [0:0] rup;
output [13:0] seriesterminationcontrol;
`ifndef ALTERA_RESERVED_QIS
// syno... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
i... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
i... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
oci... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_b... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switc... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (fr... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty ... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg ... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component_module (
// inputs:
address_a,
... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_nios2_performance_monitors;
endmodule
| 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
);
input [29:0] dct_buffer;
input [3:0] dct_count;
input test_ending;
input test_has_ended;
endmodule
| 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "../ddr3_s4_uniphy_p0_qsys_sequencer_sequencer_ram.hex";
output [31:0] readdata;
in... | 6.60431 |
module ddr3_s4_uniphy_p0_qsys_sequencer_sequencer_rom (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
reset,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "ddr3_s4_uniphy_p0_sequencer_rom.hex";
output [31:0] readdata;
inp... | 6.60431 |
module ddr3_s4_uniphy_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] ... | 6.60431 |
module ddr3_s4_uniphy_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
reset_reques... | 6.60431 |
module ddr3_s4_uniphy_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Sinc... | 6.60431 |
module ddr3_s4_uniphy_p0_write_datapath (
pll_afi_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM... | 6.60431 |
module ddr3_sr4 #(
parameter PIPE_LEN = 7
) (
input wire clk,
input wire [3:0] shift_in,
output wire [3:0] shift_out
);
//register to hold value
reg [PIPE_LEN-1:0] d0;
reg [PIPE_LEN-1:0] d1;
reg [PIPE_LEN-1:0] d2;
reg [PIPE_LEN-1:0] d3;
always @(posedge clk) begin
d3 <= {shift_i... | 8.150444 |
module ddr3_test (
input wire clk,
input wire reset,
input wire writes_en,
input wire reads_en,
input wire calib_done,
//DDR Input Buffer (ib_)
output reg ib_re,
input wire [127:0] ib_data,
input wire [ 8:0] ib_count,
input wire ib_empty,
//DDR Output B... | 6.651291 |
module ddr4a_bridge (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [511:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [ 6:0] m0_burstcount, // ... | 6.598436 |
module ddr4a_clock_bridge (
input wire in_clk, // in_clk.clk
output wire out_clk // out_clk.clk
);
assign out_clk = in_clk;
endmodule
| 7.58998 |
module ddr4b_clock_bridge (
input wire in_clk, // in_clk.clk
output wire out_clk // out_clk.clk
);
assign out_clk = in_clk;
endmodule
| 8.03111 |
module ddr4_qsys_altera_avalon_onchip_memory2_181_zh7hrqy (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "seq_cal_soft_m20k.hex";
output [31:0... | 6.87979 |
module ddr4_qsys (
input wire global_reset_n, // global_reset_n.reset_n, Asynchronous reset causes the memory interface to be reset and recalibrated. The global reset signal applies to all memory interfaces placed within an I/O column.
input wire pll_ref_clk, // pll_ref_clk.clk, ... | 8.09949 |
module ddr4_regfile #(
`include "ddr4_user_parameter.vh"
,`include "tcu_parameter.vh"
) (
input wire clk_i,
input wire reset_n_i,
//---------------
//reg IF
input wire config_en_i,
input wire [TCU_REG_BSEL_SIZE-1:0] config_wben_i,
input wire [TCU_REG_ADDR_... | 7.671476 |
module ddram #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_clk_n,
input sys_rst,
/* Configuration interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* FML 4x64 interface */
input [`SDRAM_DEPTH-1:0] fml_adr,
input fml_s... | 7.694114 |
module ddrClkOut (
datain_h,
datain_l,
outclock,
aclr,
dataout
);
input datain_h;
input datain_l;
input outclock;
input aclr;
output dataout;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout = sub_wire1;
wire sub_wire2 = datain_h;
wire sub_wire3 = sub_w... | 6.584126 |
module ddrc_status
//#(
// parameter AXI_RD_ADDR_BITS= 12
// parameter SELECT_ADDR = 'h800, // address to select this module
// parameter SELECT_ADDR_MASK = 'h800, // address mask to select this module
// parameter BUSY_ADDR = 'hc00, // address to generate busy
// parameter BUSY_ADDR_MASK ... | 7.721792 |
module DdrIn (
datain,
inclock,
dataout_h,
dataout_l
);
input [7:0] datain;
input inclock;
output [7:0] dataout_h;
output [7:0] dataout_l;
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] dataout_h = sub_wire0[7:0];
wire [7:0] dataout_l = sub_wire1[7:0];
altddio_in altddio_in_... | 7.034685 |
module DdrIn (
datain,
inclock,
dataout_h,
dataout_l
);
input [7:0] datain;
input inclock;
output [7:0] dataout_h;
output [7:0] dataout_l;
endmodule
| 7.034685 |
module ddr (
input [7:0] datain,
input clk,
rs0,
rs1,
cr2,
rw,
reset,
output [7:0] dataout,
outbus
);
reg [7:0] store;
assign dataout = store;
assign outbus = (rw & rs0 & rs1 & cr2) ? store : 8'hzz;
always @(posedge clk) begin
if (reset & rs0 & rs1 & cr2) store <= 8'h0... | 6.566075 |
module DdrSdramIf (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_c... | 8.455278 |
module DdrSdramIf_ex_lfsr8 (
clk,
reset_n,
enable,
pause,
load,
data,
ldata
);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output [8 - 1:0] data;
wire [8 - 1:0] data;
input [8 - 1:0] ldata;
reg [8 - 1:0] lfsr_data;
assign dat... | 8.062397 |
module DdrSdramIf_full_mem_model_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [15:0] q;
input [15:0] data;
input [25:0] rdaddress;
input rdclken;
input [25:0] wraddress;
input wrclock;
input wren;
reg [15:0] m... | 7.574085 |
module ddr_arbit (
input wire ui_clk,
input wire rst,
input wire wr_req,
output wire wr_ack,
input wire wr_done,
input wire rd_req,
output wire rd_ack,
input wire rd_done
);
//parameter define
parameter IDLE = 4'b0001;
parameter ARBIT = 4'b0010;
parameter WRITE = 4'b0100;
... | 8.197333 |
module has the instantiations cal_ctl and tap_dly.
//*****************************************************************************
`timescale 1ns/100ps
(* X_CORE_INFO = "mig_v3_61_ddr2_sp3, Coregen 12.4" ,
CORE_GENERATION_INFO = "ddr2_sp3,mig_v3_61,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_widt... | 6.810555 |
module ddr_cells (
clk,
data0,
data1,
ddr
);
parameter width = 16;
input clk;
input [width-1:0] data0;
input [width-1:0] data1;
output [width-1:0] ddr;
wire rst = 0;
wire set = 0;
wire ce = 1;
`ifndef SIMULATE
genvar ix;
generate
for (ix = 0; ix < width; ix = ix + 1) begin : o... | 7.508345 |
module ddr_pll_ddr3_ip_inst (CLKI, RST, CLKOP, CLKOS, LOCK)/* synthesis syn_noprune=1 *//* synthesis NGD_DRC_MASK=1 */;// exemplar attribute ddr_pll dont_touch true
input wire CLKI;
input wire RST;
output wire CLKOP;
output wire CLKOS;
output wire LOCK;
wire REFCLK;
wire CLKOS_t;
wire ... | 6.544318 |
module ddr_pll_inst1 (CLKI, RST, CLKOP, CLKOS, LOCK)/* synthesis syn_noprune=1 *//* synthesis NGD_DRC_MASK=1 */;// exemplar attribute ddr_pll dont_touch true
input wire CLKI;
input wire RST;
output wire CLKOP;
output wire CLKOS;
output wire LOCK;
wire REFCLK;
wire CLKOS_t;
wire CLKOP_t... | 6.597141 |
module ddr_pll_inst1 (CLKI, RST, CLKOP, CLKOS, LOCK)/* synthesis syn_noprune=1 *//* synthesis NGD_DRC_MASK=1 */;// exemplar attribute ddr_pll dont_touch true
input wire CLKI;
input wire RST;
output wire CLKOP;
output wire CLKOS;
output wire LOCK;
wire REFCLK;
wire CLKOS_t;
wire CLKOP_t... | 6.597141 |
module ddr_clocking (
input clk, // External clock
input rst, // External reset
input [3:0] psda, // dynamic phase control
input [3:0] fdly, // dynamic delay of CLKOUTP
output clk_ddrMain, // Main DDR clock
output clk_ddrWrite, // 270° phase-shifted clock
output clk_d... | 6.854848 |
module ddr_controller_altera_avalon_onchip_memory2_181_fwqs2dy (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "seq_cal_soft_m20k.hex";
output ... | 6.694187 |
module ddr_control (
//////////////////////////DDR2 CONTROLLER SIGNALS
input [3:0] com,
input [13:0] add,
input DM,
ck_s,
input [2:0] AB_s, //com,data,add is the suorce input.
//AB_s the bank signal from cpu.
inout [7:0] DQ,
data,
inout DQS_DQS_m,
DQS_DQS_s,
output OD... | 6.896578 |
module ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe (
input wire clock,
input wire pre_clear,
output wire reset_out
);
parameter PIPE_DEPTH = 4;
// Declare pipeline registers.
reg [PIPE_DEPTH - 1 : 0] ams_pipe;
integer i;
// begin : RESET_PIPE
always @(posedge clock or... | 7.620717 |
module ddr_ctrl_wrapper #(
parameter ADDR_WIDTH = 25 // Memory size = 2^ADDR_WIDTH = 32MB
) (
// Internal interface
output rdy_o,
output idle_o,
input [31:0] adr_i,
output [31:0] adr_o,
input [31:0] dat_i,
output [31:0] dat_o,
input [3:0] sel_i,
input acc_i,
output ack_o,
... | 8.064914 |
module ddr_datapath #(
parameter CL = 2, // TODO
parameter WIDTH = 32,
parameter ENABLES = WIDTH / 8,
parameter MSB = WIDTH - 1,
parameter ESB = ENABLES - 1,
parameter DSB = ENABLES / 2 - 1,
parameter QSB = WIDTH / 2 - 1
) (
input clk_i,
input clk_ni,
input rst_i, // System cl... | 7.025822 |
module has the instantiations s3_dq_iob, s3_dqs_iob
// and ddr_dm modules.
//*****************************************************************************
`timescale 1ns/100ps
`include "../rtl/ddr_parameters_0.v"
module ddr_data_path_iobs_0
(
input clk,
input ... | 6.810555 |
module.
//*****************************************************************************
`timescale 1ns/100ps
`include "../rtl/ddr_parameters_0.v"
module ddr_data_write_0
(
input [((`DATA_WIDTH*2)-1):0] user_input_data,
input [((`DATA_MASK_WIDTH*2)-1):0] user_data_mask,
input ... | 6.805516 |
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