code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module DE1_SoC_QSYS_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clea... | 6.788578 |
module DE1_SoC_QSYS_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg ... | 6.788578 |
module DE1_SoC_QSYS_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
i... | 6.788578 |
module DE1_SoC_QSYS_key (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input ... | 6.788578 |
module DE1_SoC_QSYS_ledr (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [9:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [3... | 6.788578 |
module DE1_SoC_QSYS_nios2_qsys_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
);
input [29:0] dct_buffer;
input [3:0] dct_count;
input test_ending;
input test_has_ended;
endmodule
| 6.788578 |
module DE1_SoC_QSYS_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "DE1_SoC_QSYS_onchip_memory2.hex";
output [31:0] readdata;
input [14:0] address;
inpu... | 6.788578 |
module DE1_SoC_QSYS_pll (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vc... | 6.788578 |
module DE1_SoC_QSYS_pll_0 (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
ou... | 6.788578 |
module DE1_SoC_QSYS_pll_audio (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_fre... | 6.788578 |
module DE1_SoC_QSYS_pll_sys (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
o... | 6.788578 |
module DE1_SoC_QSYS_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [43:0] rd_data;
input clk;
in... | 6.788578 |
module DE1_SoC_QSYS_sdram_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [15:0] q;
input [15:0] data;
input [24:0] rdaddress;
input rdclken;
input [24:0] wraddress;
input wrclock;
input wren;
reg ... | 6.788578 |
module DE1_SoC_QSYS_sgdma_0_m_readfifo_m_readfifo (
// inputs:
clk,
m_readfifo_data,
m_readfifo_rdreq,
m_readfifo_wrreq,
reset,
// outputs:
m_readfifo_empty,
m_readfifo_full,
m_readfifo_q,
m_readfifo_usedw
);
output m_readfifo_empty;
output m_readfifo_full;
output [35... | 6.788578 |
module DE1_SoC_QSYS_sgdma_0_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
);
output command_fifo_empty;
output command_fifo_full;
output [103:0] command_fi... | 6.788578 |
module DE1_SoC_QSYS_sgdma_0_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
);
output desc_address_fifo_empty;
output desc_a... | 6.788578 |
module DE1_SoC_QSYS_sgdma_0_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
);
output status_token_fifo_empty;
output status... | 6.788578 |
module DE1_SoC_QSYS_sgdma_0_stream_fifo (
// inputs:
clk,
reset,
stream_fifo_data,
stream_fifo_rdreq,
stream_fifo_wrreq,
// outputs:
stream_fifo_empty,
stream_fifo_full,
stream_fifo_q
);
output stream_fifo_empty;
output stream_fifo_full;
output [35:0] stream_fifo_q;
inp... | 6.788578 |
module DE1_SoC_QSYS_sysid (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1400224820 : 0;
endmodule
| 6.788578 |
module DE1_SoC_QSYS_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1471403382 : 0;
endmodul... | 6.788578 |
module DE1_SoC_QSYS_td_status (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [1:0] in_port;
input reset_n;
wire clk_en;
wire [ 1:0] data_in;
wire [ 1:0] read_mux_out;
reg [31:0] r... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_fabric_demux_1stage_pipeline #(
parameter PAYLOAD_WIDTH = 8
) (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [PAYLOAD_WIDTH-1:0] in_paylo... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_fabric_h2t_channel_adap (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [7:0] in_data,
input [7:0] in_channel,
input ... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_fabric_mgmt_channel_adap (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input in_data,
input [7:0] in_channel,
// In... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_fabric_mgmt_demux_1stage_pipeline #(
parameter PAYLOAD_WIDTH = 8
) (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [PAYLOAD_WIDTH-1:0] in_... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_fabric_mgmt_demux_port_adap (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input in_data,
input in_channel,
// Interface: out
input out_r... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_fabric_mgmt_time_adap (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
input in_valid,
input in_data,
input [7:0] in_channel,
// Interface: out
output reg ... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_fabric_mux_1stage_pipeline #(
parameter PAYLOAD_WIDTH = 8
) (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [PAYLOAD_WIDTH-1:0] in_payload... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_fabric_t2h_channel_adap (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [7:0] in_data,
input [1:0] in_channel,
input ... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_link (
input wire clk_clk, // clk.clk
output wire debug_reset_reset, // debug_reset.reset
output wire [7:0] h2t_channel, // h2t.channel
input wire h2t_ready, // .ready
output wire h2t_... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_link_link_h2t_timing (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
input in_valid,
input [7:0] in_data,
// Interface: out
output reg out_valid,
output reg [7:0] ou... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_tracesys_capture_mux0_1stage_pipeline #(
parameter PAYLOAD_WIDTH = 8
) (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [PAYLOAD_WIDTH-1:0]... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_tracesys_capture_width_data_ram (
// Interface: clock
input clk,
input reset_n,
// Interface: write
input [0:0] wr_address,
input [7:0] wr_writedata,
input wr_write,
output reg wr_waitrequest,
// Int... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_tracesys_capture_width_state_ram (
// Interface: clock
input clk,
input reset_n,
// Interface: write
input [0:0] wr_address,
input [1:0] wr_writedata,
input wr_write,
output reg wr_waitrequest,
// In... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_tracesys_demux_1stage_pipeline #(
parameter PAYLOAD_WIDTH = 8
) (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [PAYLOAD_WIDTH-1:0] in_pay... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_tracesys_mem (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "DE1_SoC_QSYS_trace_system_0_tracesys_mem.hex";
output [31:0] readdata;
in... | 6.788578 |
module DE1_SoC_QSYS_trace_system_0_tracesys_mux_1stage_pipeline #(
parameter PAYLOAD_WIDTH = 8
) (
input clk,
input reset_n,
output reg in_ready,
input in_valid,
input [PAYLOAD_WIDTH-1:0] in_paylo... | 6.788578 |
module DE1_SoC_QSYS_uart_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
);
output source_rxd;
input [15:0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;
reg [7:... | 6.788578 |
module DE1_SoC_QSYS_vga_sel (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0... | 6.788578 |
module PapilioPro_Next186Soc (
input CLK_32MHZ,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HSYNC,
output VGA_VSYNC,
output SDRAM_CLK,
output SDRAM_CKE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output SDRAM_nWE,
output [1:0] S... | 6.549856 |
module DE2 (
input A,
B,
output reg [3:0] X
);
always @(*) begin
case ({
A, B
}) // tmax = 1.3ns
2'd0: X <= 4'b1110;
2'd1: X <= 4'b1101;
2'd2: X <= 4'b1011;
2'd3: X <= 4'b0111;
endcase
end
endmodule
| 6.98169 |
module PC (
branchFlag,
unconditionalBranchFlag,
zeroFlag,
PC,
pcOffsetFilled,
clock
);
input clock;
input branchFlag;
input unconditionalBranchFlag;
input zeroFlag;
input [31:0] pcOffsetFilled;
inout [31:0] PC;
reg [31:0] PC_in;
reg [31:0] PC_out;
assign PC = (PC_out != 0) ?... | 7.611651 |
module DE2i_150_QSYS_jtag_uart_log_module (
// inputs:
clk,
data,
strobe,
valid
);
input clk;
input [7:0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen("DE2i_... | 7.253393 |
module DE2i_150_QSYS_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;... | 7.253393 |
module DE2i_150_QSYS_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_cle... | 7.253393 |
module DE2i_150_QSYS_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg ... | 7.253393 |
module DE2i_150_QSYS_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
... | 7.253393 |
module DE2i_150_QSYS_nios2_qsys_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
);
input [29:0] dct_buffer;
input [3:0] dct_count;
input test_ending;
input test_has_ended;
endmodule
| 7.253393 |
module DE2i_150_QSYS_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "../DE2i_150_QSYS_onchip_memory2.hex";
output [31:0] readdata;
input [15:0] address;
input [3:0] by... | 7.253393 |
module DE2i_150_QSYS_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1369391081 : 0;
endmodu... | 7.253393 |
module DE2_115_ADDA (
//////// CLOCK //////////
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
//////// I2C for HSMC //////////
I2C_SCLK,
I2C_SDAT,
//////// HSMC //////////
ADC_CLK_A,
ADC_CLK_B,
ADC_DA,
ADC_DB,
ADC_OEB_A,
ADC_OEB_B,
ADC_OTR_A,
ADC_OTR_B,
DAC_CLK_... | 7.563892 |
module DE2_115_ADDA_TOP (
CLOCK_50,
ADC_CLK_A,
ADC_CLK_B,
ADC_DA,
ADC_DB,
ADC_OEB_A,
ADC_OEB_B,
ADC_OTR_A,
ADC_OTR_B,
DAC_CLK_A,
DAC_CLK_B,
DAC_DA,
DAC_DB,
DAC_MODE,
DAC_WRT_A,
DAC_WRT_B,
OSC_SMA_ADC4,
SMA_DAC4
);
input CLOCK_50;
output ADC_... | 7.088211 |
module de2_115_picorv32_wb_soc (
input CLOCK_50,
input KEY,
inout [1:0] GPIO_0
);
wire wb_clk;
wire wb_rst;
altpll_wb_clkgen #(
.DEVICE_FAMILY ("Cyclone IV E"),
.INPUT_FREQUENCY(50),
/* wb_clk: 24 MHz */
.WB_DIVIDE_BY (25),
.WB_MULTIPLY_BY(12)
) clkgen (
.sys... | 7.196811 |
module DE2_115_SOPC_altpll_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translat... | 7.127937 |
module DE2_115_SOPC_altpll_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
DE2_115_SOPC_altpll_dffpipe_l2c dffpipe3 (
.clock(clk),
.clrn(reset_n),
.d(din),
.... | 7.127937 |
module DE2_115_SOPC_altpll (
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata
) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
output c3;
inpu... | 7.127937 |
module DE2_115_SOPC_altpll_audio_dffpipe_l2c (
clock,
clrn,
d,
q
) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys tr... | 7.127937 |
module DE2_115_SOPC_altpll_audio_stdsync_sv6 (
clk,
din,
dout,
reset_n
) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
DE2_115_SOPC_altpll_audio_dffpipe_l2c dffpipe3 (
.clock(clk),
.clrn(reset_n),
.d(d... | 7.127937 |
module DE2_115_SOPC_altpll_audio_altpll_lo32 (
areset,
clk,
inclk
) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys tran... | 7.127937 |
module DE2_115_SOPC_altpll_audio (
address,
areset,
c0,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata
) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
input clk;
output locked;
output phasedone;
input read;... | 7.127937 |
module DE2_115_SOPC_clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
module DE2_115_SOPC_clock_1_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_1_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
module DE2_115_SOPC_clock_10_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_10_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_11_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_11_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_12_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_12_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_13_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_13_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_14_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_14_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_15_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_15_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_16_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_16_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_17_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_17_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_18_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_18_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_19_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 ... | 7.127937 |
module DE2_115_SOPC_clock_19_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-... | 7.127937 |
module DE2_115_SOPC_clock_2_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_2_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
module DE2_115_SOPC_clock_3_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_3_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
module DE2_115_SOPC_clock_4_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_4_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
module DE2_115_SOPC_clock_5_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_5_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
module DE2_115_SOPC_clock_6_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_6_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
module DE2_115_SOPC_clock_7_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_7_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
module DE2_115_SOPC_clock_8_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_8_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
module DE2_115_SOPC_clock_9_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <... | 7.127937 |
module DE2_115_SOPC_clock_9_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-t... | 7.127937 |
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