code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module debouncer (
clk,
in,
out
);
input clk;
input in;
output reg out;
reg tmp0, tmp1;
reg [7:0] counter = 0;
reg start_count = 0;
always @(posedge clk) begin
if (start_count) counter = counter + 1;
end
always @(posedge clk) begin
tmp0 <= in;
tmp1 <= ~tmp0;
out <= tm... | 6.564102 |
module debouncer_clk (
clk, //clock
rst, //reset
in, //push switch input
out
); //debouncer single pulse output
input clk;
input rst;
input in;
output out;
wire myclk; //10Hz clk
wire q, q3, qb2, qb4;
wire out2;
clk_div U0 (
/*input */ .clk (clk),
/*input */ ... | 6.87819 |
module DeBouncer_D (
clk,
boton,
state
);
input clk, boton;
wire cable1, cable2;
output state;
reg rst = 1'b0;
FlipFlopD flip1 (
.D (boton),
.clk(clk),
.rst(rst),
.Q (cable1)
);
FlipFlopD flip2 (
.D (cable1),
.clk(clk),
.rst(rst),
.Q (cable... | 7.397397 |
module debouncer_delayed (
input clk,
reset_n,
input noisy,
output debounced
);
wire timer_done, timer_reset;
debouncer_delayed_fsm FSM0 (
.clk(clk),
.reset_n(reset_n),
.noisy(noisy),
.timer_done(timer_done),
.timer_reset(timer_reset),
.debounced(debounced)
... | 7.614917 |
module debouncer_delayed_fsm (
input clk,
reset_n,
input noisy,
timer_done,
output timer_reset,
debounced
);
reg [1:0] state_reg, state_next;
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3;
// Sequential state register
always @(posedge clk, negedge reset_n) begin
if (~reset_n) state_re... | 7.614917 |
module debouncer_delayed_tb ();
reg clk, reset_n;
reg noisy;
wire debounced;
integer i;
// Instantiate unit under test
debouncer_delayed uut (
.clk(clk),
.reset_n(reset_n),
.noisy(noisy),
.debounced(debounced)
);
// Generate stimuli
// Generating a clk signal
localparam T... | 7.614917 |
module debouncer_dff (
clk_in,
resetn_in,
button_in,
button_out
);
input clk_in, resetn_in, button_in;
output button_out;
wire out_1, out_2, out_2_bar;
dff dff0 (
button_in,
clk_in,
resetn_in,
out_1
);
dff dff1 (
out_1,
clk_in,
resetn_in,
out_... | 7.057201 |
module debouncer_fpga_test (
input CLK_33MHZ_FPGA, // 33 Mhz Clock Signal Input
input FPGA_ROTARY_PUSH, // Rotary Encoder Push Button Signal (Active-high)
input [4:0] GPIO_BUTTONS, // Compass User Pushbuttons (Active-high)
input FPGA_CPU_RESET_B, // CPU_RESET Pushbutton (Active-LOW), signal shoul... | 8.111872 |
module Debouncer_KBD (
input clk,
input I,
output reg O
);
parameter COUNT_MAX = 255, COUNT_WIDTH = 8;
reg [COUNT_WIDTH-1:0] count;
reg Iv = 0;
always @(posedge clk)
if (I == Iv) begin
if (count == COUNT_MAX) O <= I;
else count <= count + 1'b1;
end else begin
count <= 'b0;
... | 6.872489 |
module debouncer_key (
input clk,
input I0,
input I1,
output reg O0,
output reg O1
);
reg [4:0] cnt0, cnt1;
reg Iv0 = 0, Iv1 = 0;
reg out0, out1;
always @(posedge (clk)) begin
if (I0 == Iv0) begin
if (cnt0 == 19) O0 <= I0;
else cnt0 <= cnt0 + 1;
end else begin
cnt... | 6.930923 |
module main (
clk,
button,
led
);
input wire clk;
input wire [3:0] button;
output reg [7:0] led;
wire [3:0] button_dbc;
initial begin
led <= 0;
end
debouncer debouncer0 (
.clk_i(clk),
.d_i (button[0]),
.d_o (button_dbc[0])
);
debouncer debouncer1 (
.clk_i(c... | 7.779865 |
module debouncer_module (
clk,
rst_n,
key_in,
key_out
);
input clk;
input rst_n;
input key_in;
output key_out;
/**************************************************/
reg key_in_dly1;
reg key_in_dly2;
reg [17:0] count_debouncer;
reg key_out_r;
reg key_out_dly1_r;
/*****************... | 6.996283 |
module debouncer_test;
reg clk = 0;
reg signal = 0;
wire out;
debouncer #(
.CLK_WAIT(5)
) test (
clk,
signal,
out
);
initial begin
$dumpfile("debouncer_test.v");
$dumpvars(0, debouncer_test);
#2 signal <= 1;
#3 signal <= 0;
#5 signal <= 1;
#10 signal <... | 7.392818 |
module: debouncer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module debouncer_text;
// Inputs
reg raw;
reg clk;
// Outputs
wire enabled;
wire disabled;
// Instantiate the Uni... | 7.439354 |
module Debounce_All (
input i_Clk,
input i_Switch_1,
input i_Switch_2,
input i_Switch_3,
input i_Switch_4,
output [3:0] o_Switches
);
Debounce_Switch Debounce_1 (
.i_Clk,
.i_Switch(i_Switch_1),
.o_Switch(o_Switches[0])
);
Debounce_Switch Debounce_2 (
.i_Clk,
... | 7.847946 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module debounce_button(
input i_clk,
input d_input,... | 7.088073 |
module: debounce_circuit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module debounce_circuit_tb;
// Inputs
reg clk;
reg reset_synchr;
// Outputs
wire reset_debounc;
// Instanti... | 7.63638 |
module debounce_ctr #(
parameter N_CYCLES = 100,
parameter W_CTR = $clog2(N_CYCLES) // let this default
) (
input wire clk,
input wire rst_n,
input wire i,
output reg o
);
reg [W_CTR-1:0] ctr;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
ctr <= {W_CTR{1'b0}... | 7.20342 |
module debounce_delay (
clock,
clear,
edge_out
);
input clock, clear;
output reg edge_out;
reg [2:0] count;
initial begin
count <= 3'd7;
edge_out <= 1'b0;
end
always @(posedge clock) begin
if (clear == 1'b0) begin
count <= 3'd0;
edge_out <= 1'b0;
end else begin
... | 7.299046 |
module debounce_delay_tb;
reg clock_tb, clear_tb;
wire edge_out_tb;
reg [7:0] counter_tb;
debounce_delay uut (
clock_tb,
clear_tb,
edge_out_tb
);
initial begin
$dumpfile("../wave_forms/debounce_delay.vcd");
$dumpvars(0, debounce_delay_tb);
counter_tb = 8'd0;
clock_tb ... | 7.299046 |
module debounce_edge_detect (
clk,
rst,
signal,
rise,
fall
);
input clk;
input rst;
input signal;
output rise;
output fall;
wire signal_debounced;
debounce signal_debouncer (
.clk(clk),
.rst(rst),
.signal_in(signal),
.signal_out(signal_debounced)
);
edge_... | 8.554037 |
module debounce_explicit (
input clk,
rst_n,
input sw,
output reg db_level,
db_tick
);
/*
debounce_explicit
(
.clk(clk),
.rst_n(rst_n),
.sw(sw),
.db_level(),
.db_tick(key_tick)
);
*/
//FSM symbolic declaration
localparam [1:0] idle = 2'b00, delay0 = 2'b01, one = 2'b10, ... | 8.501502 |
module debounce_fsmd_test (
input wire clk,
reset,
input wire [1:0] btn,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
reg [7:0] b_reg, d_reg;
wire [7:0] b_next, d_next;
reg btn_reg;
wire db_tick, btn_tick, clr;
// instantiate display circuit
disp_hex_... | 9.092985 |
module debounce_generic #(
parameter N = 1
) (
input [N-1:0] in,
input clk,
input clr,
output [N-1:0] out
);
reg [N-1:0] delay1;
reg [N-1:0] delay2;
reg [N-1:0] delay3;
always @(posedge clk or posedge clr)
if (clr == 1) begin
delay1 <= 0;
delay2 <= 0;
delay3 <= 0;
... | 6.626907 |
module debounce_input (
input clk,
input N,
input D,
input Q,
input O,
input E,
output DN,
output DD,
output DQ,
output DO,
output DE
);
reg pe_ff, ne_ff;
reg [20:0] T;
reg [ 4:0] b;
initial pe_ff = 1'b0;
initial ne_ff = 1'b0;
initial T = 21'd0;
initial... | 8.155799 |
module debounce_inputs (
clk,
in,
out
);
parameter NR = 16;
parameter NUM = 100_000;
parameter WIDTH = 32;
input wire clk;
input wire [NR-1:0] in;
output wire [NR-1:0] out;
wire [NR-1:0] in_clean;
genvar i;
generate
for (i = 0; i < NR; i = i + 1) begin : loop_block1
debouncer ... | 8.155799 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module debounce_module(
input CLK,
input RST_n,
... | 7.088073 |
module debounce_ms(
input wire clk_in,
input wire db_in,
output reg db_out
);
reg [15:0] db_shift;
always @(posedge clk_in) begin
db_shift <= `SD {db_shift[14:0],db_in};
db_out <= `SD db_shift[15] & db_shift[14] & db_shift[13] & db_shift[12] & db_shift[11];
end
endmodule
| 6.596421 |
module debounce_onepulse #(
parameter SIZE = 8
) (
input clk,
input in,
output reg out
);
reg [SIZE-1:0] DFF;
reg delay;
wire debounced;
assign debounced = &DFF;
always @(posedge clk) begin
DFF[SIZE-1:1] <= DFF[SIZE-2:0];
DFF[0] <= in;
end
always @(posedge clk) begin
if ((d... | 7.025177 |
module debounce_pb (
input clk,
input i_btn,
output reg o_state,
output o_ondn,
output o_onup
);
// sync with clock and combat metastability
reg sync_0, sync_1;
always @(posedge clk) sync_0 <= i_btn;
always @(posedge clk) sync_1 <= sync_0;
// 2.6 ms counter at 50 MHz
reg [17:0] counter... | 8.290572 |
module Debounce_Project_tb (
input i_Clk,
input i_Switch_1,
output o_LED_1
);
// Override the limit for testing
Debounce_Project_Top #(
.c_DEBOUNCE_LIMIT(10)
) Debounce_Inst (
.i_Clk,
.i_Switch_1,
.o_LED_1,
.i_Switch_3(1),
.o_LED_3(),
.io_PMOD_1()
);
end... | 8.315704 |
module Debounce_Project_Top (
input i_Clk,
input i_Switch_1,
input i_Switch_3,
output o_LED_1,
output o_LED_3,
output io_PMOD_1
);
parameter c_DEBOUNCE_LIMIT = 50000; // 2 ms at 25 MHz
wire w_Switch_1;
wire w_LED_1;
wire w_Switch_3;
// Instantiate Debounce Module
Debounce_Swit... | 8.315704 |
module debounce_pulse (
input wire clk,
input wire rst,
input wire Din,
output wire Dout
);
wire A;
reg B, C;
integer cnt;
assign A = Din;
always @(posedge clk)
if (rst == 1) begin
B <= 0;
C <= 0;
end else begin
B <= A;
C <= B;
end
assign Dout = (~C ... | 6.807373 |
module debounce_rst (
input wire clk,
input wire noisy_rst,
input wire pll_locked,
output clean_pll_rst,
output clean_async_rst
);
localparam NR_SAMPLES = 10;
localparam DELAY_CC = 100;
localparam BITS_DELAY_CC = 8; // 8 = ceil(log2(DELAY_CC));
reg [NR_SAMPLES-1:0] rst_samples;
wire rst... | 7.524317 |
module DEBOUNCE_SINGLE (
keyBounce,
clk,
keyDeBounce,
repeater
);
//кнопка одиночного запуска генерирует один импульс
//макрос для условной компиляции
//если он установлен, то debounce кнопки генерирует сигнал ___/'''\___ EVENT_NEGEDGE_BUTTON
//если он не установлен, то debounce кнопки генер... | 6.786938 |
module clockDiv (
clk,
keyBounce,
clkEn
);
input wire clk;
input wire keyBounce;
output wire clkEn;
localparam MAX = 16'h0F;
localparam MIN = 16'h00;
reg [15:0] counter = MIN;
`ifdef NEGEDGE_BUTTON
always @(posedge clk, negedge keyBounce) begin
if (keyBounce == 0) counter <= MIN;
else ... | 6.913214 |
module
module dff_en(clock, en, D, Q);
input wire clock;
input wire en;
input wire D;
`ifdef NEGEDGE_BUTTON
output reg Q = 1'd0;
always @ (posedge clock)
begin
if(en == 1)
Q <= D;
end
`else
output reg Q = 1'd1;
always @ (negedge clock)
begin
if(en == 0)
Q <= D;
end
`endif
endmodul... | 6.568656 |
module is used to debounce any switch or button coming into the FPGA.
// Does not allow the output of the switch to change unless the switch is
// steady for enough time (not toggling).
// Input i_Switch is the unstable input
// Output o_Switch is the debounced version of i_Switch
// Set the DEBOUNCE_LIMIT in i_Clk clo... | 7.051566 |
module Debounce_Switch (
input i_Clk,
input i_Switch,
output o_Switch
);
parameter c_DEBOUNCE_LIMIT = 250000; // 10ms @ 25 MHz
reg r_State = 1'b0;
reg [17:0] r_Count = 0;
always @(posedge i_Clk) begin
if ((i_Switch !== r_State) && (r_Count < c_DEBOUNCE_LIMIT)) r_Count <= r_Count + 1; // C... | 6.962805 |
module
//
//
// 100MHz clock on Basys3 -> 10ns period
// 50% duty cycle 5ns HIGH and 5ns LOW
//`timescale [time unit] / [time precision]
`timescale 10 ns / 1ns
//top module
`include "debounce_switch.v"
module debounce_switch_tb();
reg clk = 1'b0;
reg btnC = 0;
wire reset;
// 50% duty cycle clock
always #0.5 cl... | 7.447046 |
module debouncer_tb ();
// For a 100 MHz clock, set up debounce time as 10 ms
// Debounce Time = DELAY_TB/f_CLK
localparam DELAY_TB = 1_000_000;
localparam T_CLK = 10; // in ns
reg i_clk;
reg i_btn_in;
wire o_btn_db;
// UUT Instantiation
debouncer #(
.DELAY(DELAY_TB)
) uut (
.i_... | 9.051168 |
module debounce_test (
input wire clk,
reset,
input wire [1:0] btn,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
reg [7:0] b_reg, d_reg;
wire [7:0] b_next, d_next;
reg btn_reg, db_reg;
wire db_level, db_tick, dtn_tick, clr;
// instantiate 7-seg LED disp... | 9.028496 |
module debounce_toggle (
input clk,
input rst,
input button,
output reg out
);
parameter counter_width = 18;
reg [counter_width-1:0] counter;
always @(posedge rst or posedge clk) begin
if (rst) begin
counter <= 0;
out <= 0;
end else begin
if (button) begin
if (... | 7.344647 |
module debounce_up (
input wire clk,
nrst,
input wire key_in,
output reg key_out
);
localparam TIME_20MS = 1_000_000;
// localparam TIME_20MS = 1_000; // just for test
reg key_cnt;
reg [20:0] cnt;
always @(posedge clk or negedge nrst) begin
if (nrst == 0) key_cnt <= 0;
e... | 7.803346 |
module DeBounce_v (
input clk,
n_reset,
button_in, // inputs
output reg DB_out // output
);
//// ---------------- internal constants --------------
parameter N = 11; // (2^ (21-1) )/ 38 MHz = 32 ms debounce time
////---------------- internal variables ---------------
reg [N-1 : 0] q_reg;... | 7.272598 |
module debounce_v1 #( parameter
WIDTH = 1,
SAMPLING_FACTOR = 16 // 0 - sampling every clk
// 1 - sampling on clk/2
// 2 - sampling on clk/4 etc....
// only one or none should be enabled
TREAT_UNSTABLE_AS_HIGH = 0,
TREAT_UNSTABLE_AS_LOW = 0
)(
input clk,
input... | 6.953671 |
module debounce_v2 #(
parameter WIDTH = 1,
SAMPLING_FACTOR = 16, // 0 - sampling every clk
// 1 - sampling on clk/2
// 2 - sampling on clk/4 etc....
// only one or none should be enabled
TREAT_UNSTABLE_AS_HIGH = 0,
TREAT_UNSTABLE_AS_LOW = 0
) ... | 6.539139 |
module db_fsm (
input wire clk,
reset,
input wire sw,
output reg db
);
// symbolic state declaration
localparam [2:0]
zero = 3'b000,
wait1_1 = 3'b001,
wait1_2 = 3'b010,
wait1_3 = 3'b011,
one = 3'b100,
... | 7.97697 |
module debouncing_button (
input clk,
rst_n,
input sw_low, //active low
output reg db
);
localparam N = 20; //free-running counter, 2^N/50MHz=2^20/50MHz=20.9ms
//symbolic declaration for FSM
localparam [2:0] zero=3'd0,
mid0_1=3'd1,
mid0_2=3'd2,
one=3'd3,
mid1_1=3'd... | 6.81595 |
module debouncing_button_TB;
// Inputs
reg clk;
reg rst_n;
reg sw_low;
// Outputs
wire db;
// Instantiate the Unit Under Test (UUT)
early_debounce uut (
.clk(clk),
.rst_n(rst_n),
.sw_low(sw_low),
.db(db)
);
always begin //100MHz -> 2^1/100MHz= 20ns
clk = 1'b1;
... | 6.81595 |
module debouncing_down (
sp_btn,
btn,
sensor1,
sensor2,
clk,
rst_n
);
output sp_btn;
input rst_n, clk, btn, sensor1, sensor2;
reg [1:0] st;
reg down;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) st <= 2'b00;
else begin
if (btn == 0) st <= 2'b01;
if (se... | 7.717649 |
module debouncing_TEST (
input clk,
rst_n,
input sw, //active low
output [7:0] seg_out,
output [5:0] sel_out
);
reg [3:0] counter_db = 0, counter_sw = 0; //counts from 0-to-9 then wraps up
reg sw_reg = 0, db_reg = 0;
wire [3:0] counter_db_nxt, counter_sw_nxt;
wire db, tick_db, tick_sw;
... | 8.156961 |
module debouncing_up (
sp_btn,
btn,
sensor1,
sensor2,
clk,
rst_n
);
output sp_btn;
input rst_n, clk, btn, sensor1, sensor2;
reg [1:0] st;
reg up;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) st <= 2'b00;
else begin
if (btn == 0) st <= 2'b01;
if (sensor... | 7.482469 |
module xbus_ram (
clk, reset,
addr, datain, dataout,
req, write, ack, decode,
sdram_addr, sdram_data_in, sdram_data_out,
sdram_req, sdram_ready, sdram_write, sdram_done
);
input reset;
input clk;
input [21:0] addr;
input [31:0] datain;
input req;
input write;
output [31:0] ... | 7.348402 |
module xbus_tv(
clk, reset, addr,
datain, dataout,
req, ack, write, decode, interrupt,
vram_addr, vram_data_in, vram_data_out,
vram_req, vram_ready, vram_write, vram_done
);
input clk;
input reset;
input [21:0] addr; /* request address */
input [31:0] datai... | 6.917406 |
module charset_rom (
input wire clk,
input wire [3:0] digito,
input wire [2:0] scan,
input wire espacio,
output reg [7:0] bitmap
);
reg [7:0] charset[0:127];
initial $readmemh("fuente_hexadecimal_ibm.hex", charset);
always @(posedge clk) begin
if (espacio == 1'b0) bitmap <= charset[{digi... | 7.253742 |
module DebugCustomXbar (
input clock,
input reset,
input auto_out_addr,
output auto_out_ready,
input auto_out_valid
);
assign auto_out_ready = 1'h0; // @[Nodes.scala 388:84 Custom.scala 83:16]
endmodule
| 7.12416 |
module debugleds (
input mem_valid,
output reg mem_ready,
input [ 5:0] mem_addr,
input [31:0] mem_wdata,
input [ 3:0] mem_wstrb,
input clk,
input nrst,
output reg [ 7:0] leds
);
always @(posedge clk) begin
if (!nrst) begin
... | 6.82405 |
module debugm (
input wire clk,
input wire dpclk,
input wire start,
input wire stop,
input wire [15:0] debugaddr,
input wire debugreq,
output reg debugack,
output reg [31:0] debugrdata,
input wire debugwr,
input wire [31:0] debugwdata
);
parameter NSZ = 12;
localparam SIZE... | 7.162182 |
module debugreg (
input wire clk,
output wire [7:0] dbgaddr,
output wire [7:0] dbgwdata,
output reg dbgreq,
input wire dbgack
`ifdef SIMULATION
,
input wire capture,
input wire shift,
input wire drck,
input wire reset,
input wire tdi,
output wire tdo
);
`else
);
wire capture, shift, drck, reset, tdi... | 7.198981 |
module debug_1 (
data_out,
ins,
A,
B,
current_address,
ans_ex,
ans_dm,
ans_wb,
mux_sel_A,
mux_sel_B,
imm_sel,
data_in,
clk,
interrupt,
reset
);
//Output for MIPS
output [15:0] data_out;
//Outputs for verification and timing analysis
output [31:0] ins... | 6.646313 |
module: debug_1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module debug_1_tb;
// Inputs
reg [15:0] data_in;
reg clk;
reg interrupt;
reg reset;
// Outputs
wire [15:0] data_out;... | 7.620177 |
module debug_2 (
data_out,
ins,
A,
B,
current_address,
ans_ex,
ans_dm,
ans_wb,
mux_sel_A,
mux_sel_B,
imm_sel,
data_in,
clk,
interrupt,
reset
);
//module debug_2(data_out, data_in, clk, interrupt, reset);
//Output for MIPS
output [15:0] data_out;
//Ou... | 7.389996 |
module: debug_2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module debug_2_tb;
// Inputs
reg [15:0] data_in;
reg clk;
reg interrupt;
reg reset;
// Outputs
wire [15:0] data_out;... | 7.244969 |
module debug_block_dev (
clk,
reset,
bd_cmd,
bd_start,
bd_bsy,
bd_rdy,
bd_err,
bd_addr,
bd_data_in,
bd_data_out,
bd_rd,
bd_wr,
bd_iordy
);
input clk;
input reset;
input [1:0] bd_cmd;
input bd_start;
output bd_bsy;
output bd_rdy;
output bd_err;
input ... | 7.469131 |
module debug_cnt (
input wire clk,
input wire rstn,
input wire cnt_en,
output LED1,
output LED2
);
parameter CNT_WIDTH = 25;
reg [CNT_WIDTH-1:0] cnt;
reg event_detect;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt <= 0;
event_detect <= 1'b0;
end else b... | 6.57997 |
module debug_console #(
parameter BASE_ADDR = 8'h00
) (
input clk,
// PicoRV32 packed MEM Bus interface
input [68:0] mem_packed_fwd, //DEC > MEM
output [32:0] mem_packed_ret //DEC < MEM
);
// --------------------------------------------------------------
// Unpack the MEM bus
// ----------... | 7.929137 |
module debug_controller(input wire clk,
output reg [1:0] addr,
output reg [31:0] write_data,
input wire [31:0] read_data/*verilator public*/,
output reg wr_en,
output reg req,
input wire ack);
`ifdef verilator
`systemc_imp_header
void dbg_sim_term(IData val);
void start_trace();
void dbg_put(IDat... | 6.818525 |
module
//% and move the bajillion instances of the ICON/ILA to a sane setup.
module debug_core(
input phy_clk_i,
input phy_debug_clk_i,
input irs_clk_i,
input pcie_clk_i,
input [52:0] phy_debug_i,
input [52:0] pc_debug_i,
input [52:0] pcie_debug_i,
input [52:0] i2c_debug_i,
input [52:0] irs_debug_i,
... | 6.737312 |
module DebugDataSender (
input wire in_clk,
input wire in_data_valid, // data valid
input wire [39:0] data,
output wire state_out_,
output wire debug_test_out_1, // TODO: debug
output wire debug_test_out_2, // TODO: debug
input wire out_clk,
output wire sout
);
localparam EMPTY = 1... | 6.915177 |
module debug_key (
output wire cart_tran_bank0_dir,
inout wire [7:4] cart_tran_bank0,
output wire cart_tran_bank3_dir,
inout wire [7:0] cart_tran_bank3,
output wire cart_tran_pin31_dir,
inout wire cart_tran_pin31,
input wire led,
output wire button... | 9.509637 |
module debug_master_port ( /*AUTOARG*/
// Outputs
m_data_o,
m_ack_o,
m_err_o,
m_rty_o,
// Inputs
clk_i,
rst_i,
m_data_i,
m_addr_i,
m_sel_i,
m_we_i,
m_cyc_i,
m_stb_i
);
parameter dw = 32;
parameter aw = 16;
parameter sw = 4;
input clk_i, rst_i;
// Mas... | 7.147208 |
module debug_mux (
// Inputs
input clk_i
, input rst_i
, input [31:0] debug_cpu_i
, input [31:0] config_i
// Outputs
, output [ 5:0] debug_cpu_src_o
, output [31:0] monitor_o
);
reg [31:0] monitor_r;
always @* begin
monitor_r = 32'b0;
monitor_r = debug_c... | 7.257243 |
module debug_pc (
input sys_rest,
input clk_20mhz,
input clk_50mhz,
input clk_25kHz,
input rv_uart_vld,
input [63:0] rv_uart_data,
input uart_demsk_data_valid,
input [63:0] uart_demsk_data,
input [31:0] send_data,
output mif_data_vaild,
output [63:0] mif_data_out
);
r... | 6.611756 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module debug_stuff (
input clk,
input rst_n,
input rbsp_buffer_valid,
input residual_start,
input intra_pred_start,
input sum_start,
input residual_valid,
input intra_pred_valid,
input sum_valid,
output reg [63:0] counter,
output reg [63:0] buffer_invalid_counter,
output... | 6.632867 |
module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 1
//
// Info: janz@easics.be (Jan Zegers)
// http://www.easics.com
//
// Modified by Nathan Y... | 7.897638 |
module edb_simple_dual_port_ram #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 9,
parameter OUTPUT_REG = "FALSE",
parameter RAM_INIT_FILE = "ram_init_file.mem"
) (
input [(DATA_WIDTH-1):0] wdata,
input [(ADDR_WIDTH-1):0] waddr,
raddr,
input we,
wclk,
re,
rclk,
... | 8.63 |
module fifo_address_trancode_unit #(
parameter TOTAL_ADDR_WIDTH = 10,
parameter CELL_ADDR_WIDTH = 11, // Additional 1 bit to indicate overflow
parameter BUFFER_DEPTH = 5,
parameter PIPE = 1
) (
input clk,
input [TOTAL_ADDR_WIDTH - 1:0] window_addr,
input [CELL_ADDR_WIDTH - 1:0] cell_addr,
... | 7.28677 |
module trigger_unit #(
parameter WIDTH = 1,
parameter TRIGIN_EN = 0,
parameter PIPE = 0,
parameter TRIGGER_IF_MASK_ZERO = 0 /* Output High / Low when mask_in is all zero,
only apply when TRIGIN_EN is disabled
*/
) (
input clk,
resetn... | 6.677667 |
module debounced_button (
input wire clk,
input wire switch_input,
output reg switch_output
);
// state declarations
localparam [2:0]
zero = 3'b000,
wait0_1 = 3'b001,
wait1_1 = 3'b010,
wait2_1 = 3'b011,
one = 3'b100,
wait0_0 = 3'b101,
wait1_0 = 3'b110,
wait2_0 = 3'b111;
// modu... | 8.678198 |
module DEC2STCH (
CLK,
D,
LFSR,
S,
INIT
);
parameter ND = 8; // precision of decimal fraction
parameter LFSR_S = ND; // LFSR size
input [ND-1:0] D; // input probability scaled to x/256
input [LFSR_S-1:0] LFSR; // LFSR comparator value
input CLK, INIT;
output S; // stochastic bit
... | 7.162085 |
module DEC2T4 (
I0,
I1,
En,
Y0,
Y1,
Y2,
Y3
);
input I0, I1, En;
output Y0, Y1, Y2, Y3;
not i0 (I0_n, I0);
not i1 (I1_n, I1);
not i2 (En_n, En);
nor nor0 (Y0, I0, I1, En_n);
nor nor1 (Y1, I0, I1_n, En_n);
nor nor2 (Y2, I0_n, I1, En_n);
nor nor3 (Y3, I0_n, I1_n, En_n);
endmod... | 6.526048 |
module dec2to4 (
W,
Y,
En
);
input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;
always @(W or En)
case ({
En, W
})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
| 7.443137 |
module dec2to4_for_loop (
W,
Y,
En
);
input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;
integer k;
always @(W or En)
for (k = 0; k <= 3; k = k + 1)
if ((W == k) && (En == 1)) Y[k] = 1;
else Y[k] = 0;
endmodule
| 6.884024 |
module dec2to4_for_loop_tb;
reg [1:0] W;
reg En;
wire [0:3] Y;
dec2to4_for_loop d1 (
W,
Y,
En
);
initial begin
En = 1'b0;
W = 2'b00;
#10 En = 1'b1;
#10 W = 2'b01;
#10 W = 2'b10;
#10 W = 2'b11;
#20 $finish;
end
endmodule
| 6.884024 |
module dec2to4_tb;
reg [1:0] W;
reg En;
wire [0:3] Y;
dec2to4 d1 (
W,
Y,
En
);
initial begin
En = 1'b0;
W = 2'b00;
#10 En = 1'b1;
#10 W = 2'b01;
#10 W = 2'b10;
#10 W = 2'b11;
#20 $finish;
end
endmodule
| 6.880544 |
module dec2x4 (
output reg [3:0] w,
input wire [1:0] in,
input wire Ld
);
always @(Ld) begin
if (Ld) w = 4'b0001 << in;
end
endmodule
| 6.697552 |
module dec2_4 (
out,
in,
en
);
input [1:0] in;
input en;
output [3:0] out;
wire [1:0] nin;
not not0 (nin[0], in[0]);
not not1 (nin[1], in[1]);
and and0 (out[0], nin[1], nin[0], en);
and and1 (out[1], nin[1], in[0], en);
and and2 (out[2], in[1], nin[0], en);
and and3 (out[3], in[1], in[0... | 6.524883 |
module Dec38 (
input [2:0] in,
input en,
output [7:0] d
);
assign d[0] = en & ~in[2] & ~in[1] & ~in[0];
assign d[1] = en & ~in[2] & ~in[1] & in[0];
assign d[2] = en & ~in[2] & in[1] & ~in[0];
assign d[3] = en & ~in[2] & in[1] & in[0];
assign d[4] = en & in[2] & ~in[1] & ~in[0];
assign d[5] = en... | 7.130969 |
module dec38h (
output z_0,
output z_1,
output z_2,
output z_3,
output z_4,
output z_5,
output z_6,
output z_7,
input a,
input b,
input c
);
wire g;
// LEGO.NET (265) - g : tie0
assign g = 1'b0;
// LEGO.NET (266) - a : dec38gh
dec38gh a_inst (
.z_0 /* OU... | 6.688193 |
module dec38_case (
Q,
D
);
input [2:0] Q;
output [7:0] D;
reg [7:0] D;
always @(Q)
case (Q)
3'b000: D = 8'b00000000;
3'b001: D = 8'b00000001;
3'b010: D = 8'b00000010;
3'b011: D = 8'b00000100;
3'b100: D = 8'b00001000;
3'b101: D = 8'b00010000;
3'b110: ... | 8.043647 |
module T;
reg [2:0] Q;
wire [7:0] D;
dec38_case u1 (
Q,
D
);
initial begin
#800 $finish;
end
initial begin
Q = 3'b000;
#100;
Q = 3'b001;
#50;
Q = 3'b010;
#50;
Q = 3'b011;
#50;
Q = 3'b100;
#50;
Q = 3'b101;
#50;
Q = 3'b110;
#... | 6.50074 |
module dec3to8 (
input E, // enable
input [2:0] W,
output wire [6:0] Y_out
);
reg [6:0] Y;
always @(*)
if (E == 0) Y = 7'b0000000;
else
case (W)
3'b000: Y = 7'b0000001;
3'b001: Y = 7'b0000010;
3'b010: Y = 7'b0000100;
3'b011: Y = 7'b0001000;
3'b100:... | 7.162437 |
module dec47 (
in,
segment
);
input [3:0] in;
output [6:0] segment;
reg [6:0] segment;
always @(in) begin
case (in)
4'b0000: segment = 7'b0111111;
4'b0001: segment = 7'b0000110;
4'b0010: segment = 7'b1011011;
4'b0011: segment = 7'b1001111;
4'b0100: segment = 7'b110011... | 7.011275 |
module dec4_16 (
W,
En,
Y
);
input [3:0] W;
input En;
output reg [0:15] Y;
always @(W, En)
case ({
En, W
})
5'b10000: Y = 4'b0000;
5'b10001: Y = 4'b0001;
5'b10010: Y = 4'b0010;
5'b10011: Y = 4'b0011;
5'b10100: Y = 4'b0100;
5'b10101: Y = 4'b0101;
... | 6.939501 |
module dec4_16_tb;
reg [3:0] W;
reg En;
output wire [0:15] Y;
dec4_16 uut (
.W (W),
.En(En),
.Y (Y)
);
initial begin
$dumpfile("dec4_16_tb.vcd");
$dumpvars(0, dec4_16_tb);
W = 4'b0110;
En = 1;
#20;
#1 $display("W = %0b En = %0b Y = %0d", W, En, Y);
if (Y !=... | 6.707863 |
module DEC4_to_BIN16 (
input [15:0] DEC,
output wire [15:0] BIN
);
assign BIN = 1000 * DEC[15:12] + 100 * DEC[11:8] + 10 * DEC[7:4] + 1 * DEC[3:0];
endmodule
| 7.043312 |
module DEC5T32E (
I,
En,
Y
);
input [4:0] I;
input En;
output [31:0] Y;
not i0 (In0, I[0]);
not i1 (In1, I[1]);
not i2 (In2, I[2]);
not i3 (In3, I[3]);
not i4 (In4, I[4]);
not i (En_n, En);
nor y31 (Y[0], I[4], I[3], I[2], I[1], I[0], En_n);
nor y30 (Y[1], I[4], I[3], I[2], I[1], In0,... | 6.618261 |
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