code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module decoder (
cx,
d
);
input [11:0] cx;
output [6:0] d;
wire d_6_, d_4_, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208,
n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221;
a... | 7.018254 |
module decoder #(
parameter CODEWID = 2,
OUTWID = 4
) (
input [CODEWID-1:0] W,
input En,
output reg [ OUTWID-1:0] Y
);
always @(*) begin
if (En == 1)
case (W)
2'b00: Y = 'b1000;
2'b01: Y = 'b0100;
2'b10: Y = 'b0010;
2'b11: Y = 'b00... | 7.227576 |
module Decoder4to16 (
input [3:0] in,
input en,
output [15:0] dout
);
wire [3:0] notin;
not notIn0 (notin[0], in[0]);
not notIn1 (notin[1], in[1]);
not notIn2 (notin[2], in[2]);
not notIn3 (notin[3], in[3]);
wire [3:0] andgates;
and I3notI2not (andgates[0], notin[3], notin[2]);
and I3notI2... | 6.608164 |
module decoder1to2 (
o1,
o0,
i
);
output o1, o0;
input i;
wire ibar;
not inv (ibar, i);
assign o1 = i;
assign o0 = ibar;
endmodule
| 7.484927 |
module decoder1to2withEnable (
o1,
o0,
i,
enable
);
input i, enable;
output o1, o0;
not inv (ibar, i);
and and1 (o1, i, enable), and0 (o0, ibar, enable);
endmodule
| 6.833176 |
module decoder1to2withEnable_tb;
reg i, en;
wire o1, o0;
//instantiate a DUT(Device Under Test)
decoder1to2withEnable dec12wEn (
o1,
o0,
i,
en
);
initial //初始化
begin
$dumpfile("Simulation/decoder1to2withEnable.vcd");
$dumpvars;
$monitor("#", $time, " ", "en ... | 6.833176 |
module decoder1to2_tb ();
reg i;
wire o1, o0;
//module instantiation
decoder1to2 dec12 (
o1,
o0,
i
);
initial //初始化
begin
$dumpfile("Simulation/decoder1to2_tb.vcd");
$dumpvars;
i = 0;
$display("\t時間（奈秒）\t狀態");
$display($time, " ", "i = %b ==> output =... | 6.619087 |
module Decoder1_3 (
inp_Addr, // This is the input address from the Address mux
sel_s0, // Select pin that goes to slave0 this goes high when slave 0 selected
sel_s1, //Select pin that goes to slave1 this goes high when slave 1 selected
sel_s2, //Select pin that goes to slave2 this goes high when ... | 7.820743 |
module decoder1_8_16b (
In,
Out
);
// parameter N for length of inputs and outputs (to use with larger inputs/outputs)
parameter N = 16;
input [2:0] In;
output reg [7:0] Out;
always @(*) begin
case (In)
3'b000: Out = 8'b00000001;
3'b001: Out = 8'b00000010;
3'b010: Out = 8'b... | 7.9076 |
module Decoder21 (
e,
i,
y
);
input e;
input [1:0] i;
output [3:0] y;
reg [3:0] y;
always @(e, i) begin
if (e)
case (i)
2'b00: y = 4'b0001;
2'b01: y = 4'b0010;
2'b10: y = 4'b0100;
2'b11: y = 4'b1000;
default: y = 4'bx;
endcase
els... | 7.089743 |
modules: N/A
*- Description: Implementation of a 2-4 decoder module with Enable
*-
*- Example of Usage:
You can implement this code on all variants of STEPFPGA family boards.
If you want to implement this code on board and observe the logic behaviors:
- assign A[1] , A[0] to 2 on-board switches
- assign EN ... | 6.670404 |
module decoder24_tb;
reg [1:0] a;
reg en;
wire [3:0] y;
decoder24 circuit1 (
a,
en,
y
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, decoder24_tb);
a = 2'b00;
en = 1;
#20;
a = 2'b01;
#20;
a = 2'b10;
#20;
a = 2'b11;
#40;
end
initial ... | 6.702215 |
module decoder2to4 (
register,
reg_no
);
//it takes a 2bit input (the register code) and returns which register it symbolise
input [1:0] reg_no;
output [3:0] register;
reg [3:0] register;
integer i;
always @(reg_no) begin
for (i = 0; i < 4; i++) register[i] <= 0;
case (reg_no)
2'b... | 7.120389 |
module decoder2to4withEnable (
o,
i,
En
);
output [3:0] o;
input [1:0] i;
input En;
wire o3a, o2a, o1a, o0a, raw1, raw1bar, raw0, raw0bar;
//
decoder1to2
dec0 (
raw0,
raw0bar,
i[0]
),
dec1 (
raw1,
raw1bar,
i[1]
... | 6.833292 |
module decoder2to4Test;
wire [3:0] o;
reg [1:0] i;
reg En;
//測試元件實體化
decoder2to4withEnable dec24wEn (
o,
i,
En
);
initial begin
//初始化
$dumpfile("Simulation/decoder2to4withEnable_tb.vcd");
$dumpvars;
$monitor($time, " i = %2b En = %b -> o = %4b", i, En, o);
i[1] = ... | 6.611159 |
module main (
input A0_m,
A1_m,
output Y0_m,
Y1_m,
Y2_m,
Y3_m
);
decoder2to4_model deco1 (
.A0(A0_m),
.A1(A1_m),
.Y0(Y0_m),
.Y1(Y1_m),
.Y2(Y2_m),
.Y3(Y3_m)
);
endmodule
| 7.081372 |
module decoder2to4_model (
A0,
A1,
Y0,
Y1,
Y2,
Y3
);
input A0, A1;
output Y0, Y1, Y2, Y3;
wire A0, A1, Y0, Y1, Y2, Y3;
assign Y0 = (~A0) & (~A1);
assign Y1 = (~A0) & (A1);
assign Y2 = (A0) & (~A1);
assign Y3 = (A0) & (A1);
endmodule
| 7.226934 |
module decoder2x1_whole (
sel,
y,
i
);
input [1:0] sel;
output reg [3:0] y;
input i;
always @(sel, i) begin
if (sel == 2'b00) y = {i, 3'b000};
else if (sel == 2'b01) y = {1'b0, i, 2'b00};
else if (sel == 2'b10) y = {2'b00, i, 1'b0};
else if (sel == 2'b11) y = {3'b000, i};
end
e... | 6.712192 |
module decoder2x4 (
In,
en,
Y
);
input [1:0] In;
input en;
output reg [3:0] Y;
always @(In or en) begin
if (en == 1'b1) begin
case (In)
2'b00: Y = 4'b0001;
2'b01: Y = 4'b0010;
2'b10: Y = 4'b0100;
2'b11: Y = 4'b1000;
default: Y = 4'b0000;
... | 6.870913 |
module decoder2x4 (
output reg [3:0] y,
input [1:0] a
);
always @(*)
case (a)
0: y = 1;
1: y = 2;
2: y = 4;
3: y = 8;
default: y = 4'bx;
endcase
endmodule
| 6.870913 |
module decoder2x4 (
output [3:0] y,
input [1:0] a
);
function [3:0] d2x4(input [1:0] c);
case (a)
0: d2x4 = 1;
1: d2x4 = 2;
2: d2x4 = 4;
3: d2x4 = 8;
default: d2x4 = 4'bx;
endcase
endfunction
assign y = d2x4(a);
endmodule
| 6.870913 |
module decoder2x4_tb;
reg [1:0] din;
reg enable;
wire [3:0] dout;
decoder2x4 dc (
.din(din),
.enable(enable),
.dout(dout)
);
initial begin
$monitor("%b %b %b", din, enable, dout);
enable = 1'b0;
#5 enable = 1'b1;
din = 2'b00;
#5 enable = 1'b1;
din = 2'b01;
#... | 6.781831 |
module decoder2_4 (
a,
y
);
input [1:0] a;
output reg [3:0] y;
always @(*) begin
case (a)
2'd0: y = 4'b0001;
2'd1: y = 4'b0010;
2'd2: y = 4'b0100;
2'd3: y = 4'b1000;
endcase
end
endmodule
| 6.832221 |
module: Decoder2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decoder2_tb;
// Inputs
reg [1:0] select;
// Outputs
wire [3:0] out;
// Instantiate the Unit Under Test (UUT)
... | 6.926879 |
module DECODER (
out,
x,
y,
z
);
input x, y, z;
output [0:7] out;
wire x0, y0, z0;
not g1 (x0, x);
not g2 (y0, y);
not g3 (z0, z);
and g4 (out[0], x0, y0, z0);
and g5 (out[1], x0, y0, z);
and g6 (out[2], x0, y, z0);
and g7 (out[3], x0, y, z);
and g8 (out[4], x, y0, z0);
and g9 ... | 6.800244 |
module decoder3e (
n,
ena,
e
);
input [2:0] n;
input ena;
output [7:0] e;
reg [7:0] e;
always @(ena or n) begin
e = 8'b0;
e[n] = ena;
end
endmodule
| 6.907435 |
module decoder3e_test;
reg [2:0] n;
reg ena;
wire [7:0] e;
integer i;
decoder3e d3e (
n,
ena,
e
);
initial begin
#0 $display("time\tena\tn\te");
#0 ena = 1;
n = 0;
for (i = 1; i < 8; i = i + 1) begin
#1 n = i;
end
#1 ena = 0;
#1 ... | 7.339916 |
module decoder3to8 (
out,
addr
);
input [2:0] addr;
output [7:0] out;
wire not1, not2, not3;
not n3 (not3, addr[0]);
not n4 (not2, addr[1]);
not n5 (not1, addr[2]);
and and1 (out[0], not1, not2, not3);
and and2 (out[1], not1, not2, addr[0]);
and and3 (out[2], not1, addr[1], not3);
and and... | 8.532605 |
module decoder3to8_gate (
out,
x,
y,
z
);
input x, y, z;
output [7:0] out;
wire x1, y1, z1;
not n1 (x1, x);
not n2 (y1, y);
not n3 (z1, z);
and a1 (out[0], z1, x1, y1);
and a2 (out[1], z, x1, y1);
and a3 (out[2], z1, x1, y);
and a4 (out[3], z, x1, y);
and a5 (out[4], z1, x, y1);
... | 7.355926 |
module _tb;
reg [2:0] in;
wire [7:0] out;
//D.U.T. instantiation
decoder3to8 dec38 (
out,
in
);
initial begin
//初始化
$dumpfile("Simulation/decoder3to8_tb.vcd");
$dumpvars;
$monitor($time, " in=%3b -> out=%8b", in, out);
in = 3'b000;
//測試
#10 in = 3'b001;
#1... | 7.969256 |
module decoder3x8 (
output reg [7:0] YL,
input EN,
C,
B,
A
);
always @(*) begin
if (EN)
case ({
C, B, A
})
0: YL = 8'b1111_1110;
1: YL = 8'b1111_1101;
2: YL = 8'b1111_1011;
3: YL = 8'b1111_0111;
4: YL = 8'b1110_1111;
5: ... | 6.699031 |
module decoder3x8 (
output reg [7:0] YL,
input EN,
input [2:0] DIN
);
always @(*) begin
if (EN) begin
if (DIN == 0) YL = 8'b1111_1110;
else if (DIN == 1) YL = 8'b1111_1101;
else if (DIN == 2) YL = 8'b1111_1011;
else if (DIN == 3) YL = 8'b1111_0111;
else if (DIN == 4) YL =... | 6.699031 |
module decoder3x8 (
output [7:0] YL,
input EN,
C,
B,
A
);
wire [7:0] YH;
assign YH[7] = EN & (C & B & A),
YH[6] = EN & (C & B & ~A),
YH[5] = EN & (C & ~B & A),
YH[4] = EN & (C & ~B & ~A),
YH[3] = EN & (~C & B & A),
YH[2] = EN & (~C & B & ~A),
YH[1] = EN & (~C ... | 6.699031 |
module: dec3x8_code
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module dec_3x8_tb;
// Inputs
reg in0;
reg in1;
reg in2;
// Outputs
wire out0;
wire out1;
wire out2;
wire out3;... | 7.572882 |
module decoder3_8 (
a,
b,
c,
out
);
input a;
input b;
input c;
output [7:0] out;
reg [7:0] out;
always @(a, b, c) begin
case ({
a, b, c
})
3'b000: out = 8'b0000_0001;
3'b001: out = 8'b0000_0010;
3'b010: out = 8'b0000_0100;
3'b011: out = 8'b0000_1000;
... | 7.729152 |
module represents a 3-8 decoder that
we will need in order to have register selection done with the W_Adr, R_Adr
and S_Adr address inputs.
*
* Notes: This 3-8 decoder is written in behavioral verilog that uses an
always block and a case statement since a decoder will only output only
one byte dependin... | 7.311982 |
module decoder47 (
in,
segment
);
input [3:0] in;
output [6:0] segment;
reg [6:0] segment;
always @(in) begin
case (in)
4'b0000: segment = 7'b0111111;
4'b0001: segment = 7'b0000110;
4'b0010: segment = 7'b1011011;
4'b0011: segment = 7'b1001111;
4'b0100: segment = 7'b11... | 6.814172 |
module decoder4to16 (
in,
out
);
// Output signals representing the 11-bit decoded vector
output reg [15:1] out;
// Input signals representing the 15-bit input
input [3:0] in;
// Declare "reg" signals...
reg [3:0] in_bar;
// Declare "wire" signals...
// Defining constants: parameter [name_of... | 8.126959 |
module decoder4to16_tb ();
//宣告port類型
wire [3:0] in;
wire [15:0] out;
reg Rst;
reg Clk;
counterSyncPosRstWithPosEnUp4bit count (
.out(in),
.clock(Clk),
.reset(Rst),
.enable('b1)
);
//D.U.T. instantiation
decoder4to16 dut (
out,
in
);
/* 時脈產生器*/
always begin... | 7.537292 |
module decoder2_4 (
w,
en,
out
);
input [1:0] w;
input en;
output [3:0] out;
and a0 (out[0], ~w[0], ~w[1], en);
and a1 (out[1], w[0], ~w[1], en);
and a2 (out[2], ~w[0], w[1], en);
and a3 (out[3], w[0], w[1], en);
endmodule
| 6.832221 |
module decoder4_16 (
w,
en,
out
);
input [3:0] w;
input en;
output [15:0] out;
wire [3:0] enOut;
//initial encoder
decoder2_4 d1 (
w[3:2],
en,
enOut
);
//rest of encoders necessary for 16-1
decoder2_4 d2 (
w[1:0],
enOut[0],
out[3:0]
);
decoder2_4 d... | 7.409446 |
module decoder5x32 (
`ifdef USE_POWER_PINS
inout VDD,
inout VSS,
`endif
input [ 4:0] a, // 5 input lines
input en, // enable pin
output [31:0] y
);
endmodule
| 8.317174 |
module decoder6x64 (
input wire [5 : 0] x,
output wire [63 : 0] y
);
wire [15:0] y1;
wire [31:0] y2;
decoder4x16 d1 (
.x(x[3:0]),
.y(y1)
);
assign y2 = x[4] ? {y1, 16'b0} : {16'b0, y1};
assign y = x[5] ? {y2, 32'b0} : {32'b0, y2};
endmodule
| 6.898197 |
module decoder6_64 (
in,
out
);
input [5:0] in;
output [63:0] out;
wire [7:0] out_pre;
decoder3_8$ sel_decoder (
in[5:3],
out_pre,
);
wire [2:0] in_low_buffered;
bufferH16$
b1 (
in_low_buffered[2],
in[2]
),
b2 (
in_low_buffered[1],
... | 6.887949 |
module decoder7_s (
input wire [3:0] In,
output reg [6:0] Out,
input clock
);
always @(posedge clock)
//always @(*)
case (In)
4'b0000: Out = ~7'b0111111;
4'b0001: Out = ~7'b0000110;
4'b0010: Out = ~7'b1011011;
4'b0011: Out = ~7'b1001111;
4'b0100: Out = ~7'b1100110... | 7.200024 |
module decoder8 (
input [0:2] i,
input ena,
output [0:7] o
);
always @(*) begin
case ({
~ena, i
})
4'h0: o <= 8'b10000000;
4'h1: o <= 8'b01000000;
4'h2: o <= 8'b00100000;
4'h3: o <= 8'b00010000;
4'h4: o <= 8'b00001000;
4'h5: o <= 8'b00000100;
4'h6: ... | 7.066331 |
module decoderBCD (
led,
s
);
input [3:0] s;
output reg [6:0] led;
// reg [6:0]led;
always @(s)
case (s)
4'b0000: led = 7'b1000000; //0
4'b0001: led = 7'b1111001; //1
4'b0010: led = 7'b0100100; //2
4'b0011: led = 7'b0110000; //3
4'b0100: led = 7'b0011001; //4
... | 6.58151 |
module DecoderBINSN (
input wire [31:0] insn, // instrução de 32 bits
input wire EQ,
LS,
LU, // entradas de comparação
output reg pc_alu_sel // Sinal que seleciona se qual incremeto será dado ao PC
);
wire [2:0] func; // net func para auxiliar na legibilidade do código
assign func = insn[1... | 8.007071 |
module DecoderBINSN_TB ();
reg [31:0] insn; // reg que contém a instrução
reg pc_alu_sel_c; // reg que contém o valor correto da saída do módulo
reg EQ, LS, LU; // regs que contém o resultado das comparações
// net que contém o sinal de Clock proveniente do gerador
wire clk;
// net contendo a saída do... | 6.636707 |
module decoderDisplay7Segment (
out,
in
);
output [7:0] out;
input [3:0] in;
//h(currently not used)
assign out[7] = 0;
//g
assign out[6] = ~in[3] & ~in[2] & in[1] |
~in[3] & in[2] & ~in[1] |
in[3] & in[2] & in[0] |
in[1] & ~in[0] |
... | 7.383629 |
module decoderDisplay7Segment_tb;
reg [3:0] i;
wire [7:0] o;
//D.U.T. instantiation
decoderDisplay7Segment sevSegDec (
o,
i
);
//初始化
initial begin
$dumpfile("Simulation/decoderDisplay7Segment_testbench.vcd");
$dumpvars;
$monitor($time, " i=%2d -> o=%2H", i, o);
i = 4'b0000;... | 7.383629 |
module decodeReg (
input clk,
input wire [`icodeBus] icode,
input wire [`ifunBus] ifun,
input wire [`icodeBus] reg1_read_src,
reg2_read_src,
input wire [`digitsBus] valC,
input wire [`digitsBus] valP,
input wire [2:0] stat,
input wire bubble,
stall, //ǰһDzݣ൱ڽָnopһͣ(ֵָ)
//dec... | 7.286178 |
module decorderInstruction (
input wire clk_en,
input wire [31:0] dataA,
input wire [31:0] dataB,
input wire new_instruction,
output reg [ 3:0] out_opcode,
output reg [13:0] out_register,
output reg [31:0] out_data
);
reg [ 3:0] opcode;
reg [13:0] register;
reg [3... | 8.465071 |
module decodeInstruction_test ();
reg new_instruction;
reg clk_en;
reg [31:0] dataA;
reg [31:0] dataB;
wire [3:0] out_opcode;
wire [13:0] out_register;
wire [31:0] out_data;
always begin //frequência de funcionamento do módulo
clk_en = 1'b0;
#10;
clk_en = 1'b1;
#10;
end
initial b... | 7.321336 |
module decoderMult (
register,
select
);
input [2:0] select;
output [7:0] register;
wire w3, w2, w1;
wire w3N, w2N, w1N;
assign w3 = select[2];
assign w2 = select[1];
assign w1 = select[0];
not Notw3 (w3N, w3);
not Notw4 (w2N, w2);
not Notw5 (w1N, w1);
and r0 (register[0], w3N, w2N, w1... | 6.683109 |
module DecoderRegisterFile (
input [ 4:0] WriteRegister,
output [31:0] SelectRegister
);
reg [31:0] SelectRegister_reg;
always @(*) begin
case (WriteRegister)
0: SelectRegister_reg = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
1: SelectRegister_reg = 32'b0000_0000_0000_0000_0000_0000_00... | 7.101661 |
module DecoderRINSN (
input wire [31:0] insn, // instrução de 32 bits
output wire sub_sra // controle de adição/subtração e de logical/arithmetic shift
);
assign sub_sra = ((~insn[14]) & insn[13]) | insn[30];
// Está codificada no segundo bit mais signifcativo da instrução, e também deverá ser 1 caso a i... | 7.96991 |
module DECODER2 (
x,
y,
e,
d
);
input x, y, e;
output [3:0] d;
assign d[0] = e & ~x & ~y;
assign d[1] = e & ~x & y;
assign d[2] = e & x & ~y;
assign d[3] = e & x & y; //end of decoder2
endmodule
| 7.000602 |
module TSTDECODER;
reg TA, TB, TE;
wire [3:0] TD;
DECODER2 dummy (
TA,
TB,
TE,
TD
);
initial begin
{TA, TB, TE} = 3'b000;
repeat (7) #10ns{TA, TB, TE} = {TA, TB, TE} + 3'b001;
end
endmodule
| 6.621941 |
module DECODER3 (
b,
c,
a,
d
); //decoder3
input a, b, c;
output [7:0] d;
DECODER2 G1 (
b,
c,
a,
d[7:4]
); // a here works like enable for decoder2
DECODER2 G2 (
b,
c,
~a,
d[3:0]
);
endmodule
| 7.603296 |
module TSTDECODER3;
reg TA, TB, TC;
wire [7:0] TD;
DECODER3 dummy (
TB,
TC,
TA,
TD
);
initial begin
{TA, TB, TC} = 3'b000;
repeat (7) #10ns{TA, TB, TC} = {TA, TB, TC} + 3'b001;
end
endmodule
| 6.700437 |
module decoder_10b_8b (
input clk,
input rst_n,
input [9:0] data_10b_in,
input par_en,
output [7:0] data_8b_out
);
reg [3:0] temp_3b;
reg [5:0] temp_5b;
always @(posedge clk) begin
if (!rst_n) begin
temp_3b <= 4'b0000;
temp_5b <= 6'b000000;
end else ... | 6.74563 |
module decoder_12 (
input [1:0] in,
output reg [3:0] out
);
localparam WIDTH = 2'h2;
always @* begin
out = 1'h0;
out[(in)*1+0-:1] = 1'h1;
end
endmodule
| 6.591777 |
module decoder_13 (
input [1:0] in,
output reg [3:0] out
);
localparam WIDTH = 2'h2;
always @* begin
out = 1'h0;
out[(in)*1+0-:1] = 1'h1;
end
endmodule
| 6.530242 |
module decoder_1to8 (
input [2:0] select,
input data_in,
output reg [7:0] data_out
);
initial begin
data_out <= 8'b0;
end
always @(data_in or select)
case (select)
3'b000: data_out <= {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, data_in};
3'b001: data_out <= {1'b0, 1'b0, 1'b0, 1'... | 8.238085 |
module decoder_21 (
input [1:0] in,
output reg [3:0] out
);
localparam WIDTH = 2'h2;
always @* begin
out = 1'h0;
out[(in)*1+0-:1] = 1'h1;
end
endmodule
| 7.318872 |
module decoder_24_tb ();
// input port are declared in reg(register)
reg a, b, en;
// output port are declared in wire(net)
wire [3:0] y;
// instantiate design block
decoder dut (
en,
a,
b,
y
);
initial begin
$monitor("en=%b a=%b b=%b y=%b", en, a, b, y);
// with refe... | 6.967972 |
module: decoder_2_4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decoder_24__tb;
// Inputs
reg EN;
reg A1;
reg A2;
// Outputs
wire D0;
wire D1;
wire D2;
wire D3;
// I... | 7.042472 |
module decoder_28 (
input [1:0] in,
output reg [3:0] out
);
localparam WIDTH = 2'h2;
always @* begin
out = 1'h0;
out[(in)*1+0-:1] = 1'h1;
end
endmodule
| 6.673047 |
module decoder_2to4_dataflow (
input a,
input b,
output [3:0] y
);
assign y[0] = ~a & ~b;
assign y[1] = ~a & b;
assign y[2] = a & ~b;
assign y[3] = a & b;
endmodule
| 6.936735 |
module decoder_2to4_dataflow_tb ();
reg a, b;
wire [3:0] y;
integer i;
decoder_2to4_dataflow dut (
.a(a),
.b(b),
.y(y)
);
initial begin
a = 1'b0;
b = 1'b0;
end
initial begin
for (i = 0; i < 4; i = i + 1) begin
{a, b} = i;
#10;
end
end
initial $monit... | 6.936735 |
module decoder_2to4_gates (
x,
y,
f0,
f1,
f2,
f3
);
input x, y;
output f0, f1, f2, f3;
wire n1, n2;
not i1 (n1, x);
not i2 (n2, y);
and a1 (f0, n1, n2);
and a2 (f1, n1, y);
and a3 (f2, x, n2);
and a4 (f3, x, y);
endmodule
| 6.936735 |
module decoder_2to4_tb;
// signal declaration
reg test_en;
reg [2:0] test_in;
wire [3:0] out;
// instance of decoder
decoder_2to4 uut (
.en(test_en),
.in(test_in),
.bcode(out)
);
// test vector
initial begin
// disabled block
test_en = 0;
for (test_in = 0; tes... | 6.936735 |
module Decoder_2x4 (
input [1:0] In,
output [3:0] O
);
wire [1:0] In_bar;
not N0 (In_bar[0], In[0]);
not N1 (In_bar[1], In[1]);
and A0 (O[0], In_bar[1], In_bar[0]);
and A1 (O[1], In_bar[1], In[0]);
and A2 (O[2], In[1], In_bar[0]);
and A3 (O[3], In[1], In[0]);
endmodule
| 7.032747 |
module decoder_2x4_df_tb ();
reg [1:0] I;
wire [3:0] Y;
integer i;
decoder_2x4_df DUT (
Y,
I
);
initial begin
for (i = 0; i < 4; i = i + 1) begin
{I} = i;
#10;
end
end
initial begin
#100 $finish;
end
endmodule
| 6.939844 |
module decoder_2x4_en (
input [1:0] w,
input en,
output reg [0:3] y //the lsb has index 3, following the table in slides
);
always @(w, en) begin
y = 4'b0000;
if (en) // will implement a 2x1 MUX
y[w] = 1'b1;
else y = 4'b0000;
end
endmodule
| 7.924989 |
module decoder_2x4_en_tb ();
// 1) Declare local reg and wire identifiers
reg [1:0] w;
reg en;
wire [0:3] y;
// 2) Instantiate the unit under test
decoder_2x4_en uut0 (
.w (w),
.en(en),
.y (y)
);
// 3) Specify a stopwatch to stop the simulation
initial #55 $finish;
// 4) Genera... | 7.924989 |
module decoder_2x4_tb ();
// 1) Declare local reg and wire identifiers
reg [1:0] w;
wire [0:3] y;
// 2) Instantiate the unit under test
decoder_2x4 uut0 (
.w(w),
.y(y)
);
// 3) Specify a stopwatch to stop the simulation
initial #30 $finish;
// 4) Generate stimuli, using initial and al... | 7.237175 |
module decoder_2x4_df (
Y,
I
);
output [3:0] Y;
input [1:0] I;
assign Y[0] = (~I[1]) & (~I[0]);
assign Y[1] = (~I[1]) & (I[0]);
assign Y[2] = (I[1]) & (~I[0]);
assign Y[3] = (I[1]) & (I[0]);
endmodule
| 6.939844 |
module decoder_2_4 (
input wire [1:0] in,
output reg [3:0] out
);
always @(*) begin
case (in)
2'b00: begin
out = 4'b0001;
end
2'b01: begin
out = 4'b0010;
end
2'b10: begin
out = 4'b0100;
end
2'b11: begin
out = 4'b1000;
end
... | 7.833664 |
module decoder_2_4_case (
input wire [1:0] a,
input wire en,
output reg [3:0] y
);
always @*
case ({
en, a
})
3'b000, 3'b001, 3'b010, 3'b011: y = 4'b0000;
3'b100: y = 4'b0001;
3'b101: y = 4'b0010;
3'b110: y = 4'b0100;
3'b111: y = 4'b1000; // default can also b... | 9.191837 |
module decoder_2_4_str (
a,
b,
en,
y
);
input a, b, en;
output [3:0] y;
assign y[0] = (~a) & (~b) & (en);
assign y[1] = (~a) & (b) & (en);
assign y[2] = (a) & (~b) & (en);
assign y[3] = (a) & (b) & (en);
endmodule
| 6.885565 |
module decoder_2_4_str (
a,
b,
en,
y
);
input a, b, en;
output [3:0] y;
wire n1, n2;
not l1 (n1, a);
not l2 (n2, b);
and l3 (y[0], n1, n2, en);
and l4 (y[1], n1, b, en);
and l5 (y[2], a, n2, en);
and l6 (y[3], a, b, en);
endmodule
| 6.885565 |
module decoder2_4 (
Out,
In
);
input [1:0] In;
output [3:0] Out;
assign Out[0] = (~In[1] & ~In[0]),
Out[1] = (~In[1] & In[0]),
Out[2] = (In[1] & ~In[0]),
Out[3] = (In[1] & In[0]);
endmodule
| 6.832221 |
module Decoder_2_to_4_EN (
en,
x1,
x0,
z3,
z2,
z1,
z0
);
input en, x1, x0;
output z3, z2, z1, z0;
assign z3 = en & ({x1, x0} == 'B11) ? 1 : 0; // 'B11 = 3
assign z2 = en & ({x1, x0} == 'B10) ? 1 : 0; // 'B10 = 2
assign z1 = en & ({x1, x0} == 'B01) ? 1 : 0; // 'B01 = 1
assign ... | 6.672456 |
module decoder_38 (
in,
out,
en
);
input [2:0] in;
input en;
output [7:0] out;
reg [7:0] out;
always @(in or en) begin
if (en) begin
out = 8'd0;
case (in)
3'b000: out[0] = 1'b1;
3'b001: out[1] = 1'b1;
3'b010: out[2] = 1'b1;
3'b011: out[3] = 1'b... | 7.565962 |
module: decoder_38
// Revision 0.01 - File Created
////////////////////////////////////////////////////////////////////////////////
module decoder_tb;
wire [7:0] out;
reg en;
reg [2:0] in;
integer i;
decoder_38 dut(in,out,en);
initial begin
$monitor( "en=%b, in=%d, out=%b ", en, in, out);
for ( i=0; i<16; i=i+1... | 7.000162 |
module decoder_3to1 (
output [7:0] outp,
input a,
input b,
input c
);
wire abar, bbar, cbar;
not (abar, a);
not (bbar, b);
not (cbar, c);
and (outp[0], abar, bbar, cbar);
and (outp[1], abar, bbar, c);
and (outp[2], abar, b, cbar);
and (outp[3], abar, b, c);
and (outp[4], a, bbar, c... | 7.572564 |
module decoder_3to8 (
input [2:0] addr_i,
output [7:0] select_o
);
assign select_o[0] = (addr_i == 3'd0) ? 1 : 0;
assign select_o[1] = (addr_i == 3'd1) ? 1 : 0;
assign select_o[2] = (addr_i == 3'd2) ? 1 : 0;
assign select_o[3] = (addr_i == 3'd3) ? 1 : 0;
assign select_o[4] = (addr_i == 3'd4) ? 1 : 0;... | 9.361749 |
module decoder_3to8_behavioral (
input [2:0] in,
output reg [7:0] out
);
always @(*) begin
out = 8'h00;
case (in)
3'b000: out[0] = 1'b1;
3'b001: out[1] = 1'b1;
3'b010: out[2] = 1'b1;
3'b011: out[3] = 1'b1;
3'b100: out[4] = 1'b1;
3'b101: out[5] = 1'b1;
3... | 7.457559 |
module decoder_3to8_behavioural_tb ();
reg [2:0] i;
wire [7:0] y;
integer j;
decoder_3to8_behavioral dut (
.in (i),
.out(y)
);
task initialize;
begin
i = 3'b000;
end
endtask
task data_in(input [2:0] d_in);
begin
i = d_in;
end
endtask
initial ... | 7.457559 |
module decoder_3to8_dataflow_tb ();
reg [2:0] x;
wire [7:0] y;
integer k;
decoder_3to8_dataflow DUT (
.x(x),
.y(y)
);
initial begin
x = 0;
for (k = 0; k < 8; k = k + 1) #5 x = k;
#10;
end
endmodule
| 7.457559 |
module decoder_3to8_tb;
// signal declaration
reg [3:0] test_in;
wire [7:0] out;
// instance of decoder
decoder_3to8 uut (
.in(test_in),
.bcode(out)
);
// test vectors
initial begin
for (test_in = 0; test_in < 4'b1000; test_in = test_in + 1) begin
#5;
end
$stop;
end
... | 7.457559 |
module decoder_3to_tb ();
reg [2:0] in;
wire [7:0] y;
reg [2:0] i;
decoder_3to8 d1 (
in,
y
);
initial begin
for (in = 0; in < 8; in = in + 1) begin
$monitor("in=%b,y=%b", in, y);
#10;
end
end
initial #80 $finish;
endmodule
| 6.966965 |
module Decoder_3x8 (
out,
sel
);
input [3-1:0] sel;
output [8-1:0] out;
wire [3-1:0] sel_n;
not not0 (sel_n[0], sel[0]);
not not1 (sel_n[1], sel[1]);
not not2 (sel_n[2], sel[2]);
and and0 (out[0], sel_n[2], sel_n[1], sel_n[0]);
and and1 (out[1], sel_n[2], sel_n[1], sel[0]);
and and2 (out[2... | 7.682099 |
module Decoder_3x8_in_nor (
out,
sel
);
input [3-1:0] sel;
output [8-1:0] out;
wire [3-1:0] sel_n;
Not_1bit_in_nor not_1bit_in_nor_0 (
sel_n[0],
sel[0]
);
Not_1bit_in_nor not_1bit_in_nor_1 (
sel_n[1],
sel[1]
);
Not_1bit_in_nor not_1bit_in_nor_2 (
sel_n[2],
... | 6.785854 |
module NAND_Decoder_3x8 (
out,
sel
);
parameter SIZE_IN = 3;
parameter SIZE_OUT = 8;
input [SIZE_IN-1:0] sel;
output [SIZE_OUT-1:0] out;
wire [ SIZE_IN-1:0] sel_n;
wire [SIZE_OUT-1:0] out_n;
nand nand0 (sel_n[0], sel[0], sel[0]);
nand nand1 (sel_n[1], sel[1], sel[1]);
nand nand2 (sel_n[2],... | 6.563708 |
module Decoder_3x8_t;
reg [3-1:0] sel = 3'b0;
wire [8-1:0] out;
Decoder_3x8 decoder_3x8 (
.sel(sel),
.out(out)
);
initial begin
repeat (2 ** 3) begin
#1 sel = sel + 3'b1;
end
#1 $finish;
end
endmodule
| 7.552415 |
module decoder_3x8_tb;
wire [7:0] out;
reg [2:0] in;
decoder_3x8 dec (
.out(out),
.in (in)
);
initial begin
$monitor(in, out);
in = 3'b000;
end
always #20 in = in + 3'b001;
endmodule
| 7.356709 |
module decoder_3_8 (
input [2:0] sel,
output reg [7:0] res
);
always @(sel or res) begin
case (sel)
3'b000: res = 8'b00000001;
3'b001: res = 8'b00000010;
3'b010: res = 8'b00000100;
3'b011: res = 8'b00001000;
3'b100: res = 8'b00010000;
3'b101: res = 8'b00100000;
... | 9.087557 |
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