code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DEC5T32E (
I,
En,
Y
);
input [4:0] I;
input En;
output [31:0] Y;
reg [31:0] Y;
always @(En or I) begin
if (En) begin
case (I)
5'b00000: Y = 32'b00000000000000000000000000000001;
5'b00001: Y = 32'b00000000000000000000000000000010;
5'b00010: Y = 32'b000000000... | 6.618261 |
module dec5to32 (
input [4:0] enc,
output reg [31:0] dec
);
always @(*) begin
case (enc)
5'b00000: dec = 32'h0000_0001;
5'b00001: dec = 32'h0000_0002;
5'b00010: dec = 32'h0000_0004;
5'b00011: dec = 32'h0000_0008;
5'b00100: dec = 32'h0000_0010;
5'b00101: dec = 32'h000... | 7.164931 |
module BinaryDecoder (
E,
Ld,
C
);
// BUS width
parameter DATA_WIDTH = 32;
parameter OpCode_bits = 5; // 2^5 = 32 possible register selection
// Outputs
output reg [DATA_WIDTH-1:0] E; // Output E, register enable
// Inputs
input [OpCode_bits-1:0] C; // OpCode selects Register to write t... | 6.850652 |
module top_module (
input clk,
input reset,
output [3:0] q
);
always @(posedge clk)
if (reset || q == 10) q <= 1;
else q <= q + 1;
endmodule
| 7.203305 |
module decade_counter (
input clock,
input reset,
output reg [3:0] q
);
always @(posedge clock) begin
if (reset) q <= 4'b0000;
else if (q <= 4'b1000) q <= q + 1'b1;
else q <= 4'b0000;
end
endmodule
| 6.83325 |
module decade_clock_divider (
input wire clk,
input wire rst,
output reg pulse_48k = 1'b0,
output reg pulse_480k = 1'b0,
output reg pulse_4M8 = 1'b0
);
reg [9:0] divider_48k = 10'd0;
reg [6:0] divider_480k = 7'd0;
reg [3:0] divider_4M8 = 4'd0;
always @(posedge clk) begin
pulse_48k <... | 6.523828 |
module decade_counter (
en,
clk,
cnt
); //Decade counter with enable
input en, clk;
output reg [3:0] cnt;
always @(posedge clk) begin
if (en) begin
if (cnt >= 4'd0 && cnt < 4'd10) //Checking if current number lies between 0 and 10
cnt <= cnt + 4'd1; //Incrementing
else cnt <... | 6.83325 |
module decade_counter_tb ();
reg en, clk;
wire [3:0] cnt;
decade_counter uut (
.en (en),
.clk(clk),
.cnt(cnt)
);
initial begin
$dumpfile("decade_counter.vcd");
$dumpvars(0, decade_counter_tb);
en = 1'b1; //Number of bits'Binary system Value
clk = 1'b1;
#60 $finish; ... | 6.83325 |
module Apb3Gpio (
input [ 3:0] io_apb_PADDR,
input [ 0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
i... | 6.706229 |
module PipelinedMemoryBusRam (
input io_bus_cmd_valid,
output io_bus_cmd_ready,
input io_bus_cmd_payload_write,
input [31:0] io_bus_cmd_payload_address,
input [31:0] io_bus_cmd_payload_data,
input [ 3:0] io_bus_cmd_payload_mask,
output io_bus_rsp_valid,
o... | 7.802955 |
module MuraxMasterArbiter (
input io_iBus_cmd_valid,
output reg io_iBus_cmd_ready,
input [31:0] io_iBus_cmd_payload_pc,
output io_iBus_rsp_valid,
output io_iBus_rsp_payload_error,
output [31:0] io_iBus_rsp_payload_inst,
input io_d... | 7.748629 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input io_mainClk
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.82712 |
module InterruptCtrl (
input [1:0] io_inputs,
input [1:0] io_clears,
input [1:0] io_masks,
output [1:0] io_pendings,
input io_mainClk,
input resetCtrl_systemReset
);
reg [1:0] pendings;
assign io_pendings = (pendings & io_masks);
always @(posedge io_mainClk or posedge res... | 7.510624 |
module Timer (
input io_tick,
input io_clear,
input [15:0] io_limit,
output io_full,
output [15:0] io_value,
input io_mainClk,
input resetCtrl_systemReset
);
wire [15:0] _zz_counter;
wire [ 0:0] _zz_counter_1;
reg [15:0] counter;
wire l... | 6.729771 |
module BufferCC_4 (
input [15:0] io_dataIn,
output [15:0] io_dataOut,
input io_mainClk,
input resetCtrl_systemReset
);
(* async_reg = "true" *)reg [15:0] buffers_0;
(* async_reg = "true" *)reg [15:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk) begin
... | 6.634474 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input io_mainClk,
... | 7.790686 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output ... | 7.046487 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_mainClkReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 ... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_systemReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (rese... | 6.712921 |
module Apb3Gpio (
input [ 3:0] io_apb_PADDR,
input [ 0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
i... | 6.706229 |
module PipelinedMemoryBusRam (
input io_bus_cmd_valid,
output io_bus_cmd_ready,
input io_bus_cmd_payload_write,
input [31:0] io_bus_cmd_payload_address,
input [31:0] io_bus_cmd_payload_data,
input [ 3:0] io_bus_cmd_payload_mask,
output io_bus_rsp_valid,
o... | 7.802955 |
module MuraxMasterArbiter (
input io_iBus_cmd_valid,
output reg io_iBus_cmd_ready,
input [31:0] io_iBus_cmd_payload_pc,
output io_iBus_rsp_valid,
output io_iBus_rsp_payload_error,
output [31:0] io_iBus_rsp_payload_inst,
input io_d... | 7.748629 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input io_mainClk
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.82712 |
module InterruptCtrl (
input [1:0] io_inputs,
input [1:0] io_clears,
input [1:0] io_masks,
output [1:0] io_pendings,
input io_mainClk,
input resetCtrl_systemReset
);
reg [1:0] pendings;
assign io_pendings = (pendings & io_masks);
always @(posedge io_mainClk or posedge res... | 7.510624 |
module Timer (
input io_tick,
input io_clear,
input [15:0] io_limit,
output io_full,
output [15:0] io_value,
input io_mainClk,
input resetCtrl_systemReset
);
wire [15:0] _zz_counter;
wire [ 0:0] _zz_counter_1;
reg [15:0] counter;
wire l... | 6.729771 |
module BufferCC_4 (
input [15:0] io_dataIn,
output [15:0] io_dataOut,
input io_mainClk,
input resetCtrl_systemReset
);
(* async_reg = "true" *)reg [15:0] buffers_0;
(* async_reg = "true" *)reg [15:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk) begin
... | 6.634474 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input io_mainClk,
... | 7.790686 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output ... | 7.046487 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_mainClkReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 ... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_systemReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (rese... | 6.712921 |
module decapsulation2 (
input wire [17:0] message_b,
input wire [10:0] message_c,
input wire extended,
output reg [28:0] identifier
);
//tmrg default triplicate
//tmrg tmr_error false
always @(message_b, message_c, extended) begin
if(extended == 1'b0) // BASIC Datenrahmen, id sit... | 6.682486 |
module decay (
input clk,
input rst,
/* Parameters */
input [7:0] decay, // unregistered
input fs_ready,
output fs_next,
input [23:0] s_data,
output reg [23:0] d_data,
output reg d_ready,
input d_next,
/* Register for the destination address */
input [29:0] d_addr,
... | 7.118562 |
module decay_buf (
// source side
input iclk,
input [15:0] d_in,
input stb_in, // 2-cycles
input boundary, // between blocks of input strobes
input trig, // single-cycle
// readout side
input oclk,
input [5:0] read_addr,
output [15:0] d_out,
input stb_out
);
// 64 word... | 6.902879 |
module decay_shift_amount (
input clock,
input reset,
input preset,
input [3:0] decay_value,
sustain_value,
output [3:0] shift_amount,
output done
);
wire [31:0] count_up_to;
decay_rom dr0 (
clock,
decay_value,
sustain_value,
count_up_to
);
wire enable;
ra... | 7.101704 |
module Deca_Interface_Test (
input CLK_50,
input RESET, // KEY0
// LED output
output [3:0] BOARD_LEDS, // LED0..3
// PS2
input PS2_KEYBOARD_CLK,
input PS2_KEYBOARD_DAT,
input PS2_MOUSE_CLK,
input PS2_MOUSE_DAT,
// UART
input UART_RXD,
input UART_TXD, //output
... | 6.744782 |
module deca_top(
// Clocks
input wire MAX10_CLK1_50,
// Buttons
input wire [1:0] KEY,
// led
output wire [7:0] LED,
// uart
output wire UART_TXD,
input wire UART_RXD,
// sdram (sram wrapper)
output wire [12:0] DRAM_ADDR,
inout wire [15:0] DRAM_DQ, //inout tri
output wire [1:0] DRAM_B... | 7.238042 |
module dechat #(
parameter BW = 'd8,
RV = 1'b0
) (
input RSTX,
input CLK,
input DIN,
input [BW-1:0] TIMEOUT,
output reg DOUT,
output DRISE,
output DFALL
);
reg din_d1, din_d2;
always @(posedge CLK ... | 7.613127 |
module decimal2bcd #(
parameter N = 0
) (
output wire [3:0] bcd_output
);
integer counter;
reg state;
always @(posedge clk) begin
counter <= counter + 1;
if (counter >= N) begin
counter <= 0;
state <= !state;
end
end
assign LED = state;
endmodule
| 7.394396 |
module decimalTimer (
input clk,
input rst,
input en,
output reg [31:0] shiftVal
);
reg [12:0] count;
always @(posedge clk, negedge rst) begin
if (!rst) begin
count <= 0;
shiftVal <= 0;
end else begin
if (en) begin
if (count % 15 == 0) shiftVal <= shiftVal + 32'd1... | 7.168569 |
module add3 (
in,
out
);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @(in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: ou... | 7.173963 |
module DigitAdder (
A,
B,
carry_in,
out,
carry_out
);
input [3:0] A;
input [3:0] B;
input carry_in;
output reg [3:0] out;
output reg carry_out;
always @(*) begin
if (A + B + carry_in < 5'd10) begin
out[3:0] = A + B + carry_in;
carry_out = 1'b0;
end else begin
... | 6.722939 |
module decimal_adjust_adder (
clk_2,
daa_n,
dsa_n,
half_carry,
alu_cout_n,
alu_result,
adjust_in,
adjust_out
);
input clk_2; //net: 943
input daa_n; //net: 1201; decimal add adjust
input dsa_n; //net: 725; decimal subtract adjust
input half_carry; //net: 78; carry from bit 3 ... | 8.549918 |
module decimal_counter #(
parameter DELAY = 10
) (
input cp1_n,
cp2_n,
input r0_1,
r0_2,
input r9_1,
r9_2,
output qa,
qb,
qc,
qd
);
reg [2:0] count;
reg a;
initial begin
count = 3'b0;
a = 0;
end
always @(negedge cp1_n, posedge r0_1, posedge r0_2, posedg... | 6.558886 |
module decimal_counter (
A,
Overflow,
Clock,
Reset,
Direction,
Hold
); //Declares the decimal_counter module
input Clock, Reset, Direction, Hold; //Declares the Clock, Reset, Direction, Hold inputs
output Overflow; //Declares Overflow output
output [3:0] A; //Declares 4 bit output A... | 6.558886 |
module decimal_counter_17 (
input clk,
input rst,
input inc,
output reg ovf,
output reg [3:0] value
);
reg [3:0] M_val_d, M_val_q = 1'h0;
always @* begin
M_val_d = M_val_q;
value = M_val_q;
ovf = M_val_q == 4'h9 && inc;
if (inc) begin
if (M_val_q == 4'h9) begin
... | 6.558886 |
module decimal_counter_21 (
input clk,
input rst,
input inc,
output reg ovf,
output reg [3:0] value
);
reg [3:0] M_val_d, M_val_q = 1'h0;
always @* begin
M_val_d = M_val_q;
value = M_val_q;
ovf = M_val_q == 4'h9 && inc;
if (inc) begin
if (M_val_q == 4'h9) begin
... | 6.558886 |
module decimal_counter_22 (
input clk,
input rst,
input inc,
output reg ovf,
output reg [3:0] value
);
reg [3:0] M_val_d, M_val_q = 1'h0;
always @* begin
M_val_d = M_val_q;
value = M_val_q;
ovf = M_val_q == 4'h9 && inc;
if (inc) begin
if (M_val_q == 4'h9) begin
... | 6.558886 |
module decimal_counter_23 (
input clk,
input rst,
input inc,
output reg ovf,
output reg [3:0] value
);
reg [3:0] M_val_d, M_val_q = 1'h0;
always @* begin
M_val_d = M_val_q;
value = M_val_q;
ovf = M_val_q == 4'h9 && inc;
if (inc) begin
if (M_val_q == 4'h9) begin
... | 6.558886 |
module decimal_counter_28 (
input clk,
input rst,
input inc,
output reg ovf,
output reg [4:0] value
);
reg [3:0] M_val_d, M_val_q = 1'h0;
always @* begin
M_val_d = M_val_q;
value = M_val_q;
ovf = M_val_q == 4'h9 && inc;
if (inc) begin
if (M_val_q == 4'h9) begin
... | 6.558886 |
module Decimal_Decoder (
A,
Y
); //defines decimal decoder module
input [3:0] A; //defines a 4 bit input for A
output [9:0] Y; //defines a 10 bit output for Y
assign Y[0] = A[3] | A[2] | A[1] | A[0]; //assigns POS form for Y[0]
assign Y[1] = A[3] | A[2] | A[1] | ~A[0]; //assigns POS form for Y[1]... | 6.92457 |
module Decimal_Encoder (
D,
B
); //defines Decimal Encoder Module
input [9:0] D; //defines a 10 bit input wire D
output [3:0] B; //defines a 4 bit output wire B
assign B[0]= ((D[9] & D[8] & D[7] & D[6] & D[5] & D[4] & D[3] & D[2] & ~D[1] & D[0]) | (D[9] & D[8] & D[7] & D[6] & D[5] ... | 7.158831 |
module decimal_select (
control,
dp
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [1:0] control;
output dp;
// ===========================... | 7.439165 |
module decimal_splitter(
input [6:0] dec,
output reg [3:0] tens, units
);
always @ * begin
tens = dec / 10;
units = dec % 10;
end
endmodule
| 6.705257 |
module Decimal_to_Binary (
Number,
Bin
);
input [3:0] Number;
output reg [3:0] Bin;
integer num;
integer count = 0;
always @(Number) begin
num = Number;
Bin = 0;
while (num > 0) begin
if (num % 2 == 1) Bin[count] = 1'b1;
else Bin[count] = 1'b0;
num = num / 2;
coun... | 7.682769 |
module Decimal_to_Binary_TB;
reg [3:0] Number;
wire [3:0] Bin;
integer i;
Decimal_to_Binary uut (
.Number(Number),
.Bin(Bin)
);
initial $monitor("Number = %d | Binary = %b", Number, Bin);
initial Number = 4'b0;
initial begin
for (i = 0; i < 15; i = i + 1) begin
Number = Number + ... | 7.682769 |
module Decimate (
rst,
clk,
Iin,
dout,
rdy
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟，频率为2kHz
input signed [36:0] Iin; //数据输入频率为2kHZ
output signed [36:0] dout; //滤波后的输出数据
output rdy; //数据有效指示信号
reg [2:0] c;
reg signed [36:0] dout_tem;
reg rdy_tem;
always @(posedge clk ... | 7.298247 |
module decimation (
clk,
rst_n,
data_out,
clk_data,
fir_out,
clk_fir
);
`define OUT_WIDTH 8
`define FIR_OUTS_SIZE 20
`define FIR_OUT_SIZE 23 //20为每个FIR位宽，+3表示8相叠加后的位宽，在data_fir中定义过了，但是这里文件要覆盖它！
`define PHASE_NUM 8
`define PHASE_BIT 3
input clk; //定义系统时钟
input rst_n; //复位信号
out... | 6.825156 |
module Decimation_counter (
input [23:0] Deicimation_IN,
input RST,
input CLK,
output reg EN,
output reg CLK_EN
);
/* registers */
reg [23:0] Deicimation_reg;
reg rst;
/* IN/OUT temp registers */
always @(posedge CLK) begin
rst <= RST;
CLK_EN <= EN;
end
/*... | 7.049999 |
module decimator_tb;
reg clk;
reg rst_n;
reg unsigned [11:0] data_in;
wire unsigned [11:0] data_out;
wire new_data;
decimator dut (
.clk(clk),
.rst_n(rst_n),
.data_in(data_in),
.data_out(data_out),
.new_data(new_data)
);
always #10 clk = ~clk;
initial begin
clk <=... | 6.69853 |
module decim_tb ();
`include "usrp_tasks.v"
reg clk_120mhz;
reg usbclk;
reg reset;
reg [11:0] adc1_data, adc2_data;
wire [13:0] dac1_data, dac2_data;
wire [ 5:0] usbctl;
wire [ 5:0] usbrdy;
wire [15:0] usbdata;
reg WE, RD, OE;
assign usbctl[0] = WE;
assign usbctl[1] = RD;
assign usb... | 7.700173 |
module decision_funct #(parameter XLEN_PIXEL = 8, parameter NUM_OF_PIXELS =784, parameter NUM_OF_SV = 87, parameter DECISION_FUNCT_SIZE = 56)
(input clk, [(5*XLEN_PIXEL*NUM_OF_SV)-1:0] kernel_out, input decision_funct_en, [(2*XLEN_PIXEL)-1:0] product, [(2*XLEN_PIXEL)-1:0] b,
output reg [DECISION_FUNCT_SIZE-1:0] decisio... | 6.952046 |
module decision_funct_hwf#(parameter XLEN_PIXEL = 8, parameter NUM_OF_PIXELS =784, parameter NUM_OF_SV = 10, parameter DECISION_FUNCT_SIZE = 24)
(input clk, [(2*XLEN_PIXEL*NUM_OF_SV)-1:0] kernel_out, input decision_funct_en, [(2*XLEN_PIXEL)-1:0] product, [(2*XLEN_PIXEL)-1:0] b,
output reg y_class);
reg [2*XLEN_PIXEL-1... | 6.952046 |
module decision_funct_tb #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 4,
parameter NUM_OF_SV = 2,
parameter DECISION_FUNCT_SIZE = 48
);
reg clk, decision_funct_en;
reg [0:4*XLEN_PIXEL*NUM_OF_SV-1] kernel_out;
wire [0:5*XLEN_PIXEL-1] kernel_out_temp;
reg [(2*XLEN_PIXEL)-1:0] product;
... | 6.952046 |
module decision_mux (
move_type_mux,
rst,
spiral_speed,
turn_around_speed,
motion_speed,
rand_motion_command,
spiral_motion_command,
out_motion_command
);
input [1:0] move_type_mux;
input [2:0] spiral_speed;
input [2:0] turn_around_speed;
input [9:0] spiral_motion_command;
inp... | 8.508505 |
module decision_wait ( /*AUTOARG*/
// Outputs
z1,
z2,
// Inputs
a1,
a2,
fire,
rstn
);
input a1;
input a2;
input fire;
input rstn;
output z1;
output z2;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire xor1, xor2;
wire z1, z2;
xor2 U_XOR2_1 (
... | 7.535898 |
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire x, y;
assign x = a & b;
assign y = c & d;
assign out = x | y;
assign out_n = ~(out);
endmodule
| 7.203305 |
module deco5_32 (
input [4:0] Waddr_rst,
input Wen_rst,
output reg [31:0] Wen0_rst
);
always @(Waddr_rst or Wen_rst) begin
if (Wen_rst) begin
case (Waddr_rst)
5'b00000: begin
Wen0_rst = 32'h00000001;
end
5'b00001: begin
Wen0_rst = 32'h00000002;
... | 7.480177 |
module DecoAnillo (
input i_Reset,
input i_Clk,
output [1:0] o_Sel,
output [3:0] o_Anodos //Declaramos el bus de salida an, para controlar los andos.
);
wire [ 3:0] in; //Declaramos el bus auxiliar tipo wire de 4 bits in.
wire [15:0] x;
reg [ 1:0] Clk; //Declaramos el bus auxili... | 7.084147 |
module DecoBin_7Seg (
input [3:0] i_Deco,
output reg [6:0] o_Segmentos
);
always @* begin
case (i_Deco)
4'd0: begin
o_Segmentos <= 7'b0000001;
end
4'd1: begin
o_Segmentos <= 7'b1001111;
end
4'd2: begin
o_Segmentos <= 7'b0010010;
end
4'd3: ... | 6.52499 |
module decode38 (
led,
cout,
sum,
sw
);
input [2:0] sw;
output [7:0] led;
output cout;
output sum;
reg [7:0] led;
always@(sw) //8个led灯默认为高电平,不亮
begin
case (sw)
3'b000: led = 8'b0111_1111;
3'b001: led = 8'b1011_1111;
3'b010: led = 8'b1101_1111;
3'b011: le... | 6.705153 |
module decode38 (
led,
sw
);
input [2:0] sw;
output [7:0] led;
assign led = ~(1'b1 << sw);
endmodule
| 6.705153 |
module decod3x8 (
modo,
s1,
s0,
l7,
l6,
l5,
l4,
l3,
l2,
l1,
l0
);
input modo, s1, s0;
output l7, l6, l5, l4, l3, l2, l1, l0;
//a equacao das saidas do decodificador 3x8:
assign l0 = (~modo & ~s1 & ~s0);
assign l1 = (~modo & ~s1 & s0);
assign l2 = (~modo & s1 & ... | 7.238613 |
module decod47 (
input wire A,
B,
C,
D,
output wire [6:0] segs
);
assign segs[0] = (!A && C) || (A && !B && !C) || (!B && !C && !D) || (!A && B && D);
assign segs[1] = (!A && !B) || (!B && !C) || (!A && !C && !D) || (!A && C && D);
assign segs[2] = (!A && B) || (!A && !C) || (!A && D) || (!B... | 6.501042 |
module decod7_s (
input [3:0] cont,
output reg [6:0] disp
);
always @(cont) begin
case (cont)
4'b0000: disp = 7'b0000001;
4'b0001: disp = 7'b1001111;
4'b0010: disp = 7'b0010010;
4'b0011: disp = 7'b0000110;
4'b0100: disp = 7'b1001100;
4'b0101: disp = 7'b0100100;
4'... | 7.053351 |
module decode16_5 (
input [ 4:0] in,
output reg [15:0] out
);
always @(*) begin
case (in)
5'b00000: out <= 16'b0000_0000_0000_0000;
5'b00001: out <= 16'b0000_0000_0000_0001;
5'b00010: out <= 16'b0000_0000_0000_0011;
5'b00011: out <= 16'b0000_0000_0000_0111;
5'b00100: ou... | 7.745803 |
module decode1_rom (
opcode,
uc_addr
);
`include "ucode_consts.vh"
input wire [7:0] opcode;
output reg [UCODE_ADDR_LENGTH-1:0] uc_addr;
always @(*) begin
case (opcode)
`include "decode1.vh"
default: uc_addr = 0;
endcase
end
endmodule
| 7.867822 |
module describes a 2:4 decoder using behavioral constructs*
*in Verilog HDL.*/
/*module interface for the 2:4 decoder*/
module Decode24(in, out);
input [1:0] in; //2-bit input of type wire
output reg [3:0] out; //4-bit output of type reg
always @(in) begin //Triggered when in changes
case(in)
2'b00: out = 4'... | 7.288359 |
module decode2to4 (
Y,
Ena,
A1,
A2
);
input Ena, A1, A2;
output [3:0] Y;
wire nA2, nA1;
not n1 (nA1, A1), n2 (nA2, A2);
nand nd1 (
Y[0], Ena, nA1, nA2
), nd2 (
Y[1], Ena, nA1, A2
), nd3 (
Y[2], Ena, A1, nA2
), nd4 (
Y[3], Ena, A1, A2
);
endmodule
| 7.05109 |
module main (
input [1:0] J1,
output J3
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h0001)
) inst0 (
.I0(J1[0]),
.I1(J1[1]),
.I2(1'b0),
.I3(1'b0),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module Decode2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h1)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.445193 |
module Decode2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h1)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.445193 |
module Decode32 (
output [31:0] read_data_1,
output [31:0] read_data_2,
input [31:0] Instruction,
input [31:0] read_data, //from mem or io
input [31:0] ALU_result,
input Jal,
input RegWrite,
input MemtoReg, // MemOrIOtoReg
input RegDst,
output [31:0] Sign_extend,
input cloc... | 6.755336 |
module decode38 (
//INPUT
sw,
//OUTPUT
led
);
//*******************
//DEFINE INPUT
//*******************
input [2:0] sw;
//*******************
//DEFINE OUTPUT
//*******************
output [7:0] led;
//********************
//OUTPUT ATTRIBUTE
//********************
//WIRES
... | 6.705153 |
module decode38_for (
input wire [2:0] a,
output reg [7:0] y
);
integer i;
always @(*)
for (i = 0; i <= 7; i = i + 1)
if (a == i) y[i] = 1;
else y[i] = 0;
endmodule
| 6.665985 |
module decode4_8 (
input clk,
output [6:0] Outcode
);
reg [2:0] num = 3'b001;
reg [6:0] Outcode;
always @(posedge clk) begin
case (num)
4'd1: Outcode = 7'b1011011;
4'd2: Outcode = 7'b0111111; //ֹ֣ʾȷ
4'd3: Outcode = 7'b1101111;
default: Outcode = 7'bx;
endcase
;
nu... | 6.807369 |
module main (
input [3:0] J1,
output J3
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h0001)
) inst0 (
.I0(J1[0]),
.I1(J1[1]),
.I2(J1[2]),
.I3(J1[3]),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module Decode4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h0001)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.074411 |
module Decode4 (
input [3:0] I,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h0001)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.074411 |
module EQ8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
wire inst4_O;
wire inst5_O;
wire inst6_O;
wire inst7_O;
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst0 (
.I0(1'b1),
.I1(I0[0]),
.I2(I1[0]),
.I3(1'b0),
... | 6.605022 |
module Decode8_0 (
input [7:0] I,
output O
);
wire inst0_O;
EQ8 inst0 (
.I0(I),
.I1({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 6.791691 |
module main (
input [7:0] J1,
output J3
);
wire inst0_O;
Decode8_0 inst0 (
.I(J1),
.O(inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input [7:0] SWITCH,
output LED
);
wire inst0_O;
Decode8 inst0 (
.I(SWITCH),
.O(inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module: decodehigh
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decodeactivehigh;
// Inputs
reg s0;
reg s1;
// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
// Instantia... | 7.054082 |
module decodehigh (
input s0,
input s1,
output d0,
output d1,
output d2,
output d3
);
wire w1, w2;
not (w1, s0);
not (w2, s1);
and (d0, w1, w2);
and (d1, w1, s1);
and (d2, s0, w2);
and (d3, s0, s1);
endmodule
| 6.946585 |
module decodeKeysL4 (
output wire de_esc, // esc key
output wire de_validAscii, // valid ascii 0x20 to 0x7e
output wire de_bigD, // "D"
output wire de_bigE, // "E"
output wire de_bigL, // "L"
output wire de_bigP, // "P"
output wire de_bigS, // "S"
... | 8.748567 |
module decodelow (
input s0,
input s1,
output d0,
output d1,
output d2,
output d3
);
wire w1, w2;
not (w1, s0);
not (w2, s1);
nand (d0, w1, w2);
nand (d1, w1, s1);
nand (d2, s0, w2);
nand (d3, s0, s1);
endmodule
| 6.530679 |
module: decodelow
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decodelwtest;
// Inputs
reg s0;
reg s1;
// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
// Instantiate th... | 6.579005 |
module decoder_test_aha;
// Inputs
reg A, B, EN;
// Outputs
wire o0;
wire o1;
wire o2;
wire o3;
// Instantiate the Unit Under Test (UUT)
decoder24_aha uut (
.o0(o0),
.o1(o1),
.o2(o2),
.o3(o3),
.A (A),
.B (B),
.EN(EN)
);
initial begin
// Initialize ... | 7.20602 |
module decoder24_aha (
o0,
o1,
o2,
o3,
A,
B,
EN
);
input A, B, EN;
output o0, o1, o2, o3;
assign o0 = (~A) & (~B) & EN;
assign o1 = (~A) & (B) & EN;
assign o2 = (A) & (~B) & EN;
assign o3 = (A) & (B) & EN;
endmodule
| 6.809438 |
module decoder_testbench;
reg a;
reg b;
reg c;
wire [7:0] d;
decoder_verilog uut (
.a(a),
.b(b),
.c(c),
.d(d)
);
initial begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
#10 a = 1'b0;
b = 1'b0;
c = 1'b1;
#10 a = 1'b0;
b = 1'b1;
c = 1'b0;
#10 a =... | 7.225747 |
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