code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module decoder_3_8TB ();
reg [2:0] inputs;
reg enable;
wire [7:0] struct_out;
wire [7:0] behav_out;
//Instantiations
decoder_3_8_behav inst_b (
.en(enable),
.I (inputs),
.D (behav_out)
);
decoder_3_8_struct inst_s (
.en(enable),
.I (inputs),
.D (struct_out)
);
... | 6.655496 |
module decoder_3_8_str (
a,
b,
c,
y,
en
);
input a, b, c, en;
output [7:0] y;
reg [7:0] y;
always @(a or b or c or en) begin
if (en == 1)
case ({
a, b, c
})
3'b000: begin
y[0] = 1'b1;
end
3'b001: begin
y[1] = 1'b1;
e... | 6.756187 |
module decoder_3_8_behav (
I[2:0],
en,
D[7:0]
);
input [2:0] I;
input en;
output reg [7:0] D;
always @(I or en) begin
case ({
en, I
})
4'b1000: D = 8'b00000001;
4'b1001: D = 8'b00000010;
4'b1010: D = 8'b00000100;
4'b1011: D = 8'b00001000;
4'b1100: D = 8'b... | 8.079691 |
module decoder_3_8_str (
a,
b,
c,
y,
en
);
input a, b, c, en;
output [7:0] y;
assign y[0] = (~a) & (~b) & (~c) & (en);
assign y[1] = (~a) & (~b) & (c) & (en);
assign y[2] = (~a) & (b) & (~c) & (en);
assign y[3] = (~a) & (b) & (c) & (en);
assign y[4] = (a) & (~b) & (~c) & (en);
assign... | 6.756187 |
module decoder_3_8_str (
a,
b,
c,
y,
en
);
input a, b, c, en;
output [7:0] y;
wire w1, w2, w3;
not l1 (w1, a);
not l2 (w2, b);
not l3 (w3, c);
and l4 (y[0], w1, w2, w3, en);
and l5 (y[1], w1, w2, c, en);
and l6 (y[2], w1, b, w3, en);
and l7 (y[3], w1, b, c, en);
and l8 (y[4], a... | 6.756187 |
module decoder_3_8_struct (
en,
I[2:0],
D[7:0]
);
input [2:0] I;
input en;
output [7:0] D;
wire [2:0] I_not;
not (I_not[0], I[0]);
not (I_not[1], I[1]);
not (I_not[2], I[2]);
and (D[0], en, I_not[2], I_not[1], I_not[0]);
and (D[1], en, I_not[2], I_not[1], I[0]);
and (D[2], en, I_not[... | 6.756187 |
module DECODER_3_8_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [2:0] IN;
wire [7:0] OUT;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] OUTEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
decoder_3_8_behavioral U... | 8.315477 |
module decoder_3_to_5 (
data,
position
);
input [2:0] data;
output [4:0] position;
reg [4:0] temp = 0;
//3-5 二进制译码器
assign position = temp;
always @(data) begin
case (data)
0: temp <= 5'b00001;
1: temp <= 5'b00010;
2: temp <= 5'b00100;
3: temp <= 5'b01000;
4: temp <... | 8.235119 |
module decoder_3_to_8 #(
parameter DELAY = 10
) (
input wire a0,
a1,
a2,
e1,
e2_n,
e3_n,
output wire y0_n,
y1_n,
y2_n,
y3_n,
y4_n,
y5_n,
y6_n,
y7_n
);
reg [7:0] y;
integer i;
always @*
if ({e1, e2_n, e3_n} == 3'b100)
for (i = 0; i <= 7; i = ... | 8.235119 |
module decoder_3_to_8_dataflow (
in_lines,
out_lines
);
input [2:0] in_lines;
output [7:0] out_lines;
//* Data-flow modelling
assign out_lines[0] = ~in_lines[2] & ~in_lines[1] & ~in_lines[0],
out_lines[1] = ~in_lines[2] & ~in_lines[1] & in_lines[0],
out_lines[2] = ~in_lines[2] & in_lines[1... | 8.235119 |
module decoder_3_to_8_dataflow_test;
reg [2:0] in_lines;
wire [7:0] out_lines;
decoder_3_to_8_dataflow wire_driver (
in_lines,
out_lines
);
initial begin
in_lines = 3'b000;
#20 in_lines = 3'b001;
#20 in_lines = 3'b010;
#20 in_lines = 3'b011;
#20 in_lines = 3'b100;
#20 i... | 8.235119 |
module decoder_3_to_8_structural_or_gatelevel (
in_lines,
out_lines
);
input [2:0] in_lines;
output [7:0] out_lines;
//* Gate-level modelling
and (out_lines[0], ~in_lines[2], ~in_lines[1], ~in_lines[0]);
and (out_lines[1], ~in_lines[2], ~in_lines[1], in_lines[0]);
and (out_lines[2], ~in_lines[2], ... | 8.235119 |
module decoder_3_to_8_structural_or_gatelevel_test;
reg [2:0] in_lines;
wire [7:0] out_lines;
decoder_3_to_8_structural_or_gatelevel wire_driver (
in_lines,
out_lines
);
initial begin
in_lines = 3'b000;
#20 in_lines = 3'b001;
#20 in_lines = 3'b010;
#20 in_lines = 3'b011;
#2... | 8.235119 |
module decoder_3to8 (
Y7,
Y6,
Y5,
Y4,
Y3,
Y2,
Y1,
Y0,
A,
B,
C,
en
);
//*****************************************************************
output Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
input A, B, C;
input en;
assign {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} =
( {en,A,B,C} == 4'b1... | 9.361749 |
module decoder_3to8 (
Y7,
Y6,
Y5,
Y4,
Y3,
Y2,
Y1,
Y0,
A,
B,
C,
en
);
//*****************************************************************
output Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
input A, B, C;
input en;
assign {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} = ( {en,A,B,C} == 4'b1000) ?... | 9.361749 |
module decoder_3to8 (
input [2:0] a,
input enable,
output reg [7:0] y
);
//Whenever there is a change in the bus 'a' or 'enable' -> execute the always block.
always @(a or enable) begin // wildcard '*' could also be used
if (enable == 0) y = 8'b0;
else begin
case (a) //case statement. C... | 9.361749 |
module decoder_4to16 (
input [ 3:0] a,
output [15:0] d
);
decoder_3to8 DEC1 (
.a(a[2:0]),
.enable(~a[3]),
.y(d[7:0])
);
decoder_3to8 DEC2 (
.a(a[2:0]),
.enable(a[3]),
.y(d[15:8])
);
endmodule
| 6.758035 |
module tb_decoder_4to16 ();
reg [3:0] a;
wire [15:0] d;
integer i;
// Instantiate the DUT
decoder_4to16 DEC4_16 (
.a(a),
.d(d)
);
// Create stimulus
initial begin
$monitor($time, " a = %d, d = %b", a, d);
#1;
a = 0;
for (i = 0; i < 16; i = i + 1) begin
#1;
a = ... | 6.8348 |
module decoder_4to16_tb;
// signal declaration
reg [ 4:0] test_in;
wire [15:0] out;
// instance of decoder
decoder_4to16 uut (
.in(test_in),
.bcode(out)
);
// test vectors
initial begin
for (test_in = 0; test_in < 5'b10000; test_in = test_in + 1) begin
#5;
end
$stop;
... | 6.758035 |
module Decoder_4x16_t;
parameter SIZE_IN = 4;
parameter SIZE_OUT = 16;
reg [ SIZE_IN-1:0] sel = 4'b0;
wire [SIZE_OUT-1:0] out;
Decoder_n_4x16_in_nand decoder_4x16 (
.sel(sel),
.out(out)
);
initial begin
repeat (2 ** 4) begin
#1 sel = sel + 4'b1;
end
#1 $finish;
end
en... | 6.720422 |
module decoder_4_16 (
input wire [ 3:0] in,
output reg [15:0] out
);
always @(*) begin
case (in)
4'd0: begin
out = 16'b1;
end
4'd1: begin
out = 16'b10;
end
4'd2: begin
out = 16'b100;
end
4'd3: begin
out = 16'b1000;
end
... | 7.408825 |
module decoder_4_16_tb;
// Inputs
reg [3:0] in;
reg en;
// Outputs
wire [15:0] dout;
// Instantiate the Unit Under Test (UUT)
decoder4x16 uut (
.in (in),
.en (en),
.dout(dout)
);
initial begin
// Initialize Inputs
en <= 1'b0;
in <= 4'b0000;
#10 in <= 4'b0001;
... | 7.67937 |
module decoder_4_2 (
input EN,
input A1,
input A2,
output D0,
output D1,
output D2,
output D3
);
wire A1P, A2P;
not n1 (A1P, A1), n2 (A2P, A2);
and a1 (D0, A2P, A1P, EN), a2 (D1, A2, A1P, EN), a3 (D2, A2P, A1, EN), a4 (D3, A2, A1, EN);
endmodule
| 8.043204 |
module decoder_4_7_seg (
input clk,
rst,
input [13:0] displayed_number,
output reg [3:0] digit,
output reg [7:0] segs
);
reg [ 3:0] bcd;
reg [18:0] counter;
reg [ 1:0] led_select;
initial begin
counter <= 0;
end
always @(posedge clk, posedge rst) begin
if (rst == 1'b1) begin
... | 6.850015 |
module Decoder_4_bit (
output [15:0] D,
input [ 3:0] I
);
wire w;
GL_decoder_3_bit D0 (
D[7:0],
I[2:0],
I[3]
);
not G0 (w, I[3]);
BF_decoder_3_bit D1 (
D[15:8],
I[2:0],
w
);
endmodule
| 7.152898 |
module decoder_4_to_16 (
input [ 3:0] i_i, // Input
input en_i, // Enable
output reg [15:0] y_o // Output
);
// Combinational Logic
always @(*) begin
if (en_i) begin
case (i_i)
4'h0: y_o = 16'h0001;
4'h1: y_o = 16'h0002;
4'h2: y_o = 16'h... | 6.855446 |
module decoder_4_to_16_tb ();
// Signal Decleration
reg [ 3:0] i_i;
reg en_i;
wire [15:0] y_o;
// Instantiation
decoder_4_to_16 dut (
.i_i (i_i),
.en_i(en_i),
.y_o (y_o)
);
// Logic to drive inputs and check outputs
initial begin
en_i = 1'b1;
repeat (10) begin
... | 6.855446 |
module decoder_5bits (
out,
sel,
en
);
output [31:0] out;
input [4:0] sel;
input en;
wire [4:0] nsel;
not n0 (nsel[0], sel[0]);
not n1 (nsel[1], sel[1]);
not n2 (nsel[2], sel[2]);
not n3 (nsel[3], sel[3]);
not n4 (nsel[4], sel[4]);
and_5bits out0 (
out[0],
nsel[4],
nse... | 7.029476 |
module and_5bits (
o,
a,
b,
c,
d,
e,
en
);
output o;
input a, b, c, d, e, en;
wire w0, w1, w2, w3;
and a0 (w0, a, b);
and a1 (w1, w0, c);
and a2 (w2, w1, d);
and a3 (w3, w2, e);
and a4 (o, w3, en);
endmodule
| 6.922633 |
module Decoder_5x32 (
out,
sel
);
parameter SIZE_IN = 5;
parameter SIZE_OUT = 32;
wire [SIZE_OUT/2:0] half_out;
Decoder_4x16 half_decoder (
.sel(sel[SIZE_IN-1-1:0]),
.out(half_out)
);
Mux_2x1_32bits mux (
.in0({16'b0, half_out}),
.in1({half_out, 16'b0}),
.sel(sel[SI... | 6.733416 |
module Mux_2x1_32bits (
out,
in1,
in0,
sel
);
parameter SIZE = 32;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input sel;
output [SIZE-1:0] out;
Mux_1bit mux_1bit[SIZE-1:0] (
out,
in1,
in0,
sel
);
endmodule
| 7.023729 |
module decoder_5_32 (
input wire [ 4:0] in,
output reg [31:0] out
);
always @(*) begin
case (in)
5'd00: begin
out = 32'b00000000000000000000000000000001;
end
5'd01: begin
out = 32'b00000000000000000000000000000010;
end
5'd02: begin
out = 32'b00000000... | 6.549097 |
module Decoder_6x64 (
out,
sel
);
parameter SIZE_IN = 6;
parameter SIZE_OUT = 64;
wire [SIZE_OUT/2:0] half_out;
Decoder_5x32 half_decoder (
.sel(sel[SIZE_IN-1-1:0]),
.out(half_out)
);
Mux_2x1_64bits mux (
.in0({32'b0, half_out}),
.in1({half_out, 32'b0}),
.sel(sel[SI... | 7.502547 |
module Mux_2x1_64bits (
out,
in1,
in0,
sel
);
parameter SIZE = 64;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input sel;
output [SIZE-1:0] out;
Mux_1bit mux_1bit[SIZE-1:0] (
out,
in1,
in0,
sel
);
endmodule
| 7.74829 |
module decoder_7 (
input [1:0] in,
output reg [3:0] out
);
localparam WIDTH = 2'h2;
always @* begin
out = 1'h0;
out[(in)*1+0-:1] = 1'h1;
end
endmodule
| 6.590695 |
module decoder_7seg (
A,
B,
C,
D,
led_a,
led_b,
led_c,
led_d,
led_e,
led_f,
led_g
);
// -------------------------- Inputs Declarations ---------------------------- //
input A, B, C, D;
// ------------------------- Outputs Declarations ---------------------------- //
o... | 7.043532 |
module decoder_7seg (
input [3:0] din,
output reg [6:0] segs
);
always @(*) begin
case (din)
0: segs = 7'b111_1110;
1: segs = 7'b011_0000;
2: segs = 7'b110_1101;
3: segs = 7'b111_1001;
4: segs = 7'b011_0011;
5: segs = 7'b101_1011;
6: segs = 7'b101_1111;
7: ... | 7.043532 |
module Decoder_7x128 (
out,
sel
);
parameter SIZE_IN = 7;
parameter SIZE_OUT = 128;
wire [SIZE_OUT/2:0] half_out;
Decoder_6x64 half_decoder (
.sel(sel[SIZE_IN-1-1:0]),
.out(half_out)
);
Mux_2x1_128bits mux (
.in0({64'b0, half_out}),
.in1({half_out, 64'b0}),
.sel(sel... | 8.212187 |
module Mux_2x1_128bits (
out,
in1,
in0,
sel
);
parameter SIZE = 128;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input sel;
output [SIZE-1:0] out;
Mux_1bit mux_1bit[SIZE-1:0] (
out,
in1,
in0,
sel
);
endmodule
| 7.44601 |
module Decoder_8 (
Enable,
Sel,
DecoderOut_0,
DecoderOut_1,
DecoderOut_2,
DecoderOut_3,
DecoderOut_4,
DecoderOut_5,
DecoderOut_6,
DecoderOut_7
);
/***************************************************************************
** Here the inputs are defined ... | 7.042304 |
module decoder_21 (
input e,
s,
output I_0,
I_1
);
assign I_0 = e & (!s);
assign I_1 = e & (s);
endmodule
| 7.318872 |
module decoder (
iData,
iEna,
oData
);
input [4:0] iData;
input iEna;
output [31:0] oData;
reg [31:0] oData;
always @(iData or iEna) begin
if (iEna == 1'b1)
case (iData)
5'b00000: oData = 32'b11111111111111111111111111111110;
5'b00001: oData = 32'b111111111111111111111111... | 7.018254 |
module decoder_assign (
decoder_out,
enable,
binary_in
);
input [3:0] binary_in; // 4 bit binary input
input enable; // Enable for the decoder
output [15:0] decoder_out; // 16-bit out
assign decoder_out = (enable) ? (1 << binary_in) : 16'b0;
//if enable =1, decoder_out will be 2** binary_n... | 8.269737 |
module decoder_behavioral (
out,
in
);
output [3:0] out; // 4out
input [1:0] in; // 2input
reg [3:0] out;
always @(in) begin
if (in == 2'b00) out = 4'b0001; // 00일 때 0001 출력
else if (in == 2'b01) out = 4'b0010; // 01일 때 0010 출력
else if (in == 2'b10) out = 4'b0100; // 10일 때 0100 출력
... | 6.563661 |
module decoder_case (
binary_in,
decoder_out,
enable
);
input [3:0] binary_in; // 4 bit binary input
input enable; // Enable for the decoder
output [15:0] decoder_out; // 16-bit out
reg [15:0] decoder_out;
always @(enable or binary_in) begin
decoder_out = 0;
if (enable) begin
... | 7.218686 |
module decoder_complex (
input wire [ 7 : 0] opcode, /* opcode */
input wire [ `FWIDTH - 1 : 0] flags, /* ALU flags */
output reg [`MC_OFFSET_WIDTH - 1 : 0] op_decoder_out /* microcode offset */
);
always @(*) begin
case (opcode)
/* add from immedi... | 7.060111 |
module decoder_complex_tb;
/* inputs and control signals */
reg [7:0] opcode;
reg clk;
/* output signal */
wire [5:0] rom_offset;
/* unit under testing */
decoder_complex uut (
.opcode(opcode),
.rom_offset(rom_offset)
);
initial begin
/* signal initialization */
opcode = 0;
... | 7.060111 |
module decoder_control( // @suppress "Design unit name 'decoder_control' does not match file name 'hw8v2'"
input [31:0] instr,
input [3:0] flag,
output reg jmp_en,
output reg jmp_reg_en,
output reg flag_en,
output reg data_w_en,
output reg data_mem,
output reg data_mem_en,
output reg... | 7.276265 |
module decoder_dataflow (
out,
in
);
output [3:0] out; // 4out
input [1:0] in; // 2input
assign out[0] = (~in[0] & ~in[1]); // 00 일 때 out0이 1 나머지 0
assign out[1] = (in[0] & ~in[1]); // 01 일 때 out1이 1
assign out[2] = (~in[0] & in[1]); // 10 일 대 out2이 1
assign out[3] = (in[0] & in[1]); // 11 일 ... | 6.67262 |
module decoder_DE10_Lite (
SW,
LEDR
);
input [9:0] SW;
output [9:0] LEDR;
decoder #(
.ONE_HOT_WIDTH(10)
) dec_inst (
.i_bin(SW[3:0]),
.o_one_hot(LEDR)
);
endmodule
| 6.929434 |
module DECODER_GROUP (
input wire [127:0] code_buf_i,
input wire [ 6:0] buf_size_i,
input wire [ 3:0] zrl_cnt_i,
output wire [127:0] code_buf_o,
output wire [ 6:0] buf_size_o,
output wire [ 3:0] zrl_cnt_o,
output wire [251:0] data_o,
output wire [ 3:0] valid_o,
output wire [ ... | 6.631284 |
module DECODER (
input wire [127:0] code_buf_i,
input wire [ 6:0] buf_size_i,
input wire [ 3:0] zrl_cnt_i,
output reg valid_o,
output reg [6:0] shift_cnt_o,
output reg [3:0] zrl_cnt_o,
output reg do_xor_o,
output reg [62:0] data_o
);
always @(*) begin
valid_o = 0;
shift_cn... | 6.800244 |
module decoder_generic #(
parameter N = 3
) (
input [N - 1:0] w,
input en,
output reg [0:2 ** N - 1] y
);
always @(w, en) begin
y = 'b0;
if (en) y[w] = 1'b1;
else y = 'b0;
end
endmodule
| 7.147456 |
module decoder_generic_tb ();
// 1) Declare local reg and wire identifiers
parameter N = 4;
reg [N - 1:0] w;
reg en;
wire [0:2 ** N - 1] y;
integer k;
// 2) Instantiate the unit under test
decoder_generic #(
.N(N)
) uut0 (
.w (w),
.en(en),
.y (y)
);
// 3) Specify a stopwa... | 7.147456 |
module decoder_hamming (
input wire [0:15] c_h,
output reg [0:10] data_out,
input wire enable,
output reg error,
output reg error_incorrigible
);
reg [3:0] error_index; // index do bit errado
reg [0:15] data_aux;
reg bit_parity; // bit de paridade
always @(*) begin
if (enable == 1'b1... | 7.929187 |
module decoder_hex_10 (
input [3:0] x,
output reg [0:6] h
);
always @(x)
case (x)
0: h = 7'b1000000;
1: h = 7'b1111001;
2: h = 7'b0100100;
3: h = 7'b0110000;
4: h = 7'b0011001;
5: h = 7'b0010010;
6: h = 7'b0000010;
7: h = 7'b1111000;
8: h = 7'b0000000... | 7.325232 |
module decoder_hex_16 (
input [3:0] x,
output reg [6:0] h
);
always @(x)
case (x)
0: h = 7'b1000000;
1: h = 7'b1111001;
2: h = 7'b0100100;
3: h = 7'b0110000;
4: h = 7'b0011001;
5: h = 7'b0010010;
6: h = 7'b0000010;
7: h = 7'b1111000;
8: h = 7'b0000000... | 7.325232 |
module decoder_key (
input clk,
input [3:0] columnas,
output reg [4:0] outcode = 5'b00000,
output [3:0] filas
);
reg [1:0] cont = 2'b0;
selector_filas_key(
.sel(cont), .valfilas(filas)
);
always @(posedge clk) begin
if (cont == 2'b11) begin
cont <= 0;
end else begin
... | 6.613015 |
module decoder_main (
input clk,
input enable,
input down, //up is reset, down is backspace.
short,
long, //left and right
mid,
rst, //mid for confirm
//longest morse code is 5bit, add one bit for error-detecting
//switch to Encode mode
output [22:0] led_out, //one light f... | 7.508774 |
module decoder_nbit
// Parameters section
#(
parameter N = 3
)
// Ports section
(
input [N-1:0] a,
input enable,
output reg [2**N-1:0] y
);
always @(*) begin
if (enable == 0) y = 0;
else y = (1 << a);
end
endmodule
| 6.628079 |
module tb_decoder_nbit ();
parameter DEC_WIDTH = 3;
reg [DEC_WIDTH-1:0] a;
reg enable;
wire [2**DEC_WIDTH-1:0] y;
integer i; // used in the for loop
// Instantiate the parameterized DUT
decoder_nbit #(
.N(DEC_WIDTH)
) DEC1 (
.a(a),
.enable(enable),
.y(y)
);
// Create sti... | 7.686316 |
module decoder (
code,
rd_enable,
clock,
BCD
);
input [3:0] code;
output [7:0] BCD;
input rd_enable, clock;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n33, n34, n35, n3... | 7.018254 |
module decoder_Nx2pN #(
parameter N = 2
) (
input [N-1:0] IN,
output reg [(2**N)-1:0] OUT
);
integer i = 0;
always @(*) begin
for (i = 0; i < 2 ** N; i = i + 1) begin
OUT[i] = 0;
end
OUT[IN] = 1'b1;
end
endmodule
| 7.875318 |
module decoder_param (
out,
in
);
parameter BITS = 2;
parameter SIZE = 4;
output [SIZE - 1:0] out;
input [BITS - 1:0] in;
reg [SIZE -1:0] out;
integer i;
always @(in) begin
for (i = 0; i < SIZE; i = i + 1) begin
out[i] = (in == i) ? 1'b1 : 1'b0;
end
end
endmodule
| 6.525265 |
module decoder_param_en (
out,
in,
en
);
parameter BITS = 2;
parameter SIZE = 4;
output [SIZE - 1:0] out;
input [BITS - 1:0] in;
input en;
reg [SIZE -1:0] out;
integer i;
always @(in or en) begin
for (i = 0; i < SIZE; i = i + 1) begin
out[i] = en ? ((in == i) ? 1'b1 : 1'b0) : 1... | 6.525265 |
module decoder (
cx,
d
);
output [6:0] d;
input [11:0] cx;
reg [ 6:0] d;
reg [ 4:0] s;
reg [11:0] cx1;
parameter s0 = 5'b11110;
parameter s1 = 5'b10111;
parameter s2 = 5'b01000;
parameter s3 = 5'b00111;
parameter s4 = 5'b01000;
parameter s5 = 5'b11111;
parameter s6 = 5'b10111;
para... | 7.018254 |
module implements an 5 to 32 decoder with precoding
Step 1. predecode the input in groups 3-2, that gives us 8 + 4 =12 wires
Step 2. combine the pre-decoded wires to generate final output
*/
module decoder_precoding (input [4:0] sel,
output [31:0] out);
// predecoding upper 3 bits
... | 6.667836 |
module Decoder_Register_File (
input [ 4:0] Write_Register_i,
output [31:0] Select_Register_o
);
reg [31:0] select_register_r;
always @(*) begin
case (Write_Register_i)
0: select_register_r = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
1: select_register_r = 32'b0000_0000_0000_0000_0000... | 6.843957 |
module: Decoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Decoder_tb01_v;
// Inputs
reg [11:0] Instr;
// Outputs
wire OPTION;
wire SLEEP;
wire CLRWDT;
wire TRIS1;
wir... | 6.663751 |
module for s2
module s2(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = ~c3 & ~c2 & c1 & ~c0 | c3 & c2 & ~c0 | c3 & c2 & c1;
endmodule
| 6.735825 |
module for s3
module s3(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = ~c3 & c2 & ~c1 & ~c0 | c3 & ~c2 & c1 & ~c0 | ~c1 & c0 & ~c2 | c1 & c0 & c2;
endmodule
| 6.844572 |
module for s4
module s4(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = ~c3 & c0 | ~c3 & c2 & ~c1 | ~c1 & c0 & ~c2;
endmodule
| 7.72525 |
module for s5
module s5(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = c3 & c2 & ~c1 & c0 | c1 & c0 & ~c3 | ~c3 & ~c2 & c0 | ~c3 & ~c2 & c1;
endmodule
| 6.657867 |
module for s6
module s6(c3, c2, c1, c0, o);
input c3, c2, c1, c0;
output o;
assign o = ~c3 & c2 & c1 & c0 | c3 & c2 & ~c1 & ~c0 | ~c3 & ~c2 & ~c1;
endmodule
| 6.590278 |
module Decoder_Test;
//Period of the clock
localparam PERIOD = 100;
//Parameters of the module
localparam IMAGE_WIDTH = 320;
localparam IMAGE_HEIGHT = 240;
localparam PIXEL_WIDTH = 8;
localparam TABLE_SIZE = 64;
localparam IMAGE_RAM_ADDRESS_WIDTH = $rtoi($ceil($clog2(IMAGE_WIDTH*IMA... | 7.089543 |
module decoder_testbench ();
reg [1:0] sel;
reg en;
wire ena, enb, enf;
decoder test (
.sel(sel),
.en (en),
.ena(ena),
.enb(enb),
.enf(enf)
);
initial begin
sel = 2'b0;
en = 0;
#200 en = ~en;
end
always #20 sel = sel + 1;
endmodule
| 7.225747 |
module. This module serves as an example,
// and allows the user to synthesize a self-contained design,
// which they can be used to test their hardware.
// In addition to the memory controller, the module instantiates:
// 1. Synthesizable testbench - used to model user's backend logic
// and generate ... | 7.505728 |
module decoder_top_lly (
clk, //125M
clk_dp,
// areset,//(rst_tx_fifo),
data_in, //rx_dat_fifo_dout
data_out, //mhd_dout_wdata
rst,
we_decode
);
input clk; //125M
input clk_dp;
// input areset,//(rst_tx_fifo),
input data_in; //rx_dat_fifo_dout
... | 6.545819 |
module decoder_7seg (
A,
B,
C,
D,
led_a,
led_b,
led_c,
led_d,
led_e,
led_f,
led_g
);
// -------------------------- Inputs Declarations ---------------------------- //
input A, B, C, D;
// ------------------------- Outputs Declarations ---------------------------- //
o... | 7.043532 |
module decoder_type_b (
input wire `inst_t inst,
output reg `oper_t op,
output wire `word_t imm,
output wire `regaddr_t reg_read_addrx,
output wire `regaddr_t reg_read_addry
);
assign reg_read_addrx = inst[19 : 15];
assign reg_read_addry = inst[24 : 20];
assign imm = ... | 6.89422 |
module decoder_type_i(
input wire `inst_t inst,
output reg `oper_t op,
output reg `word_t imm,
output wire `regaddr_t reg_read_addr,
output wire `regaddr_t reg_write_addr
);
/* I-type and L-type use same decoder */
wire `word_t imm0;
assign reg_read_addr = inst[19 : 15];
assign ... | 6.89422 |
module decoder_type_r (
input wire `inst_t inst,
output reg `oper_t op,
output wire `regaddr_t reg_read_addrx,
output wire `regaddr_t reg_read_addry,
output wire `regaddr_t reg_write_addr
);
assign reg_read_addry = inst[24 : 20];
assign reg_read_addrx = inst[19 : 15];
assign reg_wri... | 6.89422 |
module decoder_type_s (
input wire `inst_t inst,
output reg `oper_t op,
output wire `word_t imm,
output wire `regaddr_t reg_read_addrx,
output wire `regaddr_t reg_read_addry
);
assign reg_read_addrx = inst[19 : 15];
assign reg_read_addry = inst[24 : 20];
assign imm =... | 6.89422 |
module name and ports declarations
module Decoder_Unit (
input wire [1:0] alu_fun,
output reg arith_enable,
output reg logic_enable,
output reg cmp_enable,
output reg shift_enable );
//RTL Code
always @(*) // if it is still combinational we have to make sure the input still stable
// to the edge of th... | 8.033626 |
module decoder_using_assign (
binary_in, // 4 bit binary input
decoder_out, // 16-bit out
enable // Enable for the decoder
);
input [3:0] binary_in;
input enable;
output [15:0] decoder_out;
wire [15:0] decoder_out;
assign decoder_out = (enable) ? (1 << binary_in) : 16'b0;
endmodule
| 7.196438 |
module decoder_using_case (
binary_in, // 4 bit binary input
decoder_out, // 16-bit out
enable // Enable for the decoder
);
input [3:0] binary_in;
input enable;
output [15:0] decoder_out;
reg [15:0] decoder_out;
always @(enable or binary_in) begin
decoder_out = 0;
if (enable) begi... | 7.196438 |
module decoder_write (
out,
select_bits,
enable
);
input [4:0] select_bits;
input enable;
output [31:0] out;
wire [31:0] out0, out1, out2, out3;
wire [31:0] enable_32bits;
assign enable_32bits = {31'b0000000000000000000000000000000, enable};
assign out0 = select_bits[0] ? {enable_32bits[30:0... | 7.403734 |
module DECODESTART (
input [`NUM_STAGES-1:0] iTHERMOMETERSTART,
output [ `NUM_BITS-1:0] oBINSTART
);
reg [`NUM_BITS-1:0] rBINSTART;
integer i;
wire [`NUM_STAGES-1:0] wTHERMOMETERSTART;
assign wTHERMOMETERSTART = iTHERMOMETERSTART; // << 10;
always @(wTHERMOMETERSTART) begin
rBINSTART = 0;
... | 6.62309 |
module DECODESTOP (
input [`NUM_STAGES-1:0] iTHERMOMETERSTOP,
output [ `NUM_BITS-1:0] oBINSTOP
);
reg [`NUM_BITS-1:0] rBINSTOP;
integer i;
always @(iTHERMOMETERSTOP) begin
rBINSTOP = 0;
for (i = 0; i < `NUM_STAGES - 20; i = i + 1'b1) begin
if(~iTHERMOMETERSTOP[i] & iTHERMOMETERSTOP[i+1] ... | 7.045054 |
module Decodeunit #(parameter width=32)(
input clk,RegWrite,[width-1:0]PC1,Instruction,
WriteData,
input[4:0] Rd,RD,
input Memread,
output [width-1:0]RD1,RD2,PC,immediatevalue,
output [4:0] rd, [3:0] ALUcontrolinput,
output [8:0] control, [4:0] Rs1,Rs2,
output PCen,IFIDen);
wire... | 6.759844 |
module W0RM_Decode_10_tb (
output wire done,
error
);
Decode_base_tb #(
.FILE_SOURCE ("../testbench/data/core/Decode_10_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/Decode_10_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 6.610009 |
module W0RM_Decode_1_tb (
output wire done,
error
);
reg clk = 0;
always #2.5 clk <= ~clk;
W0RM_Core_Decode dut (
.clk(clk),
.instruction(16'd0),
.inst_valid(1'b0),
.fetch_ready(1'b0)
);
assign done = 1;
assign error = 0;
endmodule
| 6.610009 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-15-2014: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module W0RM_Decode_2_tb (
output wire done,
error
);
Decode_base_tb #(
.FILE_SOURCE ("../testbench/data/core/Decode_2_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/Decode_2_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 6.883196 |
module decode_32_2 (
input [5-1:0] sel,
input [32-1:0] din,
output dout
);
wire [32-1:0] p = din << sel;
assign dout = p[32-1];
endmodule
| 7.415286 |
module decode_38 (
input [2:0] s,
output [7:0] y
);
reg [7:0] y;
always @(s) begin
case (s)
3'b000: y = 8'b0000_0001;
3'b001: y = 8'b0000_0010;
3'b010: y = 8'b0000_0100;
3'b011: y = 8'b0000_1000;
3'b100: y = 8'b0001_0000;
3'b101: y = 8'b0010_0000;
3'b110... | 7.474326 |
module W0RM_Decode_3_tb (
output wire done,
error
);
Decode_base_tb #(
.FILE_SOURCE ("../testbench/data/core/Decode_3_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/Decode_3_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 7.618593 |
module decode_416 (
input [ 3:0] s,
output [15:0] y
);
reg [15:0] y;
always @(s) begin
case (s)
4'b0000: y = 16'b0000_0000_0000_0001;
4'b0001: y = 16'b0000_0000_0000_0010;
4'b0010: y = 16'b0000_0000_0000_0100;
4'b0011: y = 16'b0000_0000_0000_1000;
4'b0100: y = 16'b000... | 7.708663 |
module decode_4_16 (
address,
wclk,
Yi
);
input wire [3:0] address;
input wire wclk;
output reg [15:0] Yi;
always @* begin
if (wclk == 1'b1)
case (address[3:0])
4'b0000: Yi = 16'h0001;
4'b0001: Yi = 16'h0002;
4'b0010: Yi = 16'h0004;
4'b0011: Yi = 16'h0008;
... | 6.642878 |
module W0RM_Decode_4_tb (
output wire done,
error
);
Decode_base_tb #(
.FILE_SOURCE ("../testbench/data/core/Decode_4_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/Decode_4_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 7.010235 |
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