code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DECODE_5_32 (
select,
out
);
parameter SELECT_WIDTH = 5;
parameter OUT_WIDTH = 32;
input [SELECT_WIDTH-1:0] select;
output [SELECT_WIDTH-1:0] out;
assign out[0] = (~select[4]) & (~select[3]) & (~select[2]) & (~select[1]) & (~select[0]);
assign out[1] = (~select[4]) & (~select[3]) & (~sel... | 8.067909 |
module W0RM_Decode_5_tb (
output wire done,
error
);
Decode_base_tb #(
.FILE_SOURCE ("../testbench/data/core/Decode_5_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/Decode_5_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 7.159436 |
module W0RM_Decode_6_tb (
output wire done,
error
);
Decode_base_tb #(
.FILE_SOURCE ("../testbench/data/core/Decode_6_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/Decode_6_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 6.89366 |
module decode_7segment (
decimal,
display
);
input [3:0] decimal;
output [6:0] display;
/*
The binary encoded decimal digit is contained in decimal[0] to decimal[3].
Each element of display drives one segment of the output.
Boolean operation symbols:
& = AND e.g. (A & B)
| = OR e.g. (A | B)
... | 6.885807 |
module W0RM_Decode_7_tb (
output wire done,
error
);
Decode_base_tb #(
.FILE_SOURCE ("../testbench/data/core/Decode_7_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/Decode_7_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 6.687247 |
module testbench;
reg [9:0] data_in;
reg k_in;
wire [7:0] data_out;
Decode_8Bto10B testbench (
.data_in(),
.k_in(k_in),
.data_out(data_out)
);
initial begin
data_in = 10'b1100001001;
k_in = 0;
end
endmodule
| 7.015571 |
module W0RM_Decode_8_tb (
output wire done,
error
);
Decode_base_tb #(
.FILE_SOURCE ("../testbench/data/core/Decode_8_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/Decode_8_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 7.087576 |
module W0RM_Decode_9_tb (
output wire done,
error
);
Decode_base_tb #(
.FILE_SOURCE ("../testbench/data/core/Decode_9_tb_data.txt"),
.FILE_COMPARE("../testbench/data/core/Decode_9_tb_compare.txt")
) dut (
.done (done),
.error(error)
);
endmodule
| 7.356713 |
module DECODE_ADDER #( //PARAMETERS
parameter DATA_WIDTH = 32
) ( //INPUTS
input [DATA_WIDTH - 1:0] i_currentpc,
input [DATA_WIDTH - 1:0] i_extendido,
//OUTPUTS
output [DATA_WIDTH - 1:0] o_pcbranch
);
assign o_pcbranch = i_currentpc + i_extendido;
endmodule
| 8.10442 |
module decode_alu (
// outputs
op1,
op2,
alu_sel,
// inputs
inst,
rs1,
rs2
);
output reg [31:0] op1, op2;
output reg [3:0] alu_sel;
input [31:0] inst, rs1, rs2;
// instruction slots
wire [ 6:0] opcode = inst[6:0];
wire [ 2:0] funct3 = inst[14:12];
wire [ 4:0] shamt = inst... | 6.70023 |
module Decode_base_tb #(
parameter INST_WIDTH = 16,
parameter DATA_WIDTH = 32,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = "",
parameter FETCH_DELAY = 3
) (
output wire done,
error
);
localparam ADDR_WIDTH = 4;
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
l... | 7.770405 |
module decode_block_mul_10ns_32s_41_3_Mul3S_2 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [10 - 1 : 0] a; // synthesis attribute keep a "true"
input [32 - 1 : 0] b; // synthesis attribute keep b "true"
output [41 - 1 : 0] p;
reg [10 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_re... | 6.863664 |
module decode_block_mul_10ns_32s_41_3 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] d... | 6.863664 |
module decode_block_mul_10s_32s_41_3_Mul3S_1 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [10 - 1 : 0] a; // synthesis attribute keep a "true"
input [32 - 1 : 0] b; // synthesis attribute keep b "true"
output [41 - 1 : 0] p;
reg signed [10 - 1 : 0] a_reg0;
reg signed [32 - 1 :... | 6.863664 |
module decode_block_mul_10s_32s_41_3 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] di... | 6.863664 |
module decode_block_mul_32s_32s_32_6_MulnS_0 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [32 - 1 : 0] a; // synthesis attribute keep a "true"
input [32 - 1 : 0] b; // synthesis attribute keep b "true"
output [32 - 1 : 0] p;
reg signed [32 - 1 : 0] a_reg0;
reg signed [32 - 1 :... | 6.863664 |
module decode_block_mul_32s_32s_32_6 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] di... | 6.863664 |
module decode_block_mul_8ns_32s_40_3_Mul3S_0 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [8 - 1 : 0] a; // synthesis attribute keep a "true"
input [32 - 1 : 0] b; // synthesis attribute keep b "true"
output [40 - 1 : 0] p;
reg [8 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_reg0;... | 6.863664 |
module decode_block_mul_8ns_32s_40_3 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] di... | 6.863664 |
module decode_block_mul_9ns_32s_41_3_Mul3S_3 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [9 - 1 : 0] a; // synthesis attribute keep a "true"
input [32 - 1 : 0] b; // synthesis attribute keep b "true"
output [41 - 1 : 0] p;
reg [9 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_reg0;... | 6.863664 |
module decode_block_mul_9ns_32s_41_3 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] di... | 6.863664 |
module decode_block_mux_20to1_sel5_32_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDT... | 6.863664 |
module decode_cb_rom (
opcode,
uc_addr
);
`include "ucode_consts.vh"
input wire [7:0] opcode;
output reg [UCODE_ADDR_LENGTH-1:0] uc_addr;
always @(*) begin
case (opcode)
`include "decode_cb.vh"
default: uc_addr = 0;
endcase
end
endmodule
| 7.840948 |
module decode_commands (
input protected_mode,
input dec_ready_one,
input dec_ready_one_one,
input dec_ready_one_two,
input dec_ready_one_three,
input dec_ready_2byte_one,
input dec_ready_modregrm_one,
input dec_ready_2byte_modregrm,
input dec_ready_call_jmp_imm,
input dec_read... | 6.692852 |
module top level
// Group 3
// Author: Ashan Shanaka Liyanage
// ashan8k@gmail.com
module decode_control # (
parameter REG_WIDTH=16)(
// System related ports
input wire clk, // clock
input wire rst, // reset active HIGH
// fetch related ports
input wire [15:0] i_16_data_mem2cpu,
input wire [REG_W... | 8.461556 |
module decode_dirty(instruction);
input [31:0] instruction;
reg [5:0] op_code;
reg [5:0] lsb;
reg [4:0] param2;
always @(instruction) begin
case(op_code)
6'b000000:case(lsb)
6'b000000:if(param2 == 5'b00000){
$display("nop");}
else{
$display("sll");
}
6'b000010:$display("srl");
6'b0... | 6.536369 |
module decode_ed_rom (
opcode,
uc_addr
);
`include "ucode_consts.vh"
input wire [7:0] opcode;
output reg [UCODE_ADDR_LENGTH-1:0] uc_addr;
always @(*) begin
case (opcode)
`include "decode_ed.vh"
default: uc_addr = 0;
endcase
end
endmodule
| 7.863112 |
module decode_execute ( // decode and execute
// from fetch
input [31 : 0] ir,
input [31 : 0] pc,
// from regfile
input [31 : 0] rs1_data,
input [31 : 0] rs2_data,
// from csr_file
input [31 : 0] csr_rdata,
// to regfile
output [4 : 0] rs1_num,
output [4 : 0] rs2_num,
... | 6.878014 |
module Decode_Execute_Reg (
clk,
rst_n,
stall_en,
rd1_in,
rd2_in,
rd1_out,
rd2_out,
sign_ext_in,
sign_ext_out,
dstReg_in,
dstReg_out,
srcReg1_in,
srcReg1_out,
srcReg2_in,
srcReg2_out,
is_LLB_or_LHB_in,
is_LLB_or_LHB_out,
is_PCS_in,
is_PCS_out
)... | 7.335422 |
module decode_field (
input clock,
input [31:0] instruction,
output reg [ 2:0] funct3,
output reg [ 6:0] funct7,
output [ 6:0] opcode,
output [ 4:0] rs1,
output [ 4:0] rs2,
output reg [ 4:0] rd,
output reg [31:0] immediate12_itype,
output reg [31:0] i... | 6.528313 |
module decode_func (
input wire [65:0] decoder_in_buffer,
output reg [71:0] decoder_func_out
);
wire [7:0] idle_or_error_lane_1;
wire [7:0] idle_or_error_lane_2;
wire [7:0] idle_or_error_lane_3;
wire [7:0] idle_or_error_lane_4;
wire [7:0] idle_or_error_lane_5;
wire [7:0] idle_or_error_lane_6;
w... | 6.671394 |
module decode_hex (
in,
HEX
);
input [3:0] in;
output reg [6:0] HEX;
always @(in) begin
case (in)
0: HEX = 7'b1000000;
1: HEX = 7'b1111001;
2: HEX = 7'b0100100;
3: HEX = 7'b0110000;
4: HEX = 7'b0011001;
5: HEX = 7'b0010010;
6: HEX = 7'b0000010;
7: HEX =... | 8.032663 |
module decode_hint (
input [71:0] raw_hint,
output valid_hint,
output [3:0] syscall_state,
output [1:0] mask,
output is_write,
output [31:0] address,
output [31:0] data
);
`include "funcs.v"
wire [7:0] meta = raw_hint[71:64];
assign mask = meta[1:0];
assign is_write = meta[2];
... | 8.585998 |
module decode_imm (
input wire [ 31:0] instruction,
input wire [ 3:0] select,
output wire [`REGSZ-1:0] out
);
reg [`REGSZ-1:0] outval;
assign out = outval;
always @(*) begin
case (select)
`DE_IMM_D: // And DE_IMM_SI
outval = {{(`REGSZ - 16) {instruction[15]}}, instruct... | 8.251014 |
module decode_initial_conf (
input [512-1:0] initial_conf,
output [ 64-1:0] num_data_in,
output [ 64-1:0] num_data_out,
output [ 32-1:0] num_cicles_to_store,
output [ 32-1:0] num_conf,
output [ 32-1:0] start_loop
);
assign num_data_in = initial_conf[63:0];
assign num_data_out = initial_con... | 7.797427 |
module decode_inst(input wire [31:0] instruction,
output wire [`DEC_SIGS_SIZE-1:0] decode_bundle
);
wire [4:0] INST_RA = instruction[20:16];
wire [4:0] INST_RB = instruction[15:11];
wire [4:0] INST_RT = instruct... | 6.872325 |
module decode_latch (
input wire [ 1:0] ctlwb_out,
input wire [ 2:0] ctlm_out,
input wire [ 3:0] ctlex_out,
input wire [31:0] npc,
readdat1,
readdat2,
signext_out,
input wire [ 4:0] instr_2016,
instr_1511,
output reg [ 1:0] wb_ctlout,
output reg [ 2:0] m_ctlout,
ou... | 6.580441 |
module decode_logic (
tas_in,
lu_out,
ld_out
);
//-----------------------------------------------
// Parameters and Definitions
//-----------------------------------------------
parameter tasw = `ADDR_WIDTH;
//-----------------------------------------------
// Input/Output Signals
//-------... | 6.901128 |
module decode_main (
input clk,
input [31:0] d_inst,
input d_regwr,
input [63:0] d_write_data,
input [5:0] d_wr_reg,
output [63:0] d_read_data1,
output [63:0] d_read_data2,
output d_alusrc,
output d_mem2reg,
output d_ctrl_regwr,
output d_memrd,
output d_memwr,
output ... | 6.715398 |
module decode_mux (
//output
output reg [4:0] rs2_out,
output reg [4:0] rd_out,
output reg reg_write_en_out,
output reg [2:0] wb_sel_out,
output reg mem_req_write_out,
output reg mem_req_type_out,
//input
input [4:0] rs2_in,
input [4:0] rd_in,
input reg_write_en_in,
inpu... | 7.808118 |
module Decode_new_tb;
// Inputs
reg clk;
reg [31:0] Instruction;
reg RegWrite;
reg [4:0] WriteReg;
reg [31:0] WriteData;
// Outputs
wire [5:0] Opcode;
wire [31:0] Read_Data_1;
wire [31:0] Read_Data_2;
wire [31:0] Sign_Extended_Immediate;
wire [4:0] rt;
wire [4:0] rd;
// Instantiate the Un... | 6.581349 |
module prefix_analyzer (
prefix_part,
segr_override,
operand_size_sel,
cs_rep, // cs_signal
cs_segr_index, // cs_signal
isPrefix_neg
);
input [7:0] prefix_part;
output operand_size_sel;
output segr_override;
output [2:0] cs_segr_index;
output cs_rep;
output isPrefix_neg; // 1: th... | 8.472021 |
module opcode_size_analyzer (
opcode_part,
opcode_size
);
input [7:0] opcode_part;
output opcode_size; //0: one byte 1: two byte
parameter TWO_OPCODE_MARKER = 8'h0F;
// compare the possible opcode with 0FH
cmp8b cmp_0 (
opcode_size,
opcode_part,
TWO_OPCODE_MARKER
);
endmodule
| 6.836989 |
module that can exact 8, or 32 bits according to the disp_size.
module literal_analyzer(
literal,
disp_sel,
disp_part,
imm_part
);
input [63:0] literal;
input [1:0] disp_sel;
output [31:0] disp_part;
output [31:0] imm_part;
wire [31:0] imm_part0;
wire [31:0] imm_pa... | 7.802636 |
module
//
//----------------------------------------
// stall/flush decode stage
// 1. other stage's stall flush signal
// 2. decode failed
module decode_stall_logic(
decode_failed,
other_stage_stall,
other_stage_flush,
F2D_valid,
upc_stall,
D2L_valid,
D2L_stall_n,
D2F_stall_n,
D2F_... | 6.557915 |
module decode_opc_phase1 (
input [87:0] unprefixed_instr,
output is_2byte,
output [87:0] unescaped_instr
);
assign is_2byte = (unprefixed_instr[7:0] == 8'h0F);
assign unescaped_instr = (is_2byte) ? ({8'd0, unprefixed_instr[87:8]}) : unprefixed_instr;
endmodule
| 7.145293 |
module decode_opc_phase2 (
input [87:0] unescaped_instr,
input is_2byte,
output [6:0] opc,
output [3:0] opnd_form,
output [1:0] opnd_count,
output imm_1byte,
output reg_1byte,
output opnd0_is_read,
output opnd0_is_write,
output opnd1_is_one,
output opnd1_is_read,
outpu... | 7.145293 |
module Decode_Pipe_Reg #(
parameter ins_width = 32
) (
input clk,
input en,
input reset,
input clr,
input [ins_width-1:0] in_instruction,
input [ins_width-1:0] pcplus4_in,
output reg [ins_width-1:0] ins_out,
output reg [ins_width-1:0] pcplus4_out
);
always @(posedge clk, negedge re... | 7.053718 |
module Decode_reg (
// input & output ports
input wire CLK,
input wire Reset,
input wire CLR,
input wire EN,
input wire [31:0] InstrF,
input wire [31:0] PcPlus4f,
output reg [31:0] InstrD,
output reg [31:0] PcPlus4D
);
always @(posedge CLK, nege... | 6.85489 |
module decode_regfile (
input [319:0] raw_regs,
output [31:0] eax,
output [31:0] ebx,
output [31:0] ecx,
output [31:0] edx,
output [31:0] esi,
output [31:0] edi,
output [31:0] esp,
output [31:0] ebp,
output [31:0] eip,
output [31:0] eflags
);
// NOTE(ww): Our register ord... | 8.362712 |
module Decode_Register (
input wire [31:0] rd,
pcPlus4F,
input wire clk,
en,
clear,
rst,
output reg [31:0] instrD,
pcPlus4D
);
always @(posedge clk or negedge rst) begin
if (!rst) begin
instrD <= 32'b0;
pcPlus4D <= 32'b0;
end else if (clear & !en) begin... | 7.386151 |
module Decode_rx (
// input ports
DeScr_RXD,
blk_lock,
bypass_66decoder,
lpbk,
clear_errblk,
clk156,
hi_ber,
rstb156,
terminate_in,
// output ports
rxlf,
errd_blks,
rxcontrol,
rxdata,
terminate_out
);
// input ports
input [65:0] DeScr_RXD;
wire [... | 7.199923 |
module decode_show (
data,
SEG
);
input [3:0] data;
output reg [7:0] SEG;
always @(data) begin
case (data[3:0])
4'b0000: SEG[7:0] = 8'b11000000;
4'b0001: SEG[7:0] = 8'b11111001;
4'b0010: SEG[7:0] = 8'b10100100;
4'b0011: SEG[7:0] = 8'b10110000;
4'b0100: SEG[7:0] = 8'b10011... | 7.302746 |
module tb;
parameter word_size = 32;
parameter reg_size = 5;
parameter opcode_size = 6;
wire [3:0] ex_control_signals;
wire [2:0] mem_control_signals;
wire [1:0] wb_control_signals;
wire [word_size-1:0] PC_out, ReadData1, ReadData2, sign_extend_out;
wire [reg_size-1:0] rt, rd;
reg [word_size-1:0] PC... | 6.612288 |
module: decode
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decode_stage_test;
// Inputs
reg clk;
reg [15:0] instruction;
reg [15:0] write_data;
reg [2:0] write_reg;
reg re... | 6.50658 |
module Decode_t ();
reg clk, rst;
reg [10:0] clkCount;
wire Stall, DivStall, NotBranchOrJump, WrRegEn, ZeroExtend8, NextPCSel, BranchImmedSel;
wire LoadR7, DataOut2Sel, Branch, Jump, AddMode, ZeroB, FlagMux, WrMemEn, MemToReg;
wire [1:0] WrMuxSel, SignExtSel, SetFlagD, ShiftMode, SetFlagE, AOp;
wire [2:0]... | 6.792425 |
module: Decode
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Decode_tb;
// Inputs
reg clk;
reg [31:0] Instruction;
reg RegWrite;
// Outputs
wire [5:0] Opcode;
wire [31:0] ... | 6.646322 |
module decode_tbdec (
input wire clk,
input wire reset,
input wire write_tbl,
input wire write_tbu,
input wire write_dec,
input wire [31:0] write_val,
output wire [63:0] tb,
output wire [31:0] dec,
output wire dec_trigger
);
reg [63:0] as_TB /*verila... | 7.983138 |
module. Prints data in CSV format.
//
//////////////////////////////////////////////////////////////////////////////////
`ifndef DECODE_TESTBENCH
`define DECODE_TESTBENCH
`include "../component/control_store.v"
`include "../component/reg_file.v"
`include "../decode_stage.v"
module DecodeTestbench;
reg clk;
... | 6.647622 |
module Decode_to_Execute_Register #(
parameter ALU_Control_width = 3,
Rs_width = 5,
Rt_width = 5,
Rd_width = 5,
WIDTH = 32,
SignImm_width = 32
) (
input wire CLK,
RST,
CLR,
input wire MemWriteD,
input wire ... | 7.007463 |
module decode_unit_input_reg (
input clk,
rstn,
flush,
input input_valid_in,
input [31:0] inst0_in,
inst1_in,
input known0_in,
known1_in,
input [31:0] pred_record0_in,
pred_record1_in,
input first_inst_jmp_in,
input [6:0] exception_in,
input [31:0] badv_in,
input... | 6.566459 |
module decode (
input wire [31:0] pc,
input wire [31:0] instruction,
input wire clk,
input wire dec_en,
input wire [31:0] data_in,
output wire [31:0] out_s1,
output wire [31:0] out_s2,
output wire [ 4:0] sa,
output wire [15:0] im,
output wire [ 4:0] base,
out... | 7.887076 |
module decode_writeback (
clk,
icode,
rA,
rB,
valE,
valM,
valA,
valB
);
parameter n = 64;
input clk;
input [3:0] icode;
input [3:0] rA;
input [3:0] rB;
input [n-1:0] valE, valM;
output reg [n-1:0] valA;
output reg [n-1:0] valB;
integer i;
reg [n-1:0] reg_data[0:14... | 7.089229 |
module decode_writeback_pipe (
clk,
d_icode,
d_rA,
d_rB,
w_valE,
w_valM,
d_valA,
d_valB,
e_rA,
e_rB,
m_rA,
m_rB,
w_rA,
w_rB,
e_valE,
m_valE,
m_valM
);
parameter n = 64;
input clk;
input [3:0] d_icode;
input [3:0] d_rA, e_rA, m_rA, w_rA;
inpu... | 7.089229 |
module decode_writeback_test; // Ask TA why some things work while others don't
parameter n = 64;
reg clk;
reg [3:0] icode;
reg [3:0] rA, rB;
reg [n-1:0] valE, valM;
wire [n-1:0] valA, valB;
integer j;
decode_writeback m1 (
clk,
icode,
rA,
rB,
valE,
valM,
v... | 7.089229 |
module decode_xybits_rom (
opcode,
uc_addr
);
`include "ucode_consts.vh"
input wire [7:0] opcode;
output reg [UCODE_ADDR_LENGTH-1:0] uc_addr;
always @(*) begin
case (opcode)
`include "decode_xybits.vh"
default: uc_addr = 0;
endcase
end
endmodule
| 8.503596 |
module decode_xy_rom (
opcode,
uc_addr
);
`include "ucode_consts.vh"
input wire [7:0] opcode;
output reg [UCODE_ADDR_LENGTH-1:0] uc_addr;
always @(*) begin
case (opcode)
`include "decode_xy.vh"
default: uc_addr = 0;
endcase
end
endmodule
| 7.995412 |
module Decodificador1 (
input [3:0] bin,
output [6:0] display
);
assign display = (bin == 4'b0000) ? 7'b0110111 : //0
(bin == 4'b0001) ? 7'b1001111 : //1
(bin == 4'b0010) ? 7'b0010010 : //2
(bin == 4'b0011) ? 7'b0000110 : //3
(bin == 4'b0100) ? 7'b1001100 : //4
(bin == 4'b... | 7.125935 |
module decodificadorDisplay (
A,
B,
C,
D,
a,
b,
c,
d,
e,
f,
g
);
input A, B, C, D;
output a, b, c, d, e, f, g;
reg [6:0] segmentos;
always @(*)
if ({A, B, C, D} == 4'b0000) begin
segmentos = 7'b0000001;
end else if ({A, B, C, D} == 4'b0001) begin
... | 6.55702 |
module decodificadorONOFF (
number,
display
);
input [3:0] number;
output reg [0:6] display;
always @(number) begin
case (number)
1: display <= 7'b1111110;
0: display <= 7'b0000001;
endcase
end
endmodule
| 6.55702 |
module decodificador_deGray (
input clk, //100 MHz
input reset, //Entrada del boton
input [3:0] a, //Entrada de los conmutadores
output [3:0] led,
output reg led_reset,
output [7:0] anodo,
output [6:0] catodos
);
wire [3:0] bin;
//Encender un LED para indicar el funcionamiento del r... | 6.55702 |
module decodificador_tb ();
reg [3:0] sec_ones_tb;
reg [3:0] sec_tens_tb;
reg [3:0] min_tb;
wire [6:0] sec_ones_segs_tb;
wire [6:0] sec_tens_segs_tb;
wire [6:0] min_segs_tb;
decodificador DUT (
.sec_ones(sec_ones_tb),
.sec_tens(sec_tens_tb),
.min(min_tb),
.sec_ones_segs(sec_one... | 6.55702 |
module decodificaReg (
W,
En,
Y
);
/***************************************************************************
* Decodificador responsavel por receber o numero do registrador escolhido
* pela instrucao e emitir um sinal que possibilite a selecao da saida deste
* pelo multiplexador
******************... | 8.827075 |
module decodingStage (
input clk,
input reset,
input [2:0] write_addr,
input [15:0] write_data,
input [15:0] instruction,
output mem_read_buf,
output mem_write_buf,
// buffering for memory stage
output mem_read_buf2,
output mem_write_buf2,
output mem_read_buf3,
output [1... | 7.129871 |
module DecodingUnit (
input [31:0] Instr_ID,
output DU_rs1_valid,
output DU_rs2_valid,
output [4:0] DU_rs1,
output [4:0] DU_rs2,
output [4:0] DU_rd,
output DU_memread,
output DU_memwrite,
output DU_regwrite,
output DU_j,
output DU_br,
output DU_jalr,
output DU_sub,
... | 6.782755 |
module to decode and display
module BCD7 (din,dout);
input [3:0] din;
output [6:0] dout;
assign dout=(din==4'd0)?7'b1000000:
(din==4'd1)?7'b1111001:
(din==4'd2)?7'b0100100:
(din==4'd3)?7'b0110000:
(din==4'd4)?7'b0011001:
(din==4'd5)?7'b001001... | 7.193226 |
module Decoding_diplay (
out0,
out1,
out2,
out3,
Hex0,
Hex1,
Hex2,
Hex3
);
input [3:0] out0, out1, out2, out3;
output [6:0] Hex0, Hex1, Hex2, Hex3;
BCD7 hex0 (
.din (out0),
.dout(Hex0)
);
BCD7 hex1 (
.din (out1),
.dout(Hex1)
);
BCD7 hex2 (
.d... | 7.447179 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/decod_comb/decod_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
n_pad,
o_pad,
p_pad,
q_pad,
r_pad,... | 6.939825 |
module decofdificador_cs_registros (
input [2:0] funcion_conf,
input wire flag_mostrar_count,
output reg cs_seg_hora,
output reg cs_min_hora,
output reg cs_hora_hora,
output reg cs_dia_fecha,
output reg cs_mes_fecha,
output reg cs_jahr_fecha,
output reg cs_dia_semana,
output reg ... | 6.563408 |
module decompose2 #(
parameter A_width = 16,
parameter B_width = 16
) (
input CLK,
input [ A_width - 1 : 0] A,
input [ B_width - 1 : 0] B,
output reg [A_width+B_width-1:0] PRODUCT
);
localparam width = A_width + B_width;
reg [width - 1 : 0] temp_a;
... | 6.872415 |
module decompose2_pipeline #(
parameter A_width = 16,
parameter B_width = 16
) (
input CLK,
input [ A_width - 1 : 0] A,
input [ B_width - 1 : 0] B,
output reg [A_width+B_width-1:0] PRODUCT
);
localparam width = A_width + B_width;
reg [width - 1 : 0]... | 6.851202 |
module decompose3 #(
parameter width = 16
) (
input CLK,
input [width-1:0] A,
output reg [width-1:0] PRODUCT
);
reg [width - 1 : 0] temp_a;
reg [width - 1 : 0] temp_b;
parameter angle_width = width;
parameter sin_width = width;
parameter cos_width = width;
`include "D... | 7.217965 |
module decompose3_pipeline #(
parameter width = 16
) (
input CLK,
input [width-1:0] A,
output reg [width-1:0] PRODUCT
);
reg [width - 1 : 0] temp_a;
reg [width - 1 : 0] temp_b;
parameter angle_width = width;
parameter sin_width = width;
parameter cos_width = width;
`i... | 7.747945 |
module decomposer_sim ();
reg clk;
reg rst;
reg [2:0] sec_lvl;
reg valid_i;
reg ready_o;
wire ready_i;
wire valid_o;
parameter SEC_LVL_0 = 3'b000;
parameter SEC_LVL_2 = 3'b010;
parameter OUTPUT_W = 4;
parameter COEFF_W = 24;
reg [OUTPUT_W*COEFF_W - ... | 6.784579 |
module decomposer_unit #(
parameter OUTPUT_W = 4,
parameter COEFF_W = 24
) (
input rst,
input clk,
input [2:0] sec_lvl,
input valid_i,
output ready_i,
input [OUTPUT_W*COEFF_W-1:0] di,
output [OUTPUT_W*COEFF_W-1:0] doa,
output [OUTPUT_W*COEFF_W-1:0] dob,
output valid_o,
i... | 6.984429 |
module decompress (
in1,
in2,
out,
byteIndx,
bitIndx,
done,
work
);
output [3:0] bitIndx;
output [31:0] byteIndx;
output done;
output [7:0] out;
input [2:0] in1;
input [2:0] in2;
input work;
wire n_0_0_1;
wire n_0_0_0;
wire n_0_0_2;
wire n_0_2;
wire n_0_0;
wire n_0... | 6.64264 |
module decompress (
in1,
in2,
out,
byteIndx,
bitIndx,
done,
work
);
input [7:0] in1, in2;
output done;
output [255:0] out;
output [31:0] byteIndx;
output [3:0] bitIndx;
integer c;
integer rep;
integer currValue;
integer rep2;
integer currValue2;
reg [255:0] tempOut;
... | 6.64264 |
module decomp_top (
input aclk,
input aresetn,
input [255:0] tdata_fifo,
input [ 31:0] tkeep_fifo,
input tvalid_fifo,
input tlast_fifo,
output reg tready_fifo,
output reg [255:0] tdata_dma,
output reg [ 31:0] tkeep_dma,
output reg ... | 6.581987 |
module pip_1 (
input aclk,
input [255:0] data_in,
input [31:0] keep_in,
input last_in,
input valid_in,
input ready_control,
output reg [255:0] data_out,
output reg [31:0] keep_out,
output reg last_out,
output reg valid_out
);
always @(posedge aclk) begin
if (ready_contr... | 6.936335 |
module DECOMPRESSOR #(
parameter NUM_PATTERNS = 8,
parameter NUM_FIRST_TRANSFORMER = 2,
parameter NUM_LAST_TRANSFORMER = 6,
parameter NUM_TRANSFORMER = NUM_LAST_TRANSFORMER - NUM_FIRST_TRANSFORMER + 1,
parameter NUM_MODULES = NUM_PATTERNS - 1,
parameter LEN_ENCODE = $c... | 7.201582 |
module decompressor_wrapper (
input clk,
input rst_n,
output last, // Whether the data is the last one in a burst
output done, // Whether the decompression is done
input start, // Start the decompressor after the compression_length and decompression_length is set
// The user sh... | 7.759808 |
module decompress (
in1,
in2,
out,
byteIndx,
bitIndx,
done,
work
);
input [2:0] in1;
input [2:0] in2;
output [7:0] out;
output [31:0] byteIndx;
output [3:0] bitIndx;
output done;
input work;
wire n_0_0_1;
wire n_0_0_0;
wire n_0_0_2;
wire n_0_2;
wire n_0_0;
wire n_0... | 6.64264 |
module decompress (
in1,
in2,
out,
byteIndx,
bitIndx,
done,
work
);
input [2:0] in1, in2;
output done;
output [7:0] out;
output [31:0] byteIndx;
output [3:0] bitIndx;
integer c;
integer rep;
integer currValue;
integer rep2;
integer currValue2;
reg [7:0] tempOut;
in... | 6.64264 |
module DECOMP_TOP (
input wire rst_n,
input wire clk,
input wire [63:0] data_i,
input wire valid_i,
input wire ready_i,
input wire sop_i,
input wire eop_i,
output wire [63:0] data_o,
output wire valid_o,
output wire ready_o,
output wire sop_o,
output wire eop_o
);
reg... | 6.524911 |
module Decording_the_world (
input [1:0] SEG_SELECT_IN,
input [3:0] BIN_IN,
input DOT_IN,
output reg [3:0] SEG_SELECT_OUT,
output reg [7:0] HEX_OUT
);
//segment sellection case statement
always @(SEG_SELECT_IN) begin
case (SEG_SELECT_IN)
2'b00: SEG_SELECT_OUT <= 4'b1110;
2'b0... | 7.487069 |
module SlowDecoupledAdder(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [15:0] io_in_bits_a,
input [15:0] io_in_bits_b,
input io_out_ready,
output io_out_valid,
output [15:0] io_out_bits_c
);
`ifdef RANDOMIZE_REG_INIT
reg [31:... | 6.565178 |
module Decov2 (
input [8:0] i_Instruction,
output reg [2:0] ControlJump,
output reg [2:0] Sel_Mux,
output reg [2:0] Sel_RY,
output reg [2:0] Sel_RX,
output reg Load_Store,
output reg [3:0] Sel_ALU,
output reg [1:0] Sel_Salidas
);
always @(i_Instruction) begin
case (i_Instruction[... | 7.354767 |
module Deco_Display (
input [3:0] In_Num,
output reg [7:0] Out_Cod
);
always @* begin
case (In_Num)
4'b0000: Out_Cod <= 8'b00000011;
4'b0001: Out_Cod <= 8'b10011111;
4'b0010: Out_Cod <= 8'b00100101;
4'b0011: Out_Cod <= 8'b00001101;
4'b0100: Out_Cod <= 8'b10011001;
4'b0... | 8.25283 |
module Deco_Round_Mult (
input wire [1:0] round_mode,
input wire or_info, //23 less significant bits from the product of significands
input wire xor_info, //Brings information about the sign of the operation
output reg ctrl //control signal mux --- control of the rounded significand
);
always @*
... | 7.607402 |
module decrease #(
parameter DATA_SIZE = 8
) (
input [DATA_SIZE-1:0] in,
output [DATA_SIZE-1:0] out
);
reg [DATA_SIZE-1:0] outReg;
assign out = outReg;
always @* begin
outReg = in - 1;
end
endmodule
| 8.767832 |
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