code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Add4_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
input CIN
);
wire bit_const_0_None_out;
wire [3:0] coreir_add4_inst0_out;
wire [3:0] coreir_add4_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(4)
) coreir_ad... | 7.761374 |
module Add4_cout_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT,
input CIN
);
wire [4:0] coreir_add5_inst0_out;
assign coreir_add5_inst0_out = 5'((5'(({1'b0,1'b0,1'b0,1'b0,CIN}) + ({1'b0,I0}))) + ({1'b0,I1}));
assign O = coreir_add5_inst0_out[3:0];
assign COUT = coreir_add... | 8.467947 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add4_cout_cin (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT,
input CIN
);
wire bit_const_0_None_out;
wire [4:0] coreir_add5_inst0_out;
wire [4:0] coreir_add5_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [4:0] coreir_add... | 8.467947 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN_COUT (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.712749 |
module Add4_cin_cout (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire L... | 7.275542 |
module Add4_cin_cout (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2... | 7.275542 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
Ful... | 7.507677 |
module Add4_cin (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire MU... | 7.761374 |
module Add4_cin (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_ins... | 7.761374 |
module coreir_add4_wrapped (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
assign O = 4'(I0 + I1);
endmodule
| 8.166782 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module coreir_add4_wrapped (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire [3:0] coreir_add4_inst0_out;
coreir_add #(
.width(4)
) coreir_add4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_add4_inst0_out)
);
assign O = coreir_add4_inst0_out;
endmodule
| 8.166782 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire [4:0] coreir_add5_inst0_out;
assign coreir_add5_inst0_out = 5'(({1'b0, I0}) + ({1'b0, I1}));
assign O = coreir_add5_inst0_out[3:0];
assign COUT = coreir_add5_inst0_out[4];
endmodule
| 7.542776 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire bit_const_0_None_out;
wire [4:0] coreir_add5_inst0_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [4:0] coreir_add5_inst0_in0;
assign coreir_add5_inst0_in0 = {bit_cons... | 7.542776 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_COUT (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
... | 8.082367 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire... | 7.542776 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_... | 7.542776 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
input CIN
);
assign O = 8'((8'(({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, CIN}) + I0)) + I1);
endmodule
| 8.416699 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add8_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
input CIN
);
wire bit_const_0_None_out;
wire [7:0] coreir_add8_inst0_out;
wire [7:0] coreir_add8_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(8)
) coreir_ad... | 8.416699 |
module Add8_cout_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT,
input CIN
);
wire [8:0] coreir_add9_inst0_out;
assign coreir_add9_inst0_out = 9'((9'(({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CIN}) + ({1'b0,I0}))) + ({1'b0,I1}));
assign O = coreir_add9_inst0_out[7:0];
assi... | 8.324529 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add8_cout_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT,
input CIN
);
wire bit_const_0_None_out;
wire [8:0] coreir_add9_inst0_out;
wire [8:0] coreir_add9_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [8:0] coreir_add... | 8.324529 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN_COUT (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.252533 |
module Add8_cin_cout (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire L... | 7.334727 |
module Add8_cin_cout (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2... | 7.334727 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
wir... | 7.601983 |
module Add8_cin (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire MU... | 8.416699 |
module Add8_cin (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_ins... | 8.416699 |
module coreir_add8_wrapped (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
assign O = 8'(I0 + I1);
endmodule
| 7.827716 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module coreir_add8_wrapped (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire [7:0] coreir_add8_inst0_out;
coreir_add #(
.width(8)
) coreir_add8_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_add8_inst0_out)
);
assign O = coreir_add8_inst0_out;
endmodule
| 7.827716 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire [8:0] coreir_add9_inst0_out;
assign coreir_add9_inst0_out = 9'(({1'b0, I0}) + ({1'b0, I1}));
assign O = coreir_add9_inst0_out[7:0];
assign COUT = coreir_add9_inst0_out[8];
endmodule
| 7.265928 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire bit_const_0_None_out;
wire [8:0] coreir_add9_inst0_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [8:0] coreir_add9_inst0_in0;
assign coreir_add9_inst0_in0 = {bit_cons... | 7.265928 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_COUT (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
... | 7.479272 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire... | 7.265928 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_... | 7.265928 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module and2_wrapped (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
assign O = I0 & I1;
endmodule
| 8.243053 |
module coreir_and #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 & in1;
endmodule
| 8.205177 |
module and2_wrapped (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire [1:0] and2_inst0_out;
coreir_and #(
.width(2)
) and2_inst0 (
.in0(I0),
.in1(I1),
.out(and2_inst0_out)
);
assign O = and2_inst0_out;
endmodule
| 8.243053 |
module And2 (
input [1:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
assign O = {And2_inst1_O, And2_inst0_O};
endmodu... | 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
assign O = {And2_inst1_O, And2_inst0_O};
endmodu... | 7.314391 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
assign O = {And2_inst1_O, And2_inst0_O};
endmodu... | 7.314391 |
module and4_wrapped (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
assign O = I0 & I1;
endmodule
| 8.170652 |
module coreir_and #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 & in1;
endmodule
| 8.205177 |
module and4_wrapped (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire [3:0] and4_inst0_out;
coreir_and #(
.width(4)
) and4_inst0 (
.in0(I0),
.in1(I1),
.out(and4_inst0_out)
);
assign O = and4_inst0_out;
endmodule
| 8.170652 |
module And2 (
input [1:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
wire And2_inst2_O;
wire And2_inst3_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
And2 A... | 7.022857 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
wire And2_inst2_O;
wire And2_inst3_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
And2 A... | 7.022857 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
wire And2_inst2_O;
wire And2_inst3_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
And2 A... | 7.022857 |
module and8_wrapped (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
assign O = I0 & I1;
endmodule
| 8.017465 |
module coreir_and #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 & in1;
endmodule
| 8.205177 |
module and8_wrapped (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire [7:0] and8_inst0_out;
coreir_and #(
.width(8)
) and8_inst0 (
.in0(I0),
.in1(I1),
.out(and8_inst0_out)
);
assign O = and8_inst0_out;
endmodule
| 8.017465 |
module And2 (
input [1:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.880137 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
assign O = {&({I3[1], I2[1], I1[1], I0[1]}), &({I3[0], I2[0], I1[0], I0[0]})};
endmodule
| 6.971612 |
module coreir_andr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = ∈
endmodule
| 8.06584 |
module And4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire andr_inst0_out;
wire andr_inst1_out;
wire [3:0] andr_inst0_in;
assign andr_inst0_in = {I3[0], I2[0], I1[0], I0[0]};
coreir_andr #(
.width(4)
) andr_inst0 (
.in (andr_ins... | 6.971612 |
module And4 (
input [3:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8000)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.444531 |
module And4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire And4_inst0_O;
wire And4_inst1_O;
And4 And4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(And4_inst0_O)
);
And4 And4_inst1 (
.I({I3[1], I2[1], I1[1], I0[1]}),
.O... | 6.971612 |
module And4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h8000)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 7.444531 |
module And4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire And4_inst0_O;
wire And4_inst1_O;
And4 And4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(And4_inst0_O)
);
And4 And4_inst1 (
.I({I3[1], I2[1], I1[1], I0[1]}),
.O... | 6.971612 |
module And4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h8000)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 7.444531 |
module And4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire And4_inst0_O;
wire And4_inst1_O;
And4 And4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(And4_inst0_O)
);
And4 And4_inst1 (
.I({I3[1], I2[1], I1[1], I0[1]}),
.O... | 6.971612 |
module And4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
assign O = {
&({I3[3], I2[3], I1[3], I0[3]}),
&({I3[2], I2[2], I1[2], I0[2]}),
&({I3[1], I2[1], I1[1], I0[1]}),
&({I3[0], I2[0], I1[0], I0[0]})
};
endmodule
| 6.737413 |
module coreir_andr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = ∈
endmodule
| 8.06584 |
module And4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
wire andr_inst0_out;
wire andr_inst1_out;
wire andr_inst2_out;
wire andr_inst3_out;
wire [3:0] andr_inst0_in;
assign andr_inst0_in = {I3[0], I2[0], I1[0], I0[0]};
coreir_andr #(
... | 6.737413 |
module And4 (
input [3:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8000)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.444531 |
module And4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
wire And4_inst0_O;
wire And4_inst1_O;
wire And4_inst2_O;
wire And4_inst3_O;
And4 And4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(And4_inst0_O)
);
And4 And4_inst1 (
... | 6.737413 |
module And4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h8000)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 7.444531 |
module And4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
wire And4_inst0_O;
wire And4_inst1_O;
wire And4_inst2_O;
wire And4_inst3_O;
And4 And4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(And4_inst0_O)
);
And4 And4_inst1 (
... | 6.737413 |
module And4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h8000)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 7.444531 |
module And4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
wire And4_inst0_O;
wire And4_inst1_O;
wire And4_inst2_O;
wire And4_inst3_O;
And4 And4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(And4_inst0_O)
);
And4 And4_inst1 (
... | 6.737413 |
module coreir_andr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = ∈
endmodule
| 8.06584 |
module And4 (
input [3:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8000)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.444531 |
module And4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h8000)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 7.444531 |
module And4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h8000)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 7.444531 |
module And8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
assign O = {
&({I7[1], I6[1], I5[1], I4[1], I3[1], I2[1], I1[1], I0[1]}),
&({I7[0], I6[0], I5[0], I4[0],... | 7.035489 |
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