code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_COUT (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
... | 8.082367 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
wire SB_DFF_inst2_Q;
wire SB_DFF_inst3_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_D... | 7.403606 |
module Counter4_COUT (output [3:0] O, output COUT, input CLK);
wire [3:0] Add4_COUT_inst0_O;
wire Add4_COUT_inst0_COUT;
wire [3:0] Register4_inst0_O;
Add4_COUT Add4_COUT_inst0 (.I0(Register4_inst0_O), .I1(4'd1'), .O(Add4_COUT_inst0_O), .COUT(Add4_COUT_inst0_COUT));
Register4 Register4_inst0 (.I(Add4_COUT_inst0_O), .... | 7.925226 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire... | 7.542776 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
... | 7.403606 |
module Counter4_COUT (output [3:0] O, output COUT, input CLK);
wire [3:0] Add4_cout_inst0_O;
wire Add4_cout_inst0_COUT;
wire [3:0] Register4_inst0_O;
Add4_cout Add4_cout_inst0 (.I0(Register4_inst0_O), .I1(4'd1'), .O(Add4_cout_inst0_O), .COUT(Add4_cout_inst0_COUT));
Register4 Register4_inst0 (.I(Add4_cout_inst0_O), .... | 7.925226 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_... | 7.542776 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
... | 7.403606 |
module Counter4_COUT (output [3:0] O, output COUT, input CLK);
wire [3:0] Add4_cout_inst0_O;
wire Add4_cout_inst0_COUT;
wire [3:0] Register4_inst0_O;
Add4_cout Add4_cout_inst0 (.I0(Register4_inst0_O), .I1(4'd1'), .O(Add4_cout_inst0_O), .COUT(Add4_cout_inst0_COUT));
Register4 Register4_inst0 (.I(Add4_cout_inst0_O), .... | 7.925226 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire [8:0] coreir_add9_inst0_out;
assign coreir_add9_inst0_out = 9'(({1'b0, I0}) + ({1'b0, I1}));
assign O = coreir_add9_inst0_out[7:0];
assign COUT = coreir_add9_inst0_out[8];
endmodule
| 7.265928 |
module Counter8_COUT (
output [7:0] O,
output COUT,
input CLK
);
wire [7:0] Add8_cout_inst0_O;
Add8_cout Add8_cout_inst0 (
.I0(O),
.I1(8'h01),
.O(Add8_cout_inst0_O),
.COUT(COUT)
);
coreir_reg #(
.clk_posedge(1'b1),
.init(8'h00),
.width(8)
) reg_P_inst0 (
... | 7.314885 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire bit_const_0_None_out;
wire [8:0] coreir_add9_inst0_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [8:0] coreir_add9_inst0_in0;
assign coreir_add9_inst0_in0 = {bit_cons... | 7.265928 |
module Counter8_COUT (
output [7:0] O,
output COUT,
input CLK
);
wire [7:0] Add8_cout_inst0_O;
wire Add8_cout_inst0_COUT;
wire [7:0] const_1_8_out;
wire [7:0] reg_P_inst0_out;
Add8_cout Add8_cout_inst0 (
.I0(reg_P_inst0_out),
.I1(const_1_8_out),
.O(Add8_cout_inst0_O),
.COUT... | 7.314885 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_COUT (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
... | 7.479272 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
wire SB_DFF_inst2_Q;
wire SB_DFF_inst3_Q;
wire SB_DFF_inst4_Q;
wire SB_DFF_inst5_Q;
wire SB_DFF_inst6_Q;
wire SB_DFF_inst7_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
... | 6.73316 |
module Counter8_COUT (output [7:0] O, output COUT, input CLK);
wire [7:0] Add8_COUT_inst0_O;
wire Add8_COUT_inst0_COUT;
wire [7:0] Register8_inst0_O;
Add8_COUT Add8_COUT_inst0 (.I0(Register8_inst0_O), .I1(8'd1'), .O(Add8_COUT_inst0_O), .COUT(Add8_COUT_inst0_COUT));
Register8 Register8_inst0 (.I(Add8_COUT_inst0_O), .... | 7.314885 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire... | 7.265928 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
wire FDRSE_inst4_Q;
wire FDRSE_inst5_Q;
wire FDRSE_inst6_Q;
wire FDRSE_inst7_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
... | 6.73316 |
module Counter8_COUT (output [7:0] O, output COUT, input CLK);
wire [7:0] Add8_cout_inst0_O;
wire Add8_cout_inst0_COUT;
wire [7:0] Register8_inst0_O;
Add8_cout Add8_cout_inst0 (.I0(Register8_inst0_O), .I1(8'd1'), .O(Add8_cout_inst0_O), .COUT(Add8_cout_inst0_COUT));
Register8 Register8_inst0 (.I(Add8_cout_inst0_O), .... | 7.314885 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_... | 7.265928 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
wire FDRSE_inst4_Q;
wire FDRSE_inst5_Q;
wire FDRSE_inst6_Q;
wire FDRSE_inst7_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
... | 6.73316 |
module Counter8_COUT (output [7:0] O, output COUT, input CLK);
wire [7:0] Add8_cout_inst0_O;
wire Add8_cout_inst0_COUT;
wire [7:0] Register8_inst0_O;
Add8_cout Add8_cout_inst0 (.I0(Register8_inst0_O), .I1(8'd1'), .O(Add8_cout_inst0_O), .COUT(Add8_cout_inst0_COUT));
Register8 Register8_inst0 (.I(Add8_cout_inst0_O), .... | 7.314885 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Mux2x2 (
input [1:0] I0,
input [1:0] I1,
input S,
output [1:0] O
);
reg [1:0] coreir_commonlib_mux2x2_inst0_out;
always @(*) begin
if (S == 0) begin
coreir_commonlib_mux2x2_inst0_out = I0;
end else begin
coreir_commonlib_mux2x2_inst0_out = I1;
end
end
assign O = c... | 7.444141 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse DFF_init0_has_ceFalse_has_resetFalse_... | 6.626169 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire [2:0] coreir_add3_inst0_out;
assign coreir_add3_inst0_out = 3'(({1'b0, I0}) + ({1'b0, I1}));
assign O = coreir_add3_inst0_out[1:0];
assign COUT = coreir_add3_inst0_out[2];
endmodule
| 6.529797 |
module CounterLoad2_COUT (
input [1:0] DATA,
input LOAD,
output [1:0] O,
output COUT,
input CLK
);
wire [1:0] Add2_cout_inst0_O;
wire [1:0] Mux2x2_inst0_O;
Add2_cout Add2_cout_inst0 (
.I0(O),
.I1(2'h1),
.O(Add2_cout_inst0_O),
.COUT(COUT)
);
Mux2x2 Mux2x2_inst0 (
... | 8.102846 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module commonlib_muxn__N2__width2 (
input [1:0] in_data[1:0],
input [0:0] in_sel,
output [1:0] out
);
wire [1:0] _join_out;
coreir_mux #(
.width(2)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2x2 (
input [1:0] I0,
input [1:0] I1,
input S,
output [1:0] O
);
wire [1:0] coreir_commonlib_mux2x2_inst0_out;
wire [1:0] coreir_commonlib_mux2x2_inst0_in_data[1:0];
assign coreir_commonlib_mux2x2_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x2_inst0_in_data[0] = I0;
commonlib_... | 7.444141 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse DFF_init0_has_ceFalse_has_resetFalse_... | 6.626169 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire bit_const_0_None_out;
wire [2:0] coreir_add3_inst0_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [2:0] coreir_add3_inst0_in0;
assign coreir_add3_inst0_in0 = {bit_cons... | 6.529797 |
module CounterLoad2_COUT (
input [1:0] DATA,
input LOAD,
output [1:0] O,
output COUT,
input CLK
);
wire [1:0] Add2_cout_inst0_O;
wire Add2_cout_inst0_COUT;
wire [1:0] Mux2x2_inst0_O;
wire [1:0] Register2_inst0_O;
wire [1:0] const_1_2_out;
Add2_cout Add2_cout_inst0 (
.I0(Register2_i... | 8.102846 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_COUT (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(1'b0),
.O(FullAdder_inst0_O),... | 7.301465 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module Mux2x2 (
input [1:0] I0,
input [1:0] I1,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I1[1], I0[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = ... | 7.444141 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_DFF_inst1_Q)
);
assign O = {SB_DFF_inst1_Q,... | 6.626169 |
module CounterLoad2_COUT (input [1:0] DATA, input LOAD, output [1:0] O, output COUT, input CLK);
wire [1:0] Add2_COUT_inst0_O;
wire Add2_COUT_inst0_COUT;
wire [1:0] Mux2x2_inst0_O;
wire [1:0] Register2_inst0_O;
Add2_COUT Add2_COUT_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_COUT_inst0_O), .COUT(Add2_COUT_ins... | 8.102846 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
LUT2 #(
.INIT(4'h6)
) LUT2_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.O (L... | 6.529797 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x2 (
input [1:0] I0,
input [1:0] I1,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I1[1], I0[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = ... | 7.444141 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module CounterLoad2_COUT (input [1:0] DATA, input LOAD, output [1:0] O, output COUT, input CLK);
wire [1:0] Add2_cout_inst0_O;
wire Add2_cout_inst0_COUT;
wire [1:0] Mux2x2_inst0_O;
wire [1:0] Register2_inst0_O;
Add2_cout Add2_cout_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_cout_inst0_O), .COUT(Add2_cout_ins... | 8.102846 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
LUT6_2 #(
.INIT(64'h66666666AA... | 6.529797 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x2 (
input [1:0] I0,
input [1:0] I1,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I1[1], I0[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = ... | 7.444141 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module CounterLoad2_COUT (input [1:0] DATA, input LOAD, output [1:0] O, output COUT, input CLK);
wire [1:0] Add2_cout_inst0_O;
wire Add2_cout_inst0_COUT;
wire [1:0] Mux2x2_inst0_O;
wire [1:0] Register2_inst0_O;
Add2_cout Add2_cout_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_cout_inst0_O), .COUT(Add2_cout_ins... | 8.102846 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Mux2x4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
reg [3:0] coreir_commonlib_mux2x4_inst0_out;
always @(*) begin
if (S == 0) begin
coreir_commonlib_mux2x4_inst0_out = I0;
end else begin
coreir_commonlib_mux2x4_inst0_out = I1;
end
end
assign O = c... | 7.040503 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 7.403606 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire [4:0] coreir_add5_inst0_out;
assign coreir_add5_inst0_out = 5'(({1'b0, I0}) + ({1'b0, I1}));
assign O = coreir_add5_inst0_out[3:0];
assign COUT = coreir_add5_inst0_out[4];
endmodule
| 7.542776 |
module CounterLoad4_COUT (
input [3:0] DATA,
input LOAD,
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] Add4_cout_inst0_O;
wire [3:0] Mux2x4_inst0_O;
Add4_cout Add4_cout_inst0 (
.I0(O),
.I1(4'h1),
.O(Add4_cout_inst0_O),
.COUT(COUT)
);
Mux2x4 Mux2x4_inst0 (
... | 8.346251 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2x4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
commonlib_... | 7.040503 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 7.403606 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire bit_const_0_None_out;
wire [4:0] coreir_add5_inst0_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [4:0] coreir_add5_inst0_in0;
assign coreir_add5_inst0_in0 = {bit_cons... | 7.542776 |
module CounterLoad4_COUT (
input [3:0] DATA,
input LOAD,
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] Add4_cout_inst0_O;
wire Add4_cout_inst0_COUT;
wire [3:0] Mux2x4_inst0_O;
wire [3:0] Register4_inst0_O;
wire [3:0] const_1_4_out;
Add4_cout Add4_cout_inst0 (
.I0(Register4_i... | 8.346251 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_COUT (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
... | 8.082367 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module Mux2x4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I1[1], I0[1]}),
.S(S),... | 7.040503 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
wire SB_DFF_inst2_Q;
wire SB_DFF_inst3_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_D... | 7.403606 |
module CounterLoad4_COUT (input [3:0] DATA, input LOAD, output [3:0] O, output COUT, input CLK);
wire [3:0] Add4_COUT_inst0_O;
wire Add4_COUT_inst0_COUT;
wire [3:0] Mux2x4_inst0_O;
wire [3:0] Register4_inst0_O;
Add4_COUT Add4_COUT_inst0 (.I0(Register4_inst0_O), .I1(4'd1'), .O(Add4_COUT_inst0_O), .COUT(Add4_COUT_ins... | 8.346251 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire... | 7.542776 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I1[1], I0[1]}),
.S(S),... | 7.040503 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
... | 7.403606 |
module CounterLoad4_COUT (input [3:0] DATA, input LOAD, output [3:0] O, output COUT, input CLK);
wire [3:0] Add4_cout_inst0_O;
wire Add4_cout_inst0_COUT;
wire [3:0] Mux2x4_inst0_O;
wire [3:0] Register4_inst0_O;
Add4_cout Add4_cout_inst0 (.I0(Register4_inst0_O), .I1(4'd1'), .O(Add4_cout_inst0_O), .COUT(Add4_cout_ins... | 8.346251 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_... | 7.542776 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I1[1], I0[1]}),
.S(S),... | 7.040503 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
... | 7.403606 |
module CounterLoad4_COUT (input [3:0] DATA, input LOAD, output [3:0] O, output COUT, input CLK);
wire [3:0] Add4_cout_inst0_O;
wire Add4_cout_inst0_COUT;
wire [3:0] Mux2x4_inst0_O;
wire [3:0] Register4_inst0_O;
Add4_cout Add4_cout_inst0 (.I0(Register4_inst0_O), .I1(4'd1'), .O(Add4_cout_inst0_O), .COUT(Add4_cout_ins... | 8.346251 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Mux2x8 (
input [7:0] I0,
input [7:0] I1,
input S,
output [7:0] O
);
reg [7:0] coreir_commonlib_mux2x8_inst0_out;
always @(*) begin
if (S == 0) begin
coreir_commonlib_mux2x8_inst0_out = I0;
end else begin
coreir_commonlib_mux2x8_inst0_out = I1;
end
end
assign O = c... | 7.018661 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 6.73316 |
module Add8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire [8:0] coreir_add9_inst0_out;
assign coreir_add9_inst0_out = 9'(({1'b0, I0}) + ({1'b0, I1}));
assign O = coreir_add9_inst0_out[7:0];
assign COUT = coreir_add9_inst0_out[8];
endmodule
| 7.265928 |
module CounterLoad8_COUT (
input [7:0] DATA,
input LOAD,
output [7:0] O,
output COUT,
input CLK
);
wire [7:0] Add8_cout_inst0_O;
wire [7:0] Mux2x8_inst0_O;
Add8_cout Add8_cout_inst0 (
.I0(O),
.I1(8'h01),
.O(Add8_cout_inst0_O),
.COUT(COUT)
);
Mux2x8 Mux2x8_inst0 (
... | 8.059733 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
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