code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module coreir_andr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = ∈
endmodule
| 8.06584 |
module And8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire andr_inst0_out;
wire andr_inst1_out;
wire [7:0] andr_inst0_in;
assign andr_inst0_in = {I7[0], I6[0], ... | 7.035489 |
module And8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire And8_inst0_O;
wire And8_inst1_O;
And8 And8_inst0 (
.I({I7[0], I6[0], I5[0], I4[0], I3[0], I2[0], ... | 7.035489 |
module And8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire And8_inst0_O;
wire And8_inst1_O;
And8 And8_inst0 (
.I({I7[0], I6[0], I5[0], I4[0], I3[0], I2[0], ... | 7.035489 |
module And8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire And8_inst0_O;
wire And8_inst1_O;
And8 And8_inst0 (
.I({I7[0], I6[0], I5[0], I4[0], I3[0], I2[0], ... | 7.035489 |
module And8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
assign O = {
&({I7[3], I6[3], I5[3], I4[3], I3[3], I2[3], I1[3], I0[3]}),
&({I7[2], I6[2], I5[2], I4[2],... | 6.606257 |
module coreir_andr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = ∈
endmodule
| 8.06584 |
module And8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire andr_inst0_out;
wire andr_inst1_out;
wire andr_inst2_out;
wire andr_inst3_out;
wire [7:0] andr_inst... | 6.606257 |
module And8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire And8_inst0_O;
wire And8_inst1_O;
wire And8_inst2_O;
wire And8_inst3_O;
And8 And8_inst0 (
.I({... | 6.606257 |
module And8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire And8_inst0_O;
wire And8_inst1_O;
wire And8_inst2_O;
wire And8_inst3_O;
And8 And8_inst0 (
.I({... | 6.606257 |
module And8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire And8_inst0_O;
wire And8_inst1_O;
wire And8_inst2_O;
wire And8_inst3_O;
And8 And8_inst0 (
.I({... | 6.606257 |
module coreir_andr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = ∈
endmodule
| 8.06584 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module LUT2_2 (
input I0,
input I1,
output O
);
wire [1:0] coreir_lut2_inst0_in;
assign coreir_lut2_inst0_in = {I1, I0};
lutN #(
.init(4'h2),
.N(2)
) coreir_lut2_inst0 (
.in (coreir_lut2_inst0_in),
.out(O)
);
endmodule
| 7.802919 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module LUT2_2 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
wire [1:0] coreir_lut2_inst0_in;
assign coreir_lut2_inst0_in = {I1, I0};
lutN #(
.init(4'h2),
.N(2)
) coreir_lut2_inst0 (
.in (coreir_lut2_inst0_in),
.out(coreir_lut2_inst0_out)
);
assign O = ... | 7.802919 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module LUT2_2 (
input I0,
input I1,
output O
);
wire [1:0] coreir_lut2_inst0_in;
assign coreir_lut2_inst0_in = {I1, I0};
lutN #(
.init(4'h2),
.N(2)
) coreir_lut2_inst0 (
.in (coreir_lut2_inst0_in),
.out(O)
);
endmodule
| 7.802919 |
module Arbiter4 (
input [3:0] I,
output [3:0] O
);
wire LUT2_2_inst0_O;
wire LUT2_2_inst1_O;
wire LUT2_2_inst2_O;
wire LUT2_2_inst3_O;
wire [3:0] coreir_add4_inst0_out;
LUT2_2 LUT2_2_inst0 (
.I0(I[0]),
.I1(coreir_add4_inst0_out[0]),
.O (LUT2_2_inst0_O)
);
LUT2_2 LUT2_2_inst1 (... | 6.715014 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module LUT2_2 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
wire [1:0] coreir_lut2_inst0_in;
assign coreir_lut2_inst0_in = {I1, I0};
lutN #(
.init(4'h2),
.N(2)
) coreir_lut2_inst0 (
.in (coreir_lut2_inst0_in),
.out(coreir_lut2_inst0_out)
);
assign O = ... | 7.802919 |
module Arbiter4 (
input [3:0] I,
output [3:0] O
);
wire LUT2_2_inst0_O;
wire LUT2_2_inst1_O;
wire LUT2_2_inst2_O;
wire LUT2_2_inst3_O;
wire [3:0] const_15_4_out;
wire [3:0] coreir_add4_inst0_out;
LUT2_2 LUT2_2_inst0 (
.I0(I[0]),
.I1(coreir_add4_inst0_out[0]),
.O (LUT2_2_inst0_O)... | 6.715014 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_cin0 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire MUXCY_inst3_O;... | 6.538896 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module LUT2_2 (
input I0,
input I1,
output O
);
wire [1:0] coreir_lut2_inst0_in;
assign coreir_lut2_inst0_in = {I1, I0};
lutN #(
.init(4'h2),
.N(2)
) coreir_lut2_inst0 (
.in (coreir_lut2_inst0_in),
.out(O)
);
endmodule
| 7.802919 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module lutN #(
parameter N = 1,
parameter init = 1
) (
input [N-1:0] in,
output out
);
assign out = init[in];
endmodule
| 7.756611 |
module LUT2_2 (
input I0,
input I1,
output O
);
wire coreir_lut2_inst0_out;
wire [1:0] coreir_lut2_inst0_in;
assign coreir_lut2_inst0_in = {I1, I0};
lutN #(
.init(4'h2),
.N(2)
) coreir_lut2_inst0 (
.in (coreir_lut2_inst0_in),
.out(coreir_lut2_inst0_out)
);
assign O = ... | 7.802919 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module ASR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I(I),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[1], I[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = {Mux2_inst1_O, Mux2_inst0_O};
endmod... | 6.933713 |
module ASR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] ASR2_1_inst0_O;
ASR2_1 ASR2_1_inst0 (
.I(I),
.S(S[0]),
.O(ASR2_1_inst0_O)
);
assign O = ASR2_1_inst0_O;
endmodule
| 7.459007 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module ASR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I(I),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[1], I[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = {Mux2_inst1_O, Mux2_inst0_O};
endmod... | 6.933713 |
module ASR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] ASR2_1_inst0_O;
ASR2_1 ASR2_1_inst0 (
.I(I),
.S(S[0]),
.O(ASR2_1_inst0_O)
);
assign O = ASR2_1_inst0_O;
endmodule
| 7.459007 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module ASR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I(I),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[1], I[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = {Mux2_inst1_O, Mux2_inst0_O};
endmod... | 6.933713 |
module ASR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] ASR2_1_inst0_O;
ASR2_1 ASR2_1_inst0 (
.I(I),
.S(S[0]),
.O(ASR2_1_inst0_O)
);
assign O = ASR2_1_inst0_O;
endmodule
| 7.459007 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module ASR4_1 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[2], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.879493 |
module ASR4_2 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[3], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.769871 |
module ASR4 (
input [3:0] I,
input [1:0] S,
output [3:0] O
);
wire [3:0] ASR4_1_inst0_O;
wire [3:0] ASR4_2_inst0_O;
ASR4_1 ASR4_1_inst0 (
.I(I),
.S(S[0]),
.O(ASR4_1_inst0_O)
);
ASR4_2 ASR4_2_inst0 (
.I(ASR4_1_inst0_O),
.S(S[1]),
.O(ASR4_2_inst0_O)
);
assig... | 7.063614 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module ASR4_1 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[2], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.879493 |
module ASR4_2 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[3], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.769871 |
module ASR4 (
input [3:0] I,
input [1:0] S,
output [3:0] O
);
wire [3:0] ASR4_1_inst0_O;
wire [3:0] ASR4_2_inst0_O;
ASR4_1 ASR4_1_inst0 (
.I(I),
.S(S[0]),
.O(ASR4_1_inst0_O)
);
ASR4_2 ASR4_2_inst0 (
.I(ASR4_1_inst0_O),
.S(S[1]),
.O(ASR4_2_inst0_O)
);
assig... | 7.063614 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module ASR4_1 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[2], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.879493 |
module ASR4_2 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[3], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.769871 |
module ASR4 (
input [3:0] I,
input [1:0] S,
output [3:0] O
);
wire [3:0] ASR4_1_inst0_O;
wire [3:0] ASR4_2_inst0_O;
ASR4_1 ASR4_1_inst0 (
.I(I),
.S(S[0]),
.O(ASR4_1_inst0_O)
);
ASR4_2 ASR4_2_inst0 (
.I(ASR4_1_inst0_O),
.S(S[1]),
.O(ASR4_2_inst0_O)
);
assig... | 7.063614 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module ASR8_1 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 7.068408 |
module ASR8_2 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.776033 |
module ASR8_4 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[4], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.948746 |
module ASR8 (
input [7:0] I,
input [2:0] S,
output [7:0] O
);
wire [7:0] ASR8_1_inst0_O;
wire [7:0] ASR8_2_inst0_O;
wire [7:0] ASR8_4_inst0_O;
ASR8_1 ASR8_1_inst0 (
.I(I),
.S(S[0]),
.O(ASR8_1_inst0_O)
);
ASR8_2 ASR8_2_inst0 (
.I(ASR8_1_inst0_O),
.S(S[1]),
.O... | 7.617051 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module ASR8_1 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 7.068408 |
module ASR8_2 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.776033 |
module ASR8_4 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[4], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.948746 |
module ASR8 (
input [7:0] I,
input [2:0] S,
output [7:0] O
);
wire [7:0] ASR8_1_inst0_O;
wire [7:0] ASR8_2_inst0_O;
wire [7:0] ASR8_4_inst0_O;
ASR8_1 ASR8_1_inst0 (
.I(I),
.S(S[0]),
.O(ASR8_1_inst0_O)
);
ASR8_2 ASR8_2_inst0 (
.I(ASR8_1_inst0_O),
.S(S[1]),
.O... | 7.617051 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module ASR8_1 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 7.068408 |
module ASR8_2 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.776033 |
module ASR8_4 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[4], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.948746 |
module ASR8 (
input [7:0] I,
input [2:0] S,
output [7:0] O
);
wire [7:0] ASR8_1_inst0_O;
wire [7:0] ASR8_2_inst0_O;
wire [7:0] ASR8_4_inst0_O;
ASR8_1 ASR8_1_inst0 (
.I(I),
.S(S[0]),
.O(ASR8_1_inst0_O)
);
ASR8_2 ASR8_2_inst0 (
.I(ASR8_1_inst0_O),
.S(S[1]),
.O... | 7.617051 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire [2:0] coreir_add3_inst0_out;
assign coreir_add3_inst0_out = 3'(({1'b0, I0}) + ({1'b0, I1}));
assign O = coreir_add3_inst0_out[1:0];
assign COUT = coreir_add3_inst0_out[2];
endmodule
| 6.529797 |
module Counter2_COUT (
output [1:0] O,
output COUT,
input CLK
);
wire [1:0] Add2_cout_inst0_O;
Add2_cout Add2_cout_inst0 (
.I0(O),
.I1(2'h1),
.O(Add2_cout_inst0_O),
.COUT(COUT)
);
coreir_reg #(
.clk_posedge(1'b1),
.init(2'h0),
.width(2)
) reg_P_inst0 (
... | 7.893937 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire bit_const_0_None_out;
wire [2:0] coreir_add3_inst0_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [2:0] coreir_add3_inst0_in0;
assign coreir_add3_inst0_in0 = {bit_cons... | 6.529797 |
module Counter2_COUT (
output [1:0] O,
output COUT,
input CLK
);
wire [1:0] Add2_cout_inst0_O;
wire Add2_cout_inst0_COUT;
wire [1:0] const_1_2_out;
wire [1:0] reg_P_inst0_out;
Add2_cout Add2_cout_inst0 (
.I0(reg_P_inst0_out),
.I1(const_1_2_out),
.O(Add2_cout_inst0_O),
.COUT... | 7.893937 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_COUT (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(1'b0),
.O(FullAdder_inst0_O),... | 7.301465 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_DFF_inst1_Q)
);
assign O = {SB_DFF_inst1_Q,... | 6.626169 |
module Counter2_COUT (output [1:0] O, output COUT, input CLK);
wire [1:0] Add2_COUT_inst0_O;
wire Add2_COUT_inst0_COUT;
wire [1:0] Register2_inst0_O;
Add2_COUT Add2_COUT_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_COUT_inst0_O), .COUT(Add2_COUT_inst0_COUT));
Register2 Register2_inst0 (.I(Add2_COUT_inst0_O), .... | 7.893937 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
LUT2 #(
.INIT(4'h6)
) LUT2_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.O (L... | 6.529797 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module Counter2_COUT (output [1:0] O, output COUT, input CLK);
wire [1:0] Add2_cout_inst0_O;
wire Add2_cout_inst0_COUT;
wire [1:0] Register2_inst0_O;
Add2_cout Add2_cout_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_cout_inst0_O), .COUT(Add2_cout_inst0_COUT));
Register2 Register2_inst0 (.I(Add2_cout_inst0_O), .... | 7.893937 |
module Add2_cout (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
LUT6_2 #(
.INIT(64'h66666666AA... | 6.529797 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module Counter2_COUT (output [1:0] O, output COUT, input CLK);
wire [1:0] Add2_cout_inst0_O;
wire Add2_cout_inst0_COUT;
wire [1:0] Register2_inst0_O;
Add2_cout Add2_cout_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_cout_inst0_O), .COUT(Add2_cout_inst0_COUT));
Register2 Register2_inst0 (.I(Add2_cout_inst0_O), .... | 7.893937 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire [4:0] coreir_add5_inst0_out;
assign coreir_add5_inst0_out = 5'(({1'b0, I0}) + ({1'b0, I1}));
assign O = coreir_add5_inst0_out[3:0];
assign COUT = coreir_add5_inst0_out[4];
endmodule
| 7.542776 |
module Counter4_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] Add4_cout_inst0_O;
Add4_cout Add4_cout_inst0 (
.I0(O),
.I1(4'h1),
.O(Add4_cout_inst0_O),
.COUT(COUT)
);
coreir_reg #(
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_P_inst0 (
... | 7.925226 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add4_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire bit_const_0_None_out;
wire [4:0] coreir_add5_inst0_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [4:0] coreir_add5_inst0_in0;
assign coreir_add5_inst0_in0 = {bit_cons... | 7.542776 |
module Counter4_COUT (
output [3:0] O,
output COUT,
input CLK
);
wire [3:0] Add4_cout_inst0_O;
wire Add4_cout_inst0_COUT;
wire [3:0] const_1_4_out;
wire [3:0] reg_P_inst0_out;
Add4_cout Add4_cout_inst0 (
.I0(reg_P_inst0_out),
.I1(const_1_4_out),
.O(Add4_cout_inst0_O),
.COUT... | 7.925226 |
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