code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module coreir_sge #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) >= $signed(in1);
endmodule
| 7.874388 |
module coreir_sge4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
wire coreir_sge4_inst0_out;
coreir_sge #(
.width(4)
) coreir_sge4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_sge4_inst0_out)
);
assign O = coreir_sge4_inst0_out;
endmodule
| 7.384384 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
Ful... | 7.507677 |
module SGE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_inst0_O;
wire SB_LUT4_inst0_O;
Sub4 Sub4_inst0 (
.I0(I0),
.I1(I1),
.O (Sub4_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) SB_LUT4_inst0 (
.I0(Sub4_inst0_O[3]),
.I1(I0[3]),
... | 7.148271 |
module SGE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_inst0_O;
wire LUT3_inst0_O;
Sub4_cin1 Sub4_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub4_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub4_cin1_inst0_O[3]),
.I1(... | 7.148271 |
module SGE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_inst0_O;
wire LUT3_inst0_O;
Sub4_cin1 Sub4_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub4_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub4_cin1_inst0_O[3]),
.I1(... | 7.148271 |
module coreir_sge8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
assign O = ($signed(I0)) >= ($signed(I1));
endmodule
| 7.544806 |
module coreir_sge #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) >= $signed(in1);
endmodule
| 7.874388 |
module coreir_sge8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
wire coreir_sge8_inst0_out;
coreir_sge #(
.width(8)
) coreir_sge8_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_sge8_inst0_out)
);
assign O = coreir_sge8_inst0_out;
endmodule
| 7.544806 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
wir... | 7.601983 |
module SGE8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_inst0_O;
wire SB_LUT4_inst0_O;
Sub8 Sub8_inst0 (
.I0(I0),
.I1(I1),
.O (Sub8_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) SB_LUT4_inst0 (
.I0(Sub8_inst0_O[7]),
.I1(I0[7]),
... | 7.388147 |
module Sub8_cin1 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire MUXCY_inst3_O;... | 6.578031 |
module SGE8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_inst0_O;
wire LUT3_inst0_O;
Sub8_cin1 Sub8_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub8_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub8_cin1_inst0_O[7]),
.I1(... | 7.388147 |
module Sub8_cin1 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_inst2_O6;
wir... | 6.578031 |
module SGE8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_inst0_O;
wire LUT3_inst0_O;
Sub8_cin1 Sub8_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub8_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub8_cin1_inst0_O[7]),
.I1(... | 7.388147 |
module coreir_sgt2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
assign O = ($signed(I0)) > ($signed(I1));
endmodule
| 7.425258 |
module coreir_sgt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) > $signed(in1);
endmodule
| 7.822914 |
module coreir_sgt2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
wire coreir_sgt2_inst0_out;
coreir_sgt #(
.width(2)
) coreir_sgt2_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_sgt2_inst0_out)
);
assign O = coreir_sgt2_inst0_out;
endmodule
| 7.425258 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(FullAdder_inst0_O),
... | 6.821676 |
module SGT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_inst0_O;
wire SB_LUT4_inst0_O;
Sub2 Sub2_inst0 (
.I0(I1),
.I1(I0),
.O (Sub2_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) SB_LUT4_inst0 (
.I0(Sub2_inst0_O[1]),
.I1(I1[1]),
... | 6.906196 |
module SGT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_inst0_O;
wire LUT3_inst0_O;
Sub2_cin1 Sub2_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub2_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub2_cin1_inst0_O[1]),
.I1(... | 6.906196 |
module SGT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_inst0_O;
wire LUT3_inst0_O;
Sub2_cin1 Sub2_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub2_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub2_cin1_inst0_O[1]),
.I1(... | 6.906196 |
module coreir_sgt4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
assign O = ($signed(I0)) > ($signed(I1));
endmodule
| 7.440427 |
module coreir_sgt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) > $signed(in1);
endmodule
| 7.822914 |
module coreir_sgt4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
wire coreir_sgt4_inst0_out;
coreir_sgt #(
.width(4)
) coreir_sgt4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_sgt4_inst0_out)
);
assign O = coreir_sgt4_inst0_out;
endmodule
| 7.440427 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
Ful... | 7.507677 |
module SGT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_inst0_O;
wire SB_LUT4_inst0_O;
Sub4 Sub4_inst0 (
.I0(I1),
.I1(I0),
.O (Sub4_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) SB_LUT4_inst0 (
.I0(Sub4_inst0_O[3]),
.I1(I1[3]),
... | 6.987221 |
module SGT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_inst0_O;
wire LUT3_inst0_O;
Sub4_cin1 Sub4_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub4_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub4_cin1_inst0_O[3]),
.I1(... | 6.987221 |
module SGT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_inst0_O;
wire LUT3_inst0_O;
Sub4_cin1 Sub4_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub4_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub4_cin1_inst0_O[3]),
.I1(... | 6.987221 |
module coreir_sgt8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
assign O = ($signed(I0)) > ($signed(I1));
endmodule
| 7.725642 |
module coreir_sgt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) > $signed(in1);
endmodule
| 7.822914 |
module coreir_sgt8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
wire coreir_sgt8_inst0_out;
coreir_sgt #(
.width(8)
) coreir_sgt8_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_sgt8_inst0_out)
);
assign O = coreir_sgt8_inst0_out;
endmodule
| 7.725642 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
wir... | 7.601983 |
module SGT8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_inst0_O;
wire SB_LUT4_inst0_O;
Sub8 Sub8_inst0 (
.I0(I1),
.I1(I0),
.O (Sub8_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) SB_LUT4_inst0 (
.I0(Sub8_inst0_O[7]),
.I1(I1[7]),
... | 7.242389 |
module Sub8_cin1 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire MUXCY_inst3_O;... | 6.578031 |
module SGT8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_inst0_O;
wire LUT3_inst0_O;
Sub8_cin1 Sub8_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub8_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub8_cin1_inst0_O[7]),
.I1(... | 7.242389 |
module Sub8_cin1 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_inst2_O6;
wir... | 6.578031 |
module SGT8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_inst0_O;
wire LUT3_inst0_O;
Sub8_cin1 Sub8_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub8_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub8_cin1_inst0_O[7]),
.I1(... | 7.242389 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_sle2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
assign O = ($signed(I0)) <= ($signed(I1));
endmodule
| 7.530943 |
module coreir_sle #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) <= $signed(in1);
endmodule
| 7.904075 |
module coreir_sle2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
wire coreir_sle2_inst0_out;
coreir_sle #(
.width(2)
) coreir_sle2_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_sle2_inst0_out)
);
assign O = coreir_sle2_inst0_out;
endmodule
| 7.530943 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(FullAdder_inst0_O),
... | 6.821676 |
module SLE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_inst0_O;
wire SB_LUT4_inst0_O;
Sub2 Sub2_inst0 (
.I0(I1),
.I1(I0),
.O (Sub2_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) SB_LUT4_inst0 (
.I0(Sub2_inst0_O[1]),
.I1(I1[1]),
... | 7.129266 |
module SLE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_inst0_O;
wire LUT3_inst0_O;
Sub2_cin1 Sub2_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub2_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub2_cin1_inst0_O[1]),
.I1(... | 7.129266 |
module SLE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_inst0_O;
wire LUT3_inst0_O;
Sub2_cin1 Sub2_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub2_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub2_cin1_inst0_O[1]),
.I1(... | 7.129266 |
module coreir_sle4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
assign O = ($signed(I0)) <= ($signed(I1));
endmodule
| 7.525465 |
module coreir_sle #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) <= $signed(in1);
endmodule
| 7.904075 |
module coreir_sle4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
wire coreir_sle4_inst0_out;
coreir_sle #(
.width(4)
) coreir_sle4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_sle4_inst0_out)
);
assign O = coreir_sle4_inst0_out;
endmodule
| 7.525465 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
Ful... | 7.507677 |
module SLE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_inst0_O;
wire SB_LUT4_inst0_O;
Sub4 Sub4_inst0 (
.I0(I1),
.I1(I0),
.O (Sub4_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) SB_LUT4_inst0 (
.I0(Sub4_inst0_O[3]),
.I1(I1[3]),
... | 7.225341 |
module SLE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_inst0_O;
wire LUT3_inst0_O;
Sub4_cin1 Sub4_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub4_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub4_cin1_inst0_O[3]),
.I1(... | 7.225341 |
module SLE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_inst0_O;
wire LUT3_inst0_O;
Sub4_cin1 Sub4_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub4_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub4_cin1_inst0_O[3]),
.I1(... | 7.225341 |
module coreir_sle8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
assign O = ($signed(I0)) <= ($signed(I1));
endmodule
| 7.632912 |
module coreir_sle #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) <= $signed(in1);
endmodule
| 7.904075 |
module coreir_sle8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
wire coreir_sle8_inst0_out;
coreir_sle #(
.width(8)
) coreir_sle8_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_sle8_inst0_out)
);
assign O = coreir_sle8_inst0_out;
endmodule
| 7.632912 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
wir... | 7.601983 |
module SLE8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_inst0_O;
wire SB_LUT4_inst0_O;
Sub8 Sub8_inst0 (
.I0(I1),
.I1(I0),
.O (Sub8_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) SB_LUT4_inst0 (
.I0(Sub8_inst0_O[7]),
.I1(I1[7]),
... | 7.364145 |
module Sub8_cin1 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire MUXCY_inst3_O;... | 6.578031 |
module SLE8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_inst0_O;
wire LUT3_inst0_O;
Sub8_cin1 Sub8_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub8_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub8_cin1_inst0_O[7]),
.I1(... | 7.364145 |
module Sub8_cin1 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_inst2_O6;
wir... | 6.578031 |
module SLE8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_inst0_O;
wire LUT3_inst0_O;
Sub8_cin1 Sub8_cin1_inst0 (
.I0(I1),
.I1(I0),
.O (Sub8_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub8_cin1_inst0_O[7]),
.I1(... | 7.364145 |
module coreir_slt2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
assign O = ($signed(I0)) < ($signed(I1));
endmodule
| 7.508771 |
module coreir_slt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) < $signed(in1);
endmodule
| 7.897464 |
module coreir_slt2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
wire coreir_slt2_inst0_out;
coreir_slt #(
.width(2)
) coreir_slt2_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_slt2_inst0_out)
);
assign O = coreir_slt2_inst0_out;
endmodule
| 7.508771 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(FullAdder_inst0_O),
... | 6.821676 |
module SLT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_inst0_O;
wire SB_LUT4_inst0_O;
Sub2 Sub2_inst0 (
.I0(I0),
.I1(I1),
.O (Sub2_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) SB_LUT4_inst0 (
.I0(Sub2_inst0_O[1]),
.I1(I0[1]),
... | 6.651349 |
module SLT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_inst0_O;
wire LUT3_inst0_O;
Sub2_cin1 Sub2_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub2_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub2_cin1_inst0_O[1]),
.I1(... | 6.651349 |
module SLT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_inst0_O;
wire LUT3_inst0_O;
Sub2_cin1 Sub2_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub2_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub2_cin1_inst0_O[1]),
.I1(... | 6.651349 |
module coreir_slt4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
assign O = ($signed(I0)) < ($signed(I1));
endmodule
| 7.451821 |
module coreir_slt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) < $signed(in1);
endmodule
| 7.897464 |
module coreir_slt4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
wire coreir_slt4_inst0_out;
coreir_slt #(
.width(4)
) coreir_slt4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_slt4_inst0_out)
);
assign O = coreir_slt4_inst0_out;
endmodule
| 7.451821 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
Ful... | 7.507677 |
module SLT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_inst0_O;
wire SB_LUT4_inst0_O;
Sub4 Sub4_inst0 (
.I0(I0),
.I1(I1),
.O (Sub4_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) SB_LUT4_inst0 (
.I0(Sub4_inst0_O[3]),
.I1(I0[3]),
... | 7.061606 |
module SLT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_inst0_O;
wire LUT3_inst0_O;
Sub4_cin1 Sub4_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub4_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub4_cin1_inst0_O[3]),
.I1(... | 7.061606 |
module SLT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_inst0_O;
wire LUT3_inst0_O;
Sub4_cin1 Sub4_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub4_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub4_cin1_inst0_O[3]),
.I1(... | 7.061606 |
module coreir_slt8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
assign O = ($signed(I0)) < ($signed(I1));
endmodule
| 7.679016 |
module coreir_slt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) < $signed(in1);
endmodule
| 7.897464 |
module coreir_slt8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
wire coreir_slt8_inst0_out;
coreir_slt #(
.width(8)
) coreir_slt8_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_slt8_inst0_out)
);
assign O = coreir_slt8_inst0_out;
endmodule
| 7.679016 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
wir... | 7.601983 |
module SLT8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_inst0_O;
wire SB_LUT4_inst0_O;
Sub8 Sub8_inst0 (
.I0(I0),
.I1(I1),
.O (Sub8_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) SB_LUT4_inst0 (
.I0(Sub8_inst0_O[7]),
.I1(I0[7]),
... | 7.008963 |
module Sub8_cin1 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire MUXCY_inst3_O;... | 6.578031 |
module SLT8 (
input signed [7:0] I0,
input signed [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_inst0_O;
wire LUT3_inst0_O;
Sub8_cin1 Sub8_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub8_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) LUT3_inst0 (
.I0(Sub8_cin1_inst0_O[7]),
.I1(... | 7.008963 |
module Sub8_cin1 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_inst2_O6;
wir... | 6.578031 |
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