code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Add8_CIN (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
wir... | 7.601983 |
module Sub8_CIN (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire [7:0] Invert8_inst0_O;
wire [7:0] Add8_CIN_inst0_O;
wire SB_LUT4_inst0_O;
Invert8 Invert8_inst0 (
.I(I1),
.O(Invert8_inst0_O)
);
Add8_CIN Add8_CIN_inst0 (
.I0 (I0),
.I1 (Invert8_inst0_... | 6.913365 |
module Sub8_cin (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire MU... | 6.745054 |
module Sub8_cin (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_ins... | 6.745054 |
module Add8_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
input CIN
);
assign O = 8'((8'(({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, CIN}) + I0)) + I1);
endmodule
| 8.416699 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add8_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
input CIN
);
wire bit_const_0_None_out;
wire [7:0] coreir_add8_inst0_out;
wire [7:0] coreir_add8_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
coreir_add #(
.width(8)
) coreir_ad... | 8.416699 |
module Add8_cout_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT,
input CIN
);
wire [8:0] coreir_add9_inst0_out;
assign coreir_add9_inst0_out = 9'((9'(({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CIN}) + ({1'b0,I0}))) + ({1'b0,I1}));
assign O = coreir_add9_inst0_out[7:0];
assi... | 8.324529 |
module Sub8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire [7:0] Invert8_inst0_out;
Add8_cout_cin Add8_cout_cin_inst0 (
.I0(I0),
.I1(Invert8_inst0_out),
.O(O),
.COUT(COUT),
.CIN(1'b1)
);
assign Invert8_inst0_out = ~I1;
endmodule
| 6.715266 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_add #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 + in1;
endmodule
| 8.421559 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module Add8_cout_cin (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT,
input CIN
);
wire bit_const_0_None_out;
wire [8:0] coreir_add9_inst0_out;
wire [8:0] coreir_add9_inst1_out;
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
wire [8:0] coreir_add... | 8.324529 |
module Sub8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire [7:0] Add8_cout_cin_inst0_O;
wire Add8_cout_cin_inst0_COUT;
wire [7:0] Invert8_inst0_out;
wire bit_const_1_None_out;
Add8_cout_cin Add8_cout_cin_inst0 (
.I0(I0),
.I1(Invert8_inst0_out),
.O(... | 6.715266 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN_COUT (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.252533 |
module Sub8_COUT (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire [7:0] Invert8_inst0_O;
wire [7:0] Add8_CIN_COUT_inst0_O;
wire Add8_CIN_COUT_inst0_COUT;
Invert8 Invert8_inst0 (
.I(I1),
.O(Invert8_inst0_O)
);
Add8_CIN_COUT Add8_CIN_COUT_inst0 (
.I0(I0),... | 7.299866 |
module Sub8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
wire... | 6.715266 |
module Sub8_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_... | 6.715266 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullAdder_inst3_COUT;
wir... | 7.601983 |
module coreir_uge2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
assign O = I0 >= I1;
endmodule
| 7.089846 |
module coreir_uge #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 >= in1;
endmodule
| 7.227192 |
module coreir_uge2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
wire coreir_uge2_inst0_out;
coreir_uge #(
.width(2)
) coreir_uge2_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_uge2_inst0_out)
);
assign O = coreir_uge2_inst0_out;
endmodule
| 7.089846 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN_COUT (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(F... | 7.152261 |
module Sub2_COUT (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire [1:0] Invert2_inst0_O;
wire [1:0] Add2_CIN_COUT_inst0_O;
wire Add2_CIN_COUT_inst0_COUT;
Invert2 Invert2_inst0 (
.I(I1),
.O(Invert2_inst0_O)
);
Add2_CIN_COUT Add2_CIN_COUT_inst0 (
.I0(I0),... | 7.093823 |
module UGE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire [1:0] Sub2_COUT_inst0_O;
wire Sub2_COUT_inst0_COUT;
Sub2_COUT Sub2_COUT_inst0 (
.I0(I0),
.I1(I1),
.O(Sub2_COUT_inst0_O),
.COUT(Sub2_COUT_inst0_COUT)
);
assign O = Sub2_COUT_inst0_COUT;
endmodule
| 6.687776 |
module UGE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_cout_inst0_O;
wire Sub2_cin1_cout_inst0_COUT;
Sub2_cin1_cout Sub2_cin1_cout_inst0 (
.I0(I0),
.I1(I1),
.O(Sub2_cin1_cout_inst0_O),
.COUT(Sub2_cin1_cout_inst0_COUT)
);
assign O = Sub2_cin1_cout_ins... | 6.687776 |
module UGE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_cout_inst0_O;
wire Sub2_cin1_cout_inst0_COUT;
Sub2_cin1_cout Sub2_cin1_cout_inst0 (
.I0(I0),
.I1(I1),
.O(Sub2_cin1_cout_inst0_O),
.COUT(Sub2_cin1_cout_inst0_COUT)
);
assign O = Sub2_cin1_cout_ins... | 6.687776 |
module coreir_uge4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
assign O = I0 >= I1;
endmodule
| 7.187232 |
module coreir_uge #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 >= in1;
endmodule
| 7.227192 |
module coreir_uge4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
wire coreir_uge4_inst0_out;
coreir_uge #(
.width(4)
) coreir_uge4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_uge4_inst0_out)
);
assign O = coreir_uge4_inst0_out;
endmodule
| 7.187232 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN_COUT (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.712749 |
module Sub4_COUT (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire [3:0] Invert4_inst0_O;
wire [3:0] Add4_CIN_COUT_inst0_O;
wire Add4_CIN_COUT_inst0_COUT;
Invert4 Invert4_inst0 (
.I(I1),
.O(Invert4_inst0_O)
);
Add4_CIN_COUT Add4_CIN_COUT_inst0 (
.I0(I0),... | 7.489469 |
module UGE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire [3:0] Sub4_COUT_inst0_O;
wire Sub4_COUT_inst0_COUT;
Sub4_COUT Sub4_COUT_inst0 (
.I0(I0),
.I1(I1),
.O(Sub4_COUT_inst0_O),
.COUT(Sub4_COUT_inst0_COUT)
);
assign O = Sub4_COUT_inst0_COUT;
endmodule
| 6.909222 |
module Sub4_cin1_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
... | 6.70928 |
module UGE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_cout_inst0_O;
wire Sub4_cin1_cout_inst0_COUT;
Sub4_cin1_cout Sub4_cin1_cout_inst0 (
.I0(I0),
.I1(I1),
.O(Sub4_cin1_cout_inst0_O),
.COUT(Sub4_cin1_cout_inst0_COUT)
);
assign O = Sub4_cin1_cout_ins... | 6.909222 |
module Sub4_cin1_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LU... | 6.70928 |
module UGE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_cout_inst0_O;
wire Sub4_cin1_cout_inst0_COUT;
Sub4_cin1_cout Sub4_cin1_cout_inst0 (
.I0(I0),
.I1(I1),
.O(Sub4_cin1_cout_inst0_O),
.COUT(Sub4_cin1_cout_inst0_COUT)
);
assign O = Sub4_cin1_cout_ins... | 6.909222 |
module coreir_uge8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
assign O = I0 >= I1;
endmodule
| 7.067727 |
module coreir_uge #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 >= in1;
endmodule
| 7.227192 |
module coreir_uge8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
wire coreir_uge8_inst0_out;
coreir_uge #(
.width(8)
) coreir_uge8_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_uge8_inst0_out)
);
assign O = coreir_uge8_inst0_out;
endmodule
| 7.067727 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN_COUT (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.252533 |
module Sub8_COUT (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire [7:0] Invert8_inst0_O;
wire [7:0] Add8_CIN_COUT_inst0_O;
wire Add8_CIN_COUT_inst0_COUT;
Invert8 Invert8_inst0 (
.I(I1),
.O(Invert8_inst0_O)
);
Add8_CIN_COUT Add8_CIN_COUT_inst0 (
.I0(I0),... | 7.299866 |
module UGE8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire [7:0] Sub8_COUT_inst0_O;
wire Sub8_COUT_inst0_COUT;
Sub8_COUT Sub8_COUT_inst0 (
.I0(I0),
.I1(I1),
.O(Sub8_COUT_inst0_O),
.COUT(Sub8_COUT_inst0_COUT)
);
assign O = Sub8_COUT_inst0_COUT;
endmodule
| 7.457644 |
module Sub8_cin1_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
... | 6.819441 |
module UGE8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_cout_inst0_O;
wire Sub8_cin1_cout_inst0_COUT;
Sub8_cin1_cout Sub8_cin1_cout_inst0 (
.I0(I0),
.I1(I1),
.O(Sub8_cin1_cout_inst0_O),
.COUT(Sub8_cin1_cout_inst0_COUT)
);
assign O = Sub8_cin1_cout_ins... | 7.457644 |
module Sub8_cin1_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LU... | 6.819441 |
module UGE8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_cout_inst0_O;
wire Sub8_cin1_cout_inst0_COUT;
Sub8_cin1_cout Sub8_cin1_cout_inst0 (
.I0(I0),
.I1(I1),
.O(Sub8_cin1_cout_inst0_O),
.COUT(Sub8_cin1_cout_inst0_COUT)
);
assign O = Sub8_cin1_cout_ins... | 7.457644 |
module coreir_ugt2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
assign O = I0 > I1;
endmodule
| 7.29913 |
module coreir_ugt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 > in1;
endmodule
| 7.36211 |
module coreir_ugt2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
wire coreir_ugt2_inst0_out;
coreir_ugt #(
.width(2)
) coreir_ugt2_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_ugt2_inst0_out)
);
assign O = coreir_ugt2_inst0_out;
endmodule
| 7.29913 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN_COUT (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(F... | 7.152261 |
module Sub2_COUT (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire [1:0] Invert2_inst0_O;
wire [1:0] Add2_CIN_COUT_inst0_O;
wire Add2_CIN_COUT_inst0_COUT;
Invert2 Invert2_inst0 (
.I(I1),
.O(Invert2_inst0_O)
);
Add2_CIN_COUT Add2_CIN_COUT_inst0 (
.I0(I0),... | 7.093823 |
module coreir_ugt4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
assign O = I0 > I1;
endmodule
| 7.469583 |
module coreir_ugt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 > in1;
endmodule
| 7.36211 |
module coreir_ugt4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
wire coreir_ugt4_inst0_out;
coreir_ugt #(
.width(4)
) coreir_ugt4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_ugt4_inst0_out)
);
assign O = coreir_ugt4_inst0_out;
endmodule
| 7.469583 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN_COUT (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.712749 |
module Sub4_COUT (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire [3:0] Invert4_inst0_O;
wire [3:0] Add4_CIN_COUT_inst0_O;
wire Add4_CIN_COUT_inst0_COUT;
Invert4 Invert4_inst0 (
.I(I1),
.O(Invert4_inst0_O)
);
Add4_CIN_COUT Add4_CIN_COUT_inst0 (
.I0(I0),... | 7.489469 |
module UGT4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire [3:0] Sub4_COUT_inst0_O;
wire Sub4_COUT_inst0_COUT;
wire SB_LUT4_inst0_O;
Sub4_COUT Sub4_COUT_inst0 (
.I0(I1),
.I1(I0),
.O(Sub4_COUT_inst0_O),
.COUT(Sub4_COUT_inst0_COUT)
);
SB_LUT4 #(
.LUT_INIT(16'h5555... | 6.708774 |
module Sub4_cin1_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
... | 6.70928 |
module UGT4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_cout_inst0_O;
wire Sub4_cin1_cout_inst0_COUT;
wire LUT1_inst0_O;
Sub4_cin1_cout Sub4_cin1_cout_inst0 (
.I0(I1),
.I1(I0),
.O(Sub4_cin1_cout_inst0_O),
.COUT(Sub4_cin1_cout_inst0_COUT)
);
LUT1 #(
... | 6.708774 |
module Sub4_cin1_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LU... | 6.70928 |
module UGT4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_cout_inst0_O;
wire Sub4_cin1_cout_inst0_COUT;
wire LUT1_inst0_O;
Sub4_cin1_cout Sub4_cin1_cout_inst0 (
.I0(I1),
.I1(I0),
.O(Sub4_cin1_cout_inst0_O),
.COUT(Sub4_cin1_cout_inst0_COUT)
);
LUT1 #(
... | 6.708774 |
module coreir_ugt8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
assign O = I0 > I1;
endmodule
| 7.589144 |
module coreir_ugt #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 > in1;
endmodule
| 7.36211 |
module coreir_ugt8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
wire coreir_ugt8_inst0_out;
coreir_ugt #(
.width(8)
) coreir_ugt8_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_ugt8_inst0_out)
);
assign O = coreir_ugt8_inst0_out;
endmodule
| 7.589144 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add8_CIN_COUT (
input [7:0] I0,
input [7:0] I1,
input CIN,
output [7:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.252533 |
module Sub8_COUT (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire [7:0] Invert8_inst0_O;
wire [7:0] Add8_CIN_COUT_inst0_O;
wire Add8_CIN_COUT_inst0_COUT;
Invert8 Invert8_inst0 (
.I(I1),
.O(Invert8_inst0_O)
);
Add8_CIN_COUT Add8_CIN_COUT_inst0 (
.I0(I0),... | 7.299866 |
module UGT8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire [7:0] Sub8_COUT_inst0_O;
wire Sub8_COUT_inst0_COUT;
wire SB_LUT4_inst0_O;
Sub8_COUT Sub8_COUT_inst0 (
.I0(I1),
.I1(I0),
.O(Sub8_COUT_inst0_O),
.COUT(Sub8_COUT_inst0_COUT)
);
SB_LUT4 #(
.LUT_INIT(16'h5555... | 6.952964 |
module Sub8_cin1_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
... | 6.819441 |
module UGT8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_cout_inst0_O;
wire Sub8_cin1_cout_inst0_COUT;
wire LUT1_inst0_O;
Sub8_cin1_cout Sub8_cin1_cout_inst0 (
.I0(I1),
.I1(I0),
.O(Sub8_cin1_cout_inst0_O),
.COUT(Sub8_cin1_cout_inst0_COUT)
);
LUT1 #(
... | 6.952964 |
module Sub8_cin1_cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LU... | 6.819441 |
module UGT8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire [7:0] Sub8_cin1_cout_inst0_O;
wire Sub8_cin1_cout_inst0_COUT;
wire LUT1_inst0_O;
Sub8_cin1_cout Sub8_cin1_cout_inst0 (
.I0(I1),
.I1(I0),
.O(Sub8_cin1_cout_inst0_O),
.COUT(Sub8_cin1_cout_inst0_COUT)
);
LUT1 #(
... | 6.952964 |
module coreir_ule2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
assign O = I0 <= I1;
endmodule
| 7.653688 |
module coreir_ule #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 <= in1;
endmodule
| 7.796216 |
module coreir_ule2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
wire coreir_ule2_inst0_out;
coreir_ule #(
.width(2)
) coreir_ule2_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_ule2_inst0_out)
);
assign O = coreir_ule2_inst0_out;
endmodule
| 7.653688 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN_COUT (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(F... | 7.152261 |
module Sub2_COUT (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire [1:0] Invert2_inst0_O;
wire [1:0] Add2_CIN_COUT_inst0_O;
wire Add2_CIN_COUT_inst0_COUT;
Invert2 Invert2_inst0 (
.I(I1),
.O(Invert2_inst0_O)
);
Add2_CIN_COUT Add2_CIN_COUT_inst0 (
.I0(I0),... | 7.093823 |
module ULE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire [1:0] Sub2_COUT_inst0_O;
wire Sub2_COUT_inst0_COUT;
Sub2_COUT Sub2_COUT_inst0 (
.I0(I1),
.I1(I0),
.O(Sub2_COUT_inst0_O),
.COUT(Sub2_COUT_inst0_COUT)
);
assign O = Sub2_COUT_inst0_COUT;
endmodule
| 6.529852 |
module ULE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_cout_inst0_O;
wire Sub2_cin1_cout_inst0_COUT;
Sub2_cin1_cout Sub2_cin1_cout_inst0 (
.I0(I1),
.I1(I0),
.O(Sub2_cin1_cout_inst0_O),
.COUT(Sub2_cin1_cout_inst0_COUT)
);
assign O = Sub2_cin1_cout_ins... | 6.529852 |
module ULE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_cout_inst0_O;
wire Sub2_cin1_cout_inst0_COUT;
Sub2_cin1_cout Sub2_cin1_cout_inst0 (
.I0(I1),
.I1(I0),
.O(Sub2_cin1_cout_inst0_O),
.COUT(Sub2_cin1_cout_inst0_COUT)
);
assign O = Sub2_cin1_cout_ins... | 6.529852 |
module coreir_ule4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
assign O = I0 <= I1;
endmodule
| 7.750038 |
module coreir_ule #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 <= in1;
endmodule
| 7.796216 |
module coreir_ule4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
wire coreir_ule4_inst0_out;
coreir_ule #(
.width(4)
) coreir_ule4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_ule4_inst0_out)
);
assign O = coreir_ule4_inst0_out;
endmodule
| 7.750038 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add4_CIN_COUT (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O,
output COUT
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
wire FullAdder_inst2_O;
wire FullAdder_inst2_COUT;
wire FullAdder_inst3_O;
wire FullA... | 7.712749 |
module Sub4_COUT (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire [3:0] Invert4_inst0_O;
wire [3:0] Add4_CIN_COUT_inst0_O;
wire Add4_CIN_COUT_inst0_COUT;
Invert4 Invert4_inst0 (
.I(I1),
.O(Invert4_inst0_O)
);
Add4_CIN_COUT Add4_CIN_COUT_inst0 (
.I0(I0),... | 7.489469 |
module ULE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire [3:0] Sub4_COUT_inst0_O;
wire Sub4_COUT_inst0_COUT;
Sub4_COUT Sub4_COUT_inst0 (
.I0(I1),
.I1(I0),
.O(Sub4_COUT_inst0_O),
.COUT(Sub4_COUT_inst0_COUT)
);
assign O = Sub4_COUT_inst0_COUT;
endmodule
| 7.203038 |
module Sub4_cin1_cout (
input [3:0] I0,
input [3:0] I1,
output [3:0] O,
output COUT
);
wire LUT2_inst0_O;
wire MUXCY_inst0_O;
wire XORCY_inst0_O;
wire LUT2_inst1_O;
wire MUXCY_inst1_O;
wire XORCY_inst1_O;
wire LUT2_inst2_O;
wire MUXCY_inst2_O;
wire XORCY_inst2_O;
wire LUT2_inst3_O;
... | 6.70928 |
module ULE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire [3:0] Sub4_cin1_cout_inst0_O;
wire Sub4_cin1_cout_inst0_COUT;
Sub4_cin1_cout Sub4_cin1_cout_inst0 (
.I0(I1),
.I1(I0),
.O(Sub4_cin1_cout_inst0_O),
.COUT(Sub4_cin1_cout_inst0_COUT)
);
assign O = Sub4_cin1_cout_ins... | 7.203038 |
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