code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module design_1_JK_f_f_3_0 (
clk,
clr,
J,
K,
Q,
Qb
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire clr;
input wire J;
input wire K;
output wire Q;
output wire Qb;
JK_f_f inst (
.clk(clk),
.clr(clr),
.J (J),
.... | 7.051557 |
module design_1_MUX_addr_0_0 (
pc_addr,
pc_addr_J,
Branch,
pc_addr_final
);
input wire [31 : 0] pc_addr;
input wire [31 : 0] pc_addr_J;
input wire Branch;
output wire [31 : 0] pc_addr_final;
MUX_addr inst (
.pc_addr(pc_addr),
.pc_addr_J(pc_addr_J),
.Branch(Branch),
.p... | 6.850277 |
module design_1_MUX_addr_0_0 (
pc_addr,
pc_addr_J,
Branch,
pc_addr_final
);
input [31:0] pc_addr;
input [31:0] pc_addr_J;
input Branch;
output [31:0] pc_addr_final;
wire Branch;
wire [31:0] pc_addr;
wire [31:0] pc_addr_J;
wire [31:0] pc_addr_final;
design_1_MUX_addr_0_0_MUX_addr inst... | 6.850277 |
module design_1_mux_A_id0_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 ... | 7.371597 |
module design_1_mux_A_id0_2 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 ... | 7.371597 |
module design_1_mux_A_id1_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 ... | 7.371597 |
module design_1_mux_A_id1_2 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 ... | 7.371597 |
module design_1_mux_A_ptr0_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_A_ptr0_2 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_A_ptr1_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_A_ptr1_2 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_A_val0_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_A_val0_2 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_A_val1_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_A_val1_2 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_B_id0_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 ... | 7.371597 |
module design_1_mux_B_id1_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 ... | 7.371597 |
module design_1_mux_B_id_0 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 S... | 7.371597 |
module design_1_mux_B_ptr0_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_B_ptr0_2 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_B_ptr1_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_B_ptr1_2 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_B_val0_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_B_val1_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0... | 7.371597 |
module design_1_mux_B_val_0 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 ... | 7.371597 |
module design_1_mux_C0_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 S_C... | 7.371597 |
module design_1_mux_C1_1 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 S_C... | 7.371597 |
module design_1_mux_C_0 (
sel,
clk0,
rst0,
address0,
ce0,
we0,
d0,
q0,
clk1,
rst1,
address1,
ce1,
we1,
d1,
q1,
clk_o,
rst_o,
address_o,
ce_o,
we_o,
d_o,
q_o
);
input sel;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 S_CT... | 7.371597 |
module design_1_MUX_data_choice_0_1 (
data2,
data_sign_extend,
ALUSrc,
data_final
);
input wire [31 : 0] data2;
input wire [31 : 0] data_sign_extend;
input wire ALUSrc;
output wire [31 : 0] data_final;
MUX_data_choice inst (
.data2(data2),
.data_sign_extend(data_sign_extend),
... | 6.850277 |
module design_1_MUX_data_choice_0_1 (
data2,
data_sign_extend,
ALUSrc,
data_final
);
input [31:0] data2;
input [31:0] data_sign_extend;
input ALUSrc;
output [31:0] data_final;
wire ALUSrc;
wire [31:0] data2;
wire [31:0] data_final;
wire [31:0] data_sign_extend;
design_1_MUX_data_choi... | 6.850277 |
module design_1_MUX_sign_extend_data_0_0 (
Se,
sign_extend_zero,
sign_extend_one,
data
);
input wire Se;
input wire [31 : 0] sign_extend_zero;
input wire [31 : 0] sign_extend_one;
output wire [31 : 0] data;
MUX_sign_extend_data inst (
.Se(Se),
.sign_extend_zero(sign_extend_zero),... | 6.850277 |
module design_1_MUX_sign_extend_data_0_0 (
Se,
sign_extend_zero,
sign_extend_one,
data
);
input Se;
input [31:0] sign_extend_zero;
input [31:0] sign_extend_one;
output [31:0] data;
wire Se;
wire [31:0] data;
wire [31:0] sign_extend_one;
wire [31:0] sign_extend_zero;
design_1_MUX_sign... | 6.850277 |
module design_1_orgate_0_0 (
a,
b,
q
);
input wire [0 : 0] a;
input wire [0 : 0] b;
output wire [0 : 0] q;
orgate #(
.Port_Num(2),
.WIDTH(1)
) inst (
.a(a),
.b(b),
.c(1'B0),
.d(1'B0),
.e(1'B0),
.f(1'B0),
.g(1'B0),
.h(1'B0),
.q(q)
... | 6.849106 |
module design_1_orgate_1_0 (
a,
b,
q
);
input wire [0 : 0] a;
input wire [0 : 0] b;
output wire [0 : 0] q;
orgate #(
.Port_Num(2),
.WIDTH(1)
) inst (
.a(a),
.b(b),
.c(1'B0),
.d(1'B0),
.e(1'B0),
.f(1'B0),
.g(1'B0),
.h(1'B0),
.q(q)
... | 6.849106 |
module design_1_PC_0_0 (
pc_load,
clk,
rst,
pc_addr
);
input wire pc_load;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_clk_0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
inpu... | 6.566634 |
module design_1_PC_0_0 (
pc_load,
clk,
rst,
pc_addr
);
input pc_load;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_clk_0, INSERT_VIP 0" *) input clk;
(* X_... | 6.566634 |
module design_1_PC_0_0_PC (
Q,
pc_load,
clk,
rst
);
output [4:0] Q;
input pc_load;
input clk;
input rst;
wire [4:0] Q;
wire clk;
wire \pc_addr[0]_i_1_n_0 ;
wire \pc_addr[1]_i_1_n_0 ;
wire \pc_addr[2]_i_1_n_0 ;
wire \pc_addr[3]_i_1_n_0 ;
wire \pc_addr[4]_i_1_n_0 ;
wire pc_load;
... | 6.566634 |
module design_1_rst_clk_wiz_0_100M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_int... | 7.446465 |
module design_1_rst_clk_wiz_0_100M_0_cdc_sync (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
ext_reset_in,
mb_debug_sys_rst,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input ext_reset_in;
input mb_debug_sys_rst;
input slowest_sy... | 7.446465 |
module design_1_rst_clk_wiz_0_100M_0_cdc_sync_0 (
lpf_asr_reg,
scndry_out,
lpf_asr,
p_1_in,
p_2_in,
asr_lpf,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input p_1_in;
input p_2_in;
input [0:0] asr_lpf;
input aux_reset_in;
input ... | 7.446465 |
module design_1_rst_clk_wiz_0_100M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
ext_reset_in,
mb_debug_sys_rst,
aux_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input ext_reset_in;
input mb_debug_sys_rst;
input aux_reset_in;
wire \ACTIVE_HIGH_EXT.ACT_HI_... | 7.446465 |
module design_1_rst_clk_wiz_0_100M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_... | 7.446465 |
module design_1_rst_clk_wiz_0_100M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.IN... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input sl... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_0_cdc_sync (
lpf_exr_reg,
scndry_out,
ext_reset_in,
mb_debug_sys_rst,
lpf_exr,
p_3_out,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input ext_reset_in;
input mb_debug_sys_rst;
input lpf_exr;
input [2:0] p_3_out;
input slowest_sy... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_0_cdc_sync_0 (
lpf_asr_reg,
scndry_out,
aux_reset_in,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input aux_reset_in;
input lpf_asr;
input [0:0] asr_lpf;
input p_1_in;
input p_2_in;
input ... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
ext_reset_in,
mb_debug_sys_rst,
aux_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input ext_reset_in;
input mb_debug_sys_rst;
input aux_reset_in;
wire \ACTIVE_HIGH_EXT.ACT_HI_... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_0_proc_sys_reset (
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn,
slowest_sync_clk,
dcm_locked,
ext_reset_in,
mb_debug_sys_rst,
aux_reset_in
);
output mb_reset;
output [0:0] bus_struct_reset;
output... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_0_upcnt_n (
pr_dec0,
Q,
seq_cnt_en,
seq_clr,
slowest_sync_clk
);
output pr_dec0;
output [2:0] Q;
input seq_cnt_en;
input seq_clr;
input slowest_sync_clk;
wire [2:0] Q;
wire clear;
wire pr_dec0;
wire [5:0] q_int0;
wire seq_clr;
wire [2:0] seq_... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_1 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_int... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_1_cdc_sync (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
ext_reset_in,
mb_debug_sys_rst,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input ext_reset_in;
input mb_debug_sys_rst;
input slowest_sy... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_1_cdc_sync_0 (
lpf_asr_reg,
scndry_out,
lpf_asr,
p_1_in,
p_2_in,
asr_lpf,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input p_1_in;
input p_2_in;
input [0:0] asr_lpf;
input aux_reset_in;
input ... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_1_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
ext_reset_in,
mb_debug_sys_rst,
aux_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input ext_reset_in;
input mb_debug_sys_rst;
input aux_reset_in;
wire \ACTIVE_HIGH_EXT.ACT_HI_... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_1_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_... | 7.446465 |
module design_1_rst_clk_wiz_1_100M_1_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.IN... | 7.446465 |
module design_1_rst_ddr4_0_300M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interf... | 7.446465 |
module design_1_rst_ddr4_0_300M_0_cdc_sync (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
ext_reset_in,
mb_debug_sys_rst,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input ext_reset_in;
input mb_debug_sys_rst;
input slowest_sync_... | 7.446465 |
module design_1_rst_ddr4_0_300M_0_cdc_sync_0 (
lpf_asr_reg,
scndry_out,
lpf_asr,
p_1_in,
p_2_in,
asr_lpf,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input p_1_in;
input p_2_in;
input [0:0] asr_lpf;
input aux_reset_in;
input slo... | 7.446465 |
module design_1_rst_ddr4_0_300M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
ext_reset_in,
mb_debug_sys_rst,
aux_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input ext_reset_in;
input mb_debug_sys_rst;
input aux_reset_in;
wire \ACTIVE_HIGH_EXT.ACT_HI_EXT... | 7.446465 |
module design_1_rst_ddr4_0_300M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_res... | 7.446465 |
module design_1_rst_ddr4_0_300M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(... | 7.446465 |
module design_1_rst_ddr4_1_300M_0_cdc_sync (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
ext_reset_in,
mb_debug_sys_rst,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input ext_reset_in;
input mb_debug_sys_rst;
input slowest_sync_... | 7.446465 |
module design_1_rst_ddr4_1_300M_0_cdc_sync_0 (
lpf_asr_reg,
scndry_out,
lpf_asr,
p_1_in,
p_2_in,
asr_lpf,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input p_1_in;
input p_2_in;
input [0:0] asr_lpf;
input aux_reset_in;
input slo... | 7.446465 |
module design_1_rst_ddr4_1_300M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interf... | 7.446465 |
module design_1_rst_ddr4_1_300M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
ext_reset_in,
mb_debug_sys_rst,
aux_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input ext_reset_in;
input mb_debug_sys_rst;
input aux_reset_in;
wire \ACTIVE_HIGH_EXT.ACT_HI_EXT... | 7.446465 |
module design_1_rst_ddr4_1_300M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_res... | 7.446465 |
module design_1_rst_ddr4_1_300M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(... | 7.446465 |
module design_1_selectio_wiz_0_0
// width of the data for the system
#(
parameter SYS_W = 1,
// width of the data for the device
parameter DEV_W = 1
) (
// From the system into the device
input [SYS_W-1:0] data_in_from_pins,
output [DEV_W-1:0] data_in_to_device,
input clk_in, ... | 8.097697 |
module design_1_selectio_wiz_0_0_selectio_wiz
// width of the data for the system
#(
parameter SYS_W = 1,
// width of the data for the device
parameter DEV_W = 1
) (
// From the system into the device
input [SYS_W-1:0] data_in_from_pins,
output [DEV_W-1:0] data_in_to_device,
input ... | 8.097697 |
module design_1_SPI_Master_0_0 (
IN_DATA,
OUT_DATA,
CLK_in,
START_TRANSFER,
MISO,
MOSI,
SS,
SCLK,
reset_in,
Transfer_done
);
input [15:0] IN_DATA;
output [15:0] OUT_DATA;
input CLK_in;
input START_TRANSFER;
input MISO;
output MOSI;
output SS;
output SCLK;
(* x_i... | 6.751946 |
module design_1_uAHB2RAM_0_6 (
hsel,
fclk,
reg_sys_rst_n,
hreadyss,
haddrs,
htranss,
hwrites,
hsizes,
hwdatas,
hrdatas
);
input wire hsel;
input wire fclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME reg_sys_rst_n, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xil... | 6.928181 |
module design_1_wrapper_tb #(
parameter
// Testbench parameters
numSamples = 64
) ();
// Inputs
reg clock;
reg reset;
reg [ 7:0] din;
reg wr_en;
reg start;
reg [ 47:0] dMAC;
reg [ 47:0] sMAC;
reg [ 15:0] length;
reg ... | 6.945726 |
module design_1_xlslice_end_ready_1 (
Din,
Dout
);
input wire [3 : 0] Din;
output wire [0 : 0] Dout;
xlslice_v1_0_2_xlslice #(
.DIN_WIDTH(4),
.DIN_FROM(2),
.DIN_TO(2)
) inst (
.Din (Din),
.Dout(Dout)
);
endmodule
| 6.611486 |
module design_1_xlslice_end_ready_2 (
Din,
Dout
);
input wire [3 : 0] Din;
output wire [0 : 0] Dout;
xlslice_v1_0_2_xlslice #(
.DIN_WIDTH(4),
.DIN_FROM(2),
.DIN_TO(2)
) inst (
.Din (Din),
.Dout(Dout)
);
endmodule
| 6.611486 |
module design_1_xlslice_sel_1 (
Din,
Dout
);
input wire [3 : 0] Din;
output wire [0 : 0] Dout;
xlslice_v1_0_2_xlslice #(
.DIN_WIDTH(4),
.DIN_FROM(3),
.DIN_TO(3)
) inst (
.Din (Din),
.Dout(Dout)
);
endmodule
| 6.611486 |
module design_1_xlslice_sel_2 (
Din,
Dout
);
input wire [3 : 0] Din;
output wire [0 : 0] Dout;
xlslice_v1_0_2_xlslice #(
.DIN_WIDTH(4),
.DIN_FROM(3),
.DIN_TO(3)
) inst (
.Din (Din),
.Dout(Dout)
);
endmodule
| 6.611486 |
module design_1_xlslice_start_in_1 (
Din,
Dout
);
input wire [3 : 0] Din;
output wire [0 : 0] Dout;
xlslice_v1_0_2_xlslice #(
.DIN_WIDTH(4),
.DIN_FROM(0),
.DIN_TO(0)
) inst (
.Din (Din),
.Dout(Dout)
);
endmodule
| 6.611486 |
module design_1_xlslice_start_in_2 (
Din,
Dout
);
input wire [3 : 0] Din;
output wire [0 : 0] Dout;
xlslice_v1_0_2_xlslice #(
.DIN_WIDTH(4),
.DIN_FROM(0),
.DIN_TO(0)
) inst (
.Din (Din),
.Dout(Dout)
);
endmodule
| 6.611486 |
module design_1_xlslice_start_valid_1 (
Din,
Dout
);
input wire [3 : 0] Din;
output wire [0 : 0] Dout;
xlslice_v1_0_2_xlslice #(
.DIN_WIDTH(4),
.DIN_FROM(1),
.DIN_TO(1)
) inst (
.Din (Din),
.Dout(Dout)
);
endmodule
| 6.611486 |
module design_1_xlslice_start_valid_2 (
Din,
Dout
);
input wire [3 : 0] Din;
output wire [0 : 0] Dout;
xlslice_v1_0_2_xlslice #(
.DIN_WIDTH(4),
.DIN_FROM(1),
.DIN_TO(1)
) inst (
.Din (Din),
.Dout(Dout)
);
endmodule
| 6.611486 |
module design_1_xup_and2_0_0 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_0 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_1 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_1 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_2 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_2 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_3 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_3 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_4 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_4 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_5 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_5 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_6 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_6 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_7 (
a,
b,
y
);
input wire a;
input wire b;
output wire y;
xup_and2 #(
.DELAY(3)
) inst (
.a(a),
.b(b),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_and2_0_7 (
a,
b,
y
);
input a;
input b;
output y;
wire a;
wire b;
wire y;
LUT2 #(
.INIT(4'h8)
) y_INST_0 (
.I0(a),
.I1(b),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_inv_0_0 (
a,
y
);
input wire a;
output wire y;
xup_inv #(
.DELAY(3)
) inst (
.a(a),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_inv_0_0 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 6.893999 |
module design_1_xup_inv_0_1 (
a,
y
);
input wire a;
output wire y;
xup_inv #(
.DELAY(3)
) inst (
.a(a),
.y(y)
);
endmodule
| 6.893999 |
module design_1_xup_inv_0_1 (
a,
y
);
input a;
output y;
wire a;
wire y;
LUT1 #(
.INIT(2'h1)
) y_INST_0 (
.I0(a),
.O (y)
);
endmodule
| 6.893999 |
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