code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module display_test_tb ();
reg clk = 0;
wire [6:0] led_port;
wire c;
display_test #(
.M(4), //Change count delay to 4 cycles instead of 1 Hz
.refresh_rate(2) //Change segment refresh rate to half count time
) dut (
.clk (clk), //-- Input clock
.led_port(led_port), //-- L... | 7.697304 |
module display_timings #(
H_RES = 640, // horizontal resolution (pixels)
V_RES = 480, // vertical resolution (lines)
H_FP = 16, // horizontal front porch
H_SYNC = 96, // horizontal sync
H_BP = 48, // horizontal back porch
V_FP = 10, // vertical front porch
V_SYNC = 2, //... | 8.421921 |
module display_timings_480p (
input wire clk_pix, // pixel clock
input wire rst, // reset
output reg [9:0] sx, // horizontal screen position
output reg [9:0] sy, // vertical screen position
output wire hsync, // horizontal sync
output wire vsync, ... | 8.421921 |
module display_timings_480p (
input wire reg clk_pix, // pixel clock
input wire reg rst, // reset
output reg [9:0] sx, // horizontal screen position
output reg [9:0] sy, // vertical screen position
output reg hsync, // horizontal sync
outpu... | 8.421921 |
module display_timings_tb ();
// Display timings: 640x480p60
reg rst_480p;
reg clk_480p;
wire [15:0] sx_480p; // horizontal screen position
wire [15:0] sy_480p; // vertical screen position
wire h_sync_480p; // horizontal sync
wire v_sync_480p; // vertical sync
wire ... | 8.421921 |
module display_timings_variable (
input wire [15:0] h_res,
input wire [15:0] v_res,
input wire [15:0] h_fp,
input wire [15:0] h_sync,
input wire [15:0] h_bp,
input wire [15:0] v_fp,
input wire [15:0] v_sync,
input wire [15:0] v_bp,
input wire h_pol,
input wire v_pol... | 8.421921 |
module display_top ( /*AUTOARG*/
// Outputs
TX,
ANODE,
CATHODE,
// Inputs
CLK_IN,
RESET_IN,
RX
);
input CLK_IN;
input RESET_IN;
input RX;
output TX;
output [3:0] ANODE;
output [7:0] CATHODE;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-modu... | 6.914725 |
module display_to_dec (
input [15:0] number,
output [31:0] result
);
assign result = 32'd0;
endmodule
| 7.101832 |
module Transfer (
input CLK,
input [15:0] In,
output reg [3:0] Out,
output reg [3:0] Bit
);
integer i;
initial begin
i = 0;
end
always @(negedge CLK) begin
case (i)
0: begin
Out = In[15:12];
Bit = 4'b1110;
end
1: begin
Out = In[11:8];
... | 6.675048 |
module display_outBuffer (
input clk,
input rst,
input [7:0] inSegment,
input [3:0] inSelect,
output reg [7:0] segment,
output reg [3:0] select
);
always @(posedge clk or posedge rst)
if (rst) begin
segment <= 0;
select <= 0;
end else begin
segment <= ~inSegment;
... | 6.513214 |
module display_frequencyGen #(
parameter SPEED = 18
) (
input clk,
input rst,
output reg freq
);
reg [SPEED - 1:0] f_tim;
reg [SPEED - 1:0] n_tim;
always @(posedge clk or posedge rst)
if (rst) f_tim <= 0;
else f_tim <= n_tim;
always @(*) begin
n_tim = f_tim + 1;
freq = 0;
... | 7.853496 |
module display_TwodigitClock_HEX (
X,
D_HEX1,
D_HEX0
);
input [6:0] X;
output [0:6] D_HEX1, D_HEX0;
reg [3:0] FIRST_DEGIT, SECOND_DEGIT;
always begin
FIRST_DEGIT = X % 10;
SECOND_DEGIT = (X - FIRST_DEGIT) / 10;
end
display_HEX_Bin2HexorDec B1 (
SECOND_DEGIT,
D_HEX1
);
di... | 6.983294 |
module display_waveram (
// PORT A
clk_a, // clock, negedge triggered
addr_a, // address
wr_en_a, // write enable
rd_en_a, // read enable (unused)
data_rd_a, // data read out
data_wr_a, // data write in
// PORT B
clk_b, // clock, negedge triggered
addr_b, // address
... | 8.188986 |
module display_x (
clk,
disp_num,
digit_anode,
segment
);
input clk;
input wire [31:0] disp_num;
output reg [7:0] digit_anode;
output reg [7:0] segment;
reg [12:0] cnt = 0;
reg [ 3:0] num;
always @(posedge clk) begin
case (cnt[12:10])
3'b000: begin
digit_anode <= 8'b11111... | 7.306827 |
module vga_display_xadc (
input CLK100MHZ,
CPU_RESETN,
input vauxn3,
vauxp3,
input BTNC,
input [1:0] SW,
output [3:0] LED,
output [1:0] JA,
output VGA_HS,
VGA_VS,
output [3:0] VGA_R,
VGA_G,
VGA_B,
output CA,
CB,
CC,
CD,
CE,
CF,
CG,
outp... | 7.125328 |
module displcd (
input CCLK,
reset,
input [255:0] strdata,
output rslcd,
rwlcd,
elcd,
output [3:0] lcdd
);
wire [7:0] lcddatin;
lcd M0 (
CCLK,
resetlcd,
clearlcd,
homelcd,
datalcd,
addrlcd,
lcdreset,
lcdclear,
lcdhome,
lcddata,... | 6.847449 |
module dispmux (
output reg [7:0] SevenSeg,
output reg [3:0] SevenAnode,
input [7:0] dispA, // leftmost display
input [7:0] dispB,
input [7:0] dispC,
input [7:0] dispD, // rightmost display
input reset,
input clk
);
// Create a roughly 750 hz pulse by dividing the clock by 65,536... | 7.951134 |
module DispNum (
input wire clk,
rst,
input wire [15:0] hexs, // all four number to display // leftmost[15:12]; secondLeft[11:8]; secondRight[7:4]; rightmost[3:0]
input wire [3:0] points, // point to display // 1: activated
input wire [3:0] les, // "enable" for all four display // 0: enable
... | 8.242032 |
module DispScan (
input clk,
en,
input [3:0] in0,
in1,
in2,
in3,
input indip,
output reg [3:0] select,
out,
output reg outdip
);
// Declare state register
reg [1:0] state;
// Declare states
localparam S0 = 0, S1 = 1, S2 = 2, S3 = 3;
// Output depends only on the stat... | 7.589783 |
module dispselect (
clk,
disp_select,
Q
);
output [5:0] Q;
output [2:0] disp_select;
input clk;
reg [5:0] Q;
reg [2:0] disp_select;
always @(posedge clk) begin
if (disp_select < 3'b101) disp_select <= disp_select + 3'b1;
else disp_select <= 3'b0;
case (disp_select)
3'b000: ... | 7.369164 |
module dispString (
output reg rdy,
output reg [7:0] dOut,
input wire [7:0] dInP,
input wire rdyInP,
input wire [7:0] b0,
input wire [7:0] b1,
input wire [7:0] b2,
input wire [7:0] b3,
input wire [7:0] b4,
input wire [7:0] b5,
input wire [7:0] b6,
i... | 6.987802 |
module DISP_7SEG_DRV (
input CLK,
input CLR,
input CE,
input [7:0] E,
input [7:0] DP,
input [31:0] IN,
output [7:0] EO,
output [7:0] Q
);
wire [7:0] zero_hot_q;
reg [3:0] data;
reg a_dp;
// Krazace zero uzywane do aktywacji kolejnych cyfr.
RING_CNT #(
.BITS_NUM (8),
... | 7.538906 |
module disp_7_seg (
input CLK100MHZ, // Clock
input [4:0] digit_holder, // Current digit needed to be displayed
output [2:0] refresh_rate, // Works as a way to know what digit is being worked on
output [7:0] AN, // Anodes
output [6:0] seg // 7-seg display
);
re... | 7.965756 |
module disp_clk_crm (
input clk_in,
input rst_in,
output disp_clk,
output disp_rst,
output disp_clk_ok
);
wire LOCKED;
disp_clk_wizard disp_clk_wizard_i (
.CLK_IN1 (clk_in), // IN
.CLK_OUT1(disp_clk), // OUT
.RESET (rst_in), // IN
.LOCKED (LOCKED)
);
//... | 7.659719 |
module disp_clk_wizard ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
// Clocking primitive
//-------------------... | 7.025651 |
module disp_clk_wizard_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals... | 7.025651 |
module disp_clk_wizard_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER... | 7.025651 |
module DISP_GEN (
input i_rdisp, // current running disparity
output reg o_rdisp = 0, // disparity for next code group
input [9:0] i_stream,
output o_state,
input clk
);
integer i;
reg [3:0] o_count;
integer curr_disp; // dis... | 7.768368 |
module vid480p #(
parameter CORDW = 16,
H_RES = 640,
V_RES = 480,
H_FP = 16,
H_SYNC = 96,
H_BP = 48,
V_FP = 10,
V_SYNC = 2,
V_BP = 33,
H_POL = 0,
V_POL = 0
) (
input wire clk_pix,
input wire rst_pix,
output reg hsync,
output reg vsync,
output reg de,
o... | 8.280252 |
module display_signal2 #(
parameter COORDW = 16,
H_RES = 640,
V_RES = 480,
H_FP = 16,
H_SYNC = 96,
H_BP = 48,
V_FP = 10,
V_SYNC = 2,
V_BP = 33,
H_POL = 0,
V_POL = 0
) (
input wire clk_pix,
input wire rst_pix,
output wire [2:0] hvesync,
output reg frame,
ou... | 8.560745 |
module disp_hex_mux (
input wire clk,
reset,
input wire [3:0] hex3,
hex2,
hex1,
hex0, // hex digits
input wire [3:0] dp_in, // 4 decimal points
output reg [3:0] an, // enable 1-out-of-4 asserted low
output reg [7:0] sseg // led segments
);
// constant declarati... | 8.434995 |
module disp_hex_mux (
input wire clk,
reset,
input wire [3:0] hex3,
hex2,
hex1,
hex0,
input wire [3:0] dp_in,
output reg [3:0] an,
output reg [7:0] sseg
);
// constant declaration
// refreshing rate aroung 800 Hz (100 MHz / 2^17)
localparam N = 19;
// signal decl... | 8.434995 |
module dispManager #(
parameter COUNTHIGH = 4410,
FFT_SIZE = 256,
WORD_WIDTH = 16,
NO_FFTS = 50,
ADDRESS_WIDTH = 12,
NO_BANKS = 2
) (
input wire clk,
input wire reset,
input wire wr_en,
input wire [$clog2(FFT_SIZE/2)-1:0] i_address,
input wire [WORD_WIDTH*2-1:0] i_data,
... | 6.673565 |
module disp_mux (
input wire clk,
reset,
input wire [7:0] in3,
in2,
in1,
in0,
output reg [3:0] an,
output reg [7:0] sseg
);
// constant declaration
// refreshing rate aroung 800 Hz (100 MHz / 2^17)
localparam N = 19;
// signal declaration
reg [N-1:0] q_reg;
wire ... | 7.889435 |
module disp_mux_test (
input wire clk,
input wire [3:0] btn,
input wire [7:0] sw,
output wire [3:0] an,
output wire [7:0] seg
);
reg [7:0] d3_reg, d2_reg, d1_reg, d0_reg;
// instantiate 7-seg LED time mux module
disp_mux disp_unit (
.clk(clk),
.reset(1'b0),
.in0(d0... | 8.782013 |
module DISP_Scan (
input wire [3:0] data,
input wire rst_n,
output reg [1:8] led_n
);
parameter reg0=8'b0000_0011,
reg1=8'b1001_1111,
reg2=8'b0010_0101,
reg3=8'b0000_1101,
reg4=8'b1001_1001,
reg5=8'b0100_1001,
reg6=8'b0100_0001,
reg7=8'b0001_1111,
r... | 6.52377 |
module dispdecoder (
data_in,
data_out
);
output [7:0] data_out;
input [3:0] data_in;
reg [7:0] data_out;
always @(data_in) begin
case (data_in)
4'b0000: data_out <= 8'b11000000; //0
4'b0001: data_out <= 8'b11111001; //1
4'b0010: data_out <= 8'b10100100; //2
4'b0011: data... | 6.921858 |
module disp_selector (
input [127:0] IR,
input [2:0] disp_sel,
input disp_size,
output [31:0] disp
);
wire [7:0] byte3, byte4, byte5, byte6, byte7;
wire [7:0] byte8, byte9, byte10, byte11;
wire [7:0] out1m, out2m, out3m, out4m, out5m, out6m;
wire [7:0] out7m, out8m, out9m, out10m, out11m, out12... | 7.326877 |
module disp_sync (
input clk,
input rst,
output reg v_sync,
output reg h_sync,
output reg v_disp,
output reg h_disp,
output reg [9:0] v_loc,
output reg [10:0] h_loc
);
always @(posedge clk) begin
if (rst) h_loc <= 11'b00000000001;
else if (h_loc >= 11'b10000100000) h_loc <= 1... | 6.503624 |
module disRamTCAM #(
parameter MAX_RULE = 64, // # of rule
parameter NEXTHOP_LEN = 32, // nexthop lens
parameter KEY_LEN = 32 // search key lens
) (
output reg match, // check whether match the rule which store in ram entry
output reg [NEXTHOP_LEN-1:0] nexthop, // nexthop return to testbench t... | 7.721103 |
modules
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Distributed delay in each gate.
and #5 a1(e, a, b);
and #7 a2(f, c, d);
and #4 a3(out, e, f);
endmodule
| 6.778166 |
module.
//////////////////////////////////////////////////////////////////////////////
module DistanceLED
(
Clock,
Trigger,
Echo,
LED
);
//////////////////////////////////////////////////////////////////////////////
// Inputs / Outputs
//////////////////////////////////////////////////////////////////////////... | 6.641851 |
module distance_calculator(
input [2:0]pos, // posicion del elevador 2
input [5:0]floor, // peticion exclusiva de distancia
input dir, // direccion elevador 2: 1 para arriba 0 para abajo
input static, // estad... | 6.660755 |
module represents an individual mark. That mark needs to decide
if it should decide to the right (increase its position value)
or better still evaluate the positions of marks downstream to it.
The input 'enabled' specifies the single counter of the many that
make up the ruler that may change its positi... | 7.711546 |
module distance_fare (
input wire ten_meter_pulse,
input wire en,
input wire rst_n,
input wire wait_en,
input wire [11:0] distance_fare_per_pulse,
input wire [11:0] s_fare,
input wire max,
output wire [7:0] distance_bcd,
output wire [15:0] distance_fare_bcd
);
//里程计满标志
reg max_distance;
//四位BCD码加法器输出费用计满信号
... | 7.427208 |
module distance_fare_tb ();
reg ten_meter_pulse;
reg en;
reg rst_n;
reg [11:0] distance_fare_per_pulse;
reg [11:0] s_fare;
wire [7:0] distance_bcd;
wire [15:0] distance_fare_bcd;
parameter CYCLE = 5'd20;
always #100 ten_meter_pulse = ~ten_meter_pulse;
initial begin
en = 1'b0;
rst_n = 1'... | 7.427208 |
module Distance_meter (
input wire clk_100MHz,
input wire reset,
output reg [8:0] distance_cm,
output reg [4:0] speaker_note,
input wire Echo_in,
output reg Trig_out
);
reg [24:0] trig_cnt = 0;
reg [24:0] trig_cnt_nxt = 0;
reg [20:0] echo_cnt = 0;
reg [20:0] echo_cnt_nxt = 0;
reg [8:0... | 6.961435 |
module outputs the side the station is on, and emits a 10ns pulse when a
station is detected. This is called proximity and 0 is for the right side and
1 for the left.
-------------------------------------------------------
Author : Akhil Kapadia
-------------------------------------------------------
*/
module Distanc... | 7.303036 |
module distance_top_tb ();
reg clk;
reg rst_n;
reg echo;
distance_top u_distance_top (
.clk (clk),
.rst_n(rst_n),
.echo (echo),
.trig (trig),
.sel (sel),
.seg (seg),
.led (led)
);
localparam CLK_PERIOD = 2;
always #(CLK_PERIOD / 2) clk = ~clk;
initial beg... | 7.330937 |
module distance_trig (
clk,
rst,
trig_sig
);
input clk, rst;
output trig_sig;
reg r_sig;
reg [23:0] count;
parameter T100MS = 124_999_99;
parameter T20US = 2499;
always @(posedge clk, posedge rst) begin
if (rst) count <= 0;
else if (count == T100MS) begin
count <= 0;
end el... | 6.680678 |
module Distribucion_Salida (
input wire In_signal_conmutacion,
input wire select_salida,
output wire [1:0] Out_signal_conmutacion
);
Demux Instancia_Demux (
.out(Out_signal_conmutacion),
.in (In_signal_conmutacion),
.sel(select_salida)
);
endmodule
| 7.690331 |
module IMem (
input [11:0] a,
output [31:0] spo,
input [11:0] a2,
output [31:0] spo2
);
reg [31:0] IMEM[0:4096];
// initial begin
// $readmemh("../riscvprogram/src/graphic/graphic.dat", IMEM);
// end
assign spo = IMEM[a];
assign spo2 = IMEM[a2];
// assign spo2 = 32'hFFCCEE22;
endmodule... | 7.299969 |
module for the Aquila core (A RISC-V core).
// -----------------------------------------------------------------------------
// Revision information:
//
// None.
// -----------------------------------------------------------------------------
// License information:
//
// This software is released under the BSD-3-C... | 8.217566 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module dist_dmem_ip (
a,
d,
clk,
we,
spo
);
input wire [10 : 0] a;
input wire [31 : 0] d;
input wire clk;
input wire we;
output wire [31 : 0] spo;
dist_mem_gen_v8_0_12 #(
.C_FAMILY("artix7"),
.C_ADDR_WIDTH(11),
.C_DEFAULT_DATA("0"),
.C_DEPTH(2048),
.C_HAS_... | 6.781816 |
module dist_mem (
input [7:0] a,
input [7:0] dpra,
input [31:0] d,
input clk,
input we,
output [31:0] spo,
output [31:0] dpo
);
reg [31:0] mem[0:255];
initial begin
$readmemh("headers/data.coe", mem);
end
always @(posedge clk) if (we) mem[a] <= d;
assign spo = mem[a];
ass... | 7.535851 |
module dist_mem_65x1024 (
a,
d,
dpra,
clk,
we,
qdpo_ce,
qdpo
);
input [9 : 0] a;
input [64 : 0] d;
input [9 : 0] dpra;
input clk;
input we;
input qdpo_ce;
output [64 : 0] qdpo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(10),
.C_DEFAULT_DATA... | 6.916914 |
module dist_mem_gen_0 (
a,
d,
dpra,
clk,
we,
dpo
);
input wire [8 : 0] a;
input wire [31 : 0] d;
input wire [8 : 0] dpra;
input wire clk;
input wire we;
output wire [31 : 0] dpo;
dist_mem_gen_v8_0_12 #(
.C_FAMILY("artix7"),
.C_ADDR_WIDTH(9),
.C_DEFAULT_DATA("0")... | 6.79202 |
module dist_mem_gen_0
(a,
d,
dpra,
clk,
we,
dpo);
input [8:0]a;
input [31:0]d;
input [8:0]dpra;
input clk;
input we;
output [31:0]dpo;
wire [8:0]a;
wire clk;
wire [31:0]d;
wire [31:0]dpo;
wire [8:0]dpra;
wire we;
wire [31:0]NLW_U0_qdpo_UNCONNECTED;
wire [31:0]NLW_U0_q... | 6.79202 |
module dist_mem_gen_0_dist_mem_gen_v8_0_12 (
a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo
);
input [8:0] a;
input [31:0] d;
input [8:0] dpra;
input clk;
input we;
inpu... | 6.79202 |
module dist_mem_gen_0_dist_mem_gen_v8_0_12_synth (
dpo,
clk,
d,
dpra,
a,
we
);
output [31:0] dpo;
input clk;
input [31:0] d;
input [8:0] dpra;
input [8:0] a;
input we;
wire [8:0] a;
wire clk;
wire [31:0] d;
wire [31:0] dpo;
wire [8:0] dpra;
wire we;
dist_mem_gen_0_sdp... | 6.79202 |
module dist_mem_gen_1 (
a,
spo
);
input wire [15 : 0] a;
output wire [3 : 0] spo;
dist_mem_gen_v8_0_10 #(
.C_FAMILY("artix7"),
.C_ADDR_WIDTH(16),
.C_DEFAULT_DATA("0"),
.C_DEPTH(65536),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS... | 6.79202 |
module dist_mem_gen_1
(a,
spo);
input [15:0]a;
output [3:0]spo;
wire [15:0]a;
wire [3:0]spo;
wire [3:0]NLW_U0_dpo_UNCONNECTED;
wire [3:0]NLW_U0_qdpo_UNCONNECTED;
wire [3:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_D = "0" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *... | 6.79202 |
module dist_mem_gen_1_dist_mem_gen_v8_0_10 (
a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo
);
input [15:0] a;
input [3:0] d;
input [15:0] dpra;
input clk;
input we;
inp... | 6.79202 |
module dist_mem_gen_1_dist_mem_gen_v8_0_10_synth (
spo,
a
);
output [3:0] spo;
input [15:0] a;
wire [15:0] a;
wire [ 3:0] spo;
dist_mem_gen_1_rom \gen_rom.rom_inst (
.a (a),
.spo(spo)
);
endmodule
| 6.79202 |
module dist_mem_gen_2 (
a,
spo
);
input wire [12 : 0] a;
output wire [3 : 0] spo;
dist_mem_gen_v8_0_10 #(
.C_FAMILY("artix7"),
.C_ADDR_WIDTH(13),
.C_DEFAULT_DATA("0"),
.C_DEPTH(8192),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_... | 6.79202 |
module dist_mem_gen_2
(a,
spo);
input [12:0]a;
output [3:0]spo;
wire [12:0]a;
wire [3:0]spo;
wire [3:0]NLW_U0_dpo_UNCONNECTED;
wire [3:0]NLW_U0_qdpo_UNCONNECTED;
wire [3:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_D = "0" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *... | 6.79202 |
module dist_mem_gen_2_dist_mem_gen_v8_0_10 (
a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo
);
input [12:0] a;
input [3:0] d;
input [12:0] dpra;
input clk;
input we;
inp... | 6.79202 |
module dist_mem_gen_2_dist_mem_gen_v8_0_10_synth (
spo,
a
);
output [3:0] spo;
input [12:0] a;
wire [12:0] a;
wire [ 3:0] spo;
dist_mem_gen_2_rom \gen_rom.rom_inst (
.a (a),
.spo(spo)
);
endmodule
| 6.79202 |
module dist_mem_gen_3 (
a,
spo
);
input wire [14 : 0] a;
output wire [9 : 0] spo;
dist_mem_gen_v8_0_10 #(
.C_FAMILY("artix7"),
.C_ADDR_WIDTH(15),
.C_DEFAULT_DATA("0"),
.C_DEPTH(32768),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS... | 6.79202 |
module dist_mem_gen_3
(a,
spo);
input [14:0]a;
output [9:0]spo;
wire [14:0]a;
wire [9:0]spo;
wire [9:0]NLW_U0_dpo_UNCONNECTED;
wire [9:0]NLW_U0_qdpo_UNCONNECTED;
wire [9:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_D = "0" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *... | 6.79202 |
module dist_mem_gen_4 (
a,
spo
);
input wire [14 : 0] a;
output wire [9 : 0] spo;
dist_mem_gen_v8_0_10 #(
.C_FAMILY("artix7"),
.C_ADDR_WIDTH(15),
.C_DEFAULT_DATA("0"),
.C_DEPTH(32768),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS... | 6.79202 |
module dist_mem_gen_4
(a,
spo);
input [14:0]a;
output [9:0]spo;
wire [14:0]a;
wire [9:0]spo;
wire [9:0]NLW_U0_dpo_UNCONNECTED;
wire [9:0]NLW_U0_qdpo_UNCONNECTED;
wire [9:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_D = "0" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *... | 6.79202 |
module dist_mem_gen_4_dist_mem_gen_v8_0_10 (
a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo
);
input [14:0] a;
input [9:0] d;
input [14:0] dpra;
input clk;
input we;
inp... | 6.79202 |
module dist_mem_gen_4_dist_mem_gen_v8_0_10_synth (
spo,
a
);
output [8:0] spo;
input [14:0] a;
wire [14:0] a;
wire [ 8:0] spo;
dist_mem_gen_4_rom \gen_rom.rom_inst (
.a (a),
.spo(spo)
);
endmodule
| 6.79202 |
module dist_mem_gen_5 (
a,
spo
);
input wire [9 : 0] a;
output wire [9 : 0] spo;
dist_mem_gen_v8_0_10 #(
.C_FAMILY("artix7"),
.C_ADDR_WIDTH(10),
.C_DEFAULT_DATA("0"),
.C_DEPTH(1024),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I... | 6.79202 |
module dist_mem_gen_5
(a,
spo);
input [9:0]a;
output [9:0]spo;
wire [9:0]a;
wire [9:0]spo;
wire [9:0]NLW_U0_dpo_UNCONNECTED;
wire [9:0]NLW_U0_qdpo_UNCONNECTED;
wire [9:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_D = "0" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *) ... | 6.79202 |
module dist_mem_gen_5_dist_mem_gen_v8_0_10 (
a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo
);
input [9:0] a;
input [9:0] d;
input [9:0] dpra;
input clk;
input we;
input... | 6.79202 |
module dist_mem_gen_5_dist_mem_gen_v8_0_10_synth (
spo,
a
);
output [9:0] spo;
input [9:0] a;
wire [9:0] a;
wire [9:0] spo;
dist_mem_gen_5_rom \gen_rom.rom_inst (
.a (a),
.spo(spo)
);
endmodule
| 6.79202 |
module dist_mem_gen_5_rom (
spo,
a
);
output [9:0] spo;
input [9:0] a;
wire [9:0] a;
wire [9:0] spo;
wire \spo[3]_INST_0_i_1_n_0 ;
wire \spo[6]_INST_0_i_1_n_0 ;
wire \spo[8]_INST_0_i_1_n_0 ;
wire \spo[8]_INST_0_i_2_n_0 ;
wire \spo[9]_INST_0_i_1_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair2" *)
L... | 6.79202 |
module dist_mem_gen_sin
(a,
spo);
input [4:0]a;
output [9:0]spo;
wire [4:0]a;
wire [9:0]spo;
wire [9:0]NLW_U0_dpo_UNCONNECTED;
wire [9:0]NLW_U0_qdpo_UNCONNECTED;
wire [9:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "zynq" *)
(* C_HAS_D = "0" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *) ... | 6.79202 |
module dist_mem_gen_sin_dist_mem_gen_v8_0 (
a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo
);
input [4:0] a;
input [9:0] d;
input [4:0] dpra;
input clk;
input we;
input ... | 6.79202 |
module dist_mem_gen_sin_X99 (
a,
o
);
input [4:0] a;
output reg [9:0] o;
always @(a) begin
case (a)
5'b00000: o = 10'b0000000000;
5'b00001: o = 10'b0000011011;
5'b00010: o = 10'b0000110110;
5'b00011: o = 10'b0001010000;
5'b00100: o = 10'b0001101010;
5'b00101: o = 10... | 6.79202 |
module DIST_MEM_GEN_V3_4_XST #(
parameter C_ADDR_WIDTH = 6,
parameter C_DEFAULT_DATA = "0",
parameter C_DEPTH = 64,
parameter C_HAS_CLK = 1,
parameter C_HAS_D = 1,
parameter C_HAS_DPO = 0,
parameter C_HAS_DPRA = 0,
parameter C_HAS_I_CE ... | 6.938749 |
module dist_mem_test;
reg [3:0] addr;
reg [7:0] d_in;
wire [7:0] d_out;
reg clk, we;
dist_mem_gen_test distmem (
.a (addr),
.d (d_in),
.clk(clk),
.we (we),
.spo(d_out)
);
parameter PERIOD = 10, CYCLE = 20;
initial begin
clk = 0;
repeat (10 * CYCLE) #(PERIOD / 2)... | 7.201062 |
module dis_measure (
input [10:0] x_max,
x_min,
output [31:0] distance
);
parameter focal = 650;
//decleration
//distance / actual width = pixel width / focal distance;
assign distance = (x_max - x_min) * 40 / focal;
endmodule
| 8.319533 |
module dis_pal_buff2pal (
dis_clk,
dis_rst_n,
dis_data,
dis_sync_n,
dis_blank_n,
if_cnt_x,
if_cnt_y,
fifo_rdreq,
fifo_q
);
parameter DATA_WIDTH = 10;
parameter [9:0] CNT_X = 10'd864;
parameter [9:0] BLANK_H_BEFORE = 10'd126;
parameter [9:0] DIS_X = 10'd720;
parameter [9:0... | 6.893419 |
module dis_pal_decode (
clk,
rst_n,
din_data,
din_valid,
din_ready,
din_startofpacket,
din_endofpacket,
dout_data,
dout_valid,
dout_ready,
dout_startofpacket,
dout_endofpacket,
im_width,
im_height,
im_interlaced
);
parameter DATA_WIDTH = 14;
parameter ... | 8.179879 |
module dis_pal_delay (
clk,
rst_n,
datain,
dataout
);
parameter DATA_WIDTH = 16;
parameter DELAY_CYCLE = 2;
input clk, rst_n;
input [DATA_WIDTH-1:0] datain;
output [DATA_WIDTH-1:0] dataout;
reg [DATA_WIDTH-1:0] data_reg[DELAY_CYCLE-1:0];
assign dataout = data_reg[DELAY_CYCLE-1];
alw... | 7.715494 |
module dis_pal_mult (
clock,
aclr,
dataa,
result
);
parameter PIPELINE = 4;
parameter DATA_WIDTH = 10;
parameter [DATA_WIDTH-1:0] MULT_NUM = 716;
input aclr;
input clock;
input [DATA_WIDTH-1:0] dataa;
output [DATA_WIDTH-1:0] result;
wire [DATA_WIDTH-1:0] sub_wire0;
wire [DATA_WIDTH-1... | 6.728512 |
module dis_pal_add (
clock,
aclr,
dataa,
datab,
result
);
parameter PIPELINE = 2;
parameter DATA_WIDTH = 10;
input clock;
input aclr;
input [DATA_WIDTH-1:0] dataa;
input [DATA_WIDTH-1:0] datab;
output [DATA_WIDTH-1:0] result;
wire [DATA_WIDTH-1:0] sub_wire0;
wire [DATA_WIDTH-1:0]... | 6.549513 |
module dis_pal_embedded #(
parameter DATA_WIDTH = 10,
parameter MULT_PIPE = 4,
parameter ADD_PIPE = 2,
parameter [DATA_WIDTH-1:0] MULT_NUM = 716,
parameter [DATA_WIDTH-1:0] ADD_NUM = 307
) (
input clk,
input rst_n,
input din_sync... | 7.203996 |
module dis_pal_pixel_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw
);
parameter DATA_WIDTH = 10;
input aclr;
input [DATA_WIDTH-1:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [DATA_WIDTH-1:0] q;
output [9:0] wrusedw;
`ifndef ALTERA_RE... | 7.238777 |
module dis_pal_process_data (
vst_clk,
vst_rst_n,
vst_data,
vst_valid,
vst_ready,
vst_startofpacket,
vst_endofpacket,
fifo_data,
fifo_wrreq,
fifo_usedw,
fifo_aclr,
dis_clk,
dis_rst_n
);
parameter DATA_WIDTH = 10;
parameter [9:0] PAL_WIDTH = 720;
parameter [2... | 8.187955 |
module dis_pal_top(
vst_clk, vst_rst_n,
vst_data, vst_valid, vst_ready,
vst_startofpacket, vst_endofpacket,
`ifdef EXPORT_CNT
if_cnt_x, if_cnt_y,
`endif
dis_clk, dis_data
`ifdef SEPARATE_PAL_OUT
,
dis_sync_n, dis_blank_n
`endif
);
parameter DATA_WIDTH = 10;
parameter FRAME_NUM = 24'd2_000_000;
parame... | 7.833465 |
module counterReset #(
parameter WIDTH = 27
) (
output reg [WIDTH:0] count,
input clk,
input signal
);
reg previous = 0;
initial begin
count = 0;
end
always @(posedge clk) begin
if (signal === previous) begin
count <= count + 1;
end else begin
count <= 0;
end
p... | 7.568229 |
module dither(clk, rst, wren, in, out);
parameter in_bits = 40;
parameter fp_bits = 22;
parameter out_bits = 16;
input clk;
input rst;
input wren;
input signed [(in_bits-1):0] in;
output signed [(out_bits-1):0] out;
wire [(fp_bits-1):0] rand_0;
wire [(fp_bits-1):0] rand_1;
generate
genvar ig;
for (ig = 0; ig < f... | 6.648935 |
module dithering_process (
input CLK,
input signal,
output out
);
parameter SAMPLE_TIME = 50000;
reg [21:0] count_low;
reg [21:0] count_high;
reg key_out_reg;
always @(posedge CLK)
if (signal == 1'b0) count_low <= count_low + 1;
else count_low <= 0;
always @(posedge CLK)
if (signal... | 6.615242 |
module dit_store (
input rdy,
input [0:`ADC_DATLEN-1] in,
input get,
input [0:`FFT_VLEN_LOG2] choose,
output [0:`ADC_DATLEN-1] out_w,
output full_w
);
reg [0:`ADC_DATLEN-1] out;
reg full;
initial full = 0;
reg [0:`FFT_VLEN_LOG2] count_in_x;
initial count_in_x = 0;
reg [0:`ADC_DATL... | 6.950453 |
module div_pipelined (
clk,
rst,
z,
d,
quot,
rem
);
parameter WIDTH = 32;
localparam ZBITS = WIDTH * 2;
localparam DBITS = ZBITS / 2;
input clk;
input rst;
input [WIDTH -1:0] z;
input [DBITS -1:0] d;
output [DBITS -1:0] quot;
output [DBITS -1:0] rem;
reg [DBITS-1:0] quot;
... | 6.698593 |
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