code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Add_full_134 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_268 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_267 M2 (
.sum(sum),
.... | 7.399883 |
module Add_full_133 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_266 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_265 M2 (
.sum(sum),
.... | 7.117053 |
module Add_rca_4_34 (
sum,
c_out,
a,
b,
c_in
);
output [3:0] sum;
input [3:0] a;
input [3:0] b;
input c_in;
output c_out;
wire c_in2, c_in3, c_in4;
Add_full_136 M1 (
.sum(sum[0]),
.c_out(c_in2),
.a(a[0]),
.b(b[0]),
.c_in(c_in)
);
Add_full_135 M2 (
... | 7.071129 |
module Add_full_132 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_264 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_263 M2 (
.sum(sum),
.... | 7.36681 |
module Add_full_131 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_262 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_261 M2 (
.sum(sum),
.... | 7.128257 |
module Add_full_130 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_260 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_259 M2 (
.sum(sum),
.... | 7.314594 |
module Add_full_129 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_258 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_257 M2 (
.sum(sum),
.... | 7.265673 |
module Add_rca_4_33 (
sum,
c_out,
a,
b,
c_in
);
output [3:0] sum;
input [3:0] a;
input [3:0] b;
input c_in;
output c_out;
wire c_in2, c_in3, c_in4;
Add_full_132 M1 (
.sum(sum[0]),
.c_out(c_in2),
.a(a[0]),
.b(b[0]),
.c_in(c_in)
);
Add_full_131 M2 (
... | 7.025751 |
module Add_rca_5 (
sum,
c_out,
a,
b,
c_in
);
output [31:0] sum;
input [31:0] a;
input [31:0] b;
input c_in;
output c_out;
wire c_in4, c_in8, c_in12, c_in16, c_in20, c_in24, c_in28;
Add_rca_4_40 M1 (
.sum(sum[3:0]),
.c_out(c_in4),
.a(a[3:0]),
.b(b[3:0]),
.... | 6.609424 |
module div_number #(
parameter EXP_SIZE = `EXP_SIZE,
parameter MANTIS_SIZE = `MANTIS_SIZE
) (
number,
sign,
exp,
mantis
);
// Inputs
input [(1+EXP_SIZE+MANTIS_SIZE)-1:0] number;
// Outputs
output sign; // sign of the input number
output [EXP_SIZE -1:0] exp; // exponent of the ... | 7.739155 |
module div_odd (
iCLK,
oCLK,
div
);
input iCLK;
parameter WIDE = 32;
input [WIDE-1:0] div;
output oCLK;
wire oCLK;
reg outCLK;
reg cout;
reg [WIDE-1:0] cnt;
initial cnt = 0;
wire inCLK;
reg cc;
initial cc = 0;
always @(posedge cout) cc <= ~cc;
assign inCLK = iCLK ^ cc;
alw... | 6.538557 |
module Div_Op #(
parameter DIV_EXP = 7,
MULT_WIDTH = 18
) (
input [MULT_WIDTH-1:0] iReal,
input [MULT_WIDTH-1:0] iImag,
output [MULT_WIDTH-1:0] oReal,
output [MULT_WIDTH-1:0] oImag
);
// `include "fft_inc.h"
localparam CMPL_MSB = MULT_WIDTH - 1; // 17
assign oReal[CMPL_MSB:0] = {{DIV_... | 8.642861 |
module for Floating Point Divider
//synopsys translate_on
module div_pipe( inst_a, inst_b, z6, overflow, clock );
parameter sig_width = 23;
parameter exp_width = 8;
parameter ieee_compliance = 0;
input [sig_width+exp_width : 0] inst_a;
input [sig_width+exp_width : 0] inst_b;
input clock;
output [sig_width+exp_width... | 6.663055 |
module div_pipe_tb;
parameter clk_frequency = `CLK_FREQ;
parameter clk_period = 1e9 / clk_frequency; //ns
parameter DATA_W = 32;
parameter OPERS_PER_STAGE = 8;
parameter TEST_SZ = 100;
reg clk;
wire [DATA_W-1:0] dividend;
wire [DATA_W-1:0] divisor;
wire [DATA_W-1:0] quotient;
wire [DATA_W-1:0]... | 7.042401 |
module div_q (
clk,
ci,
co,
q
);
parameter N = 10, CounterBits = 4;
input clk, ci;
output co;
output reg [CounterBits-1:0] q = 0;
//可输出状态的 N 分频器/计数器
assign co = ci && (q == N - 1);
always @(posedge clk) begin
if (ci) begin
if (q == N - 1) begin
q = 0;
end else begin... | 6.667415 |
module: div
//description: radix-2 divider
//version: 1.4
/** log:
1.1: 增加了存储输入的逻辑 (不暂停M,W阶段, 数据前推导致输入发生变化)
1.2: 增加了flush逻辑，用于发生异常时停止计算除法（1.3: 合并到rst中）
1.3: 接口增加axi握手逻辑。其中“地址”握手(opn_valid)，认为是单向握手（slave随时都准备好接收输入）
1.4: rst时将一些reg清0，防止result出现xxx的情况
*/
module div_radix2(
input wire clk,
input wire ... | 7.088717 |
module DIV_REM (
quot,
rem,
a,
b
);
input [31:0] a, b;
output [31:0] quot, rem;
reg [31:0] quot, rem;
always @(a, b) begin
quot = 0;
rem = a;
while (rem >= b) begin
rem = rem - b;
quot = quot + 1;
end
end
endmodule
| 6.728676 |
module DIV_REM_TB;
reg [31:0] a, b;
wire [31:0] quot, rem;
DIV_REM divrem (
quot,
rem,
a,
b
);
initial begin
$dumpfile("DIV_REM_TB.vcd");
$dumpvars(0, DIV_REM_TB);
a = 4;
b = 16;
#10;
a = 11;
b = 121;
end
endmodule
| 6.613246 |
module:div_rill_clk
* file name:div_rill_clk.v
* syn:not yet
* author:rill
* date:2014-04-10
* modified by chaye
* data:2018-10-19
*/
module div_rill_clk (
input clk,
input rst, // high_power work
input enable, // high_power work
input [31:0] a,
input [31:0] b,
output reg [31:0] yshang,
... | 7.301812 |
module: div
//description: self-align divider
// 迭代次数约为，3 + max{2*(a的有效位数-b的有效位数), 0}
//version: 1.0
module div_self_align(
input clk,
input rst,
input [31:0] a, //divident
input [31:0] b, //divisor
input valid,
... | 7.088717 |
module adderN #(
N = 32
) (
input carryin,
input [N-1:0] x,
y,
output [N-1:0] s,
output carryout
);
wire [N:0] c;
assign c[0] = carryin;
assign carryout = c[N];
genvar i;
generate
for (i = 0; i < N; i = i + 1)
full_adder stage (
c[i],
x[i],
y[i],
... | 7.016561 |
module Div_shift_register #(
parameter dataIN_width = 4
) (
input clk,
rst,
sl,
sr,
ld,
leftIn,
rightIn,
input [dataIN_width - 1 : 0] D,
output reg [dataIN_width - 1 : 0] Q
);
always @(posedge clk) begin
if (rst) Q = 0;
else if (ld) Q = D;
else if (sl) // Shift Lef... | 8.61626 |
module div_signed (
aclr,
clock,
denom,
numer,
quotient,
remain
);
input aclr;
input clock;
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] quotient = sub_wire0[31:0];
wire [31:0... | 6.55091 |
module div_signed (
aclr,
clock,
denom,
numer,
quotient,
remain
);
input aclr;
input clock;
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
endmodule
| 6.55091 |
module AL_DFF_0 (
ar,
as,
clk,
d,
en,
sr,
ss,
q
);
input ar;
input as;
input clk;
input d;
input en;
input sr;
input ss;
output q;
wire al_00000256AA222B30;
wire al_00000256AA220C40;
wire al_00000256AA2206C0;
AL_MUX_release al_00000256AA399800 (
.i0 (q),
... | 6.538648 |
module AL_MUX_release (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.086364 |
module AL_DFF_release (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.837635 |
module div_signed_lpm_divide (
aclr,
clock,
denom,
numer,
quotient,
remain
) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`... | 6.744281 |
module div_signed (
aclr,
clock,
denom,
numer,
quotient,
remain
) /* synthesis synthesis_clearbox = 1 */;
input aclr;
input clock;
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] ... | 6.55091 |
module div_slice #(
parameter DATA_W = 32,
parameter STAGE = 1,
parameter OUTPUT_REG = 1
) (
input clk,
input [DATA_W-1:0] dividend_i,
input [DATA_W-1:0] divisor_i,
input [DATA_W-1:0] quotient_i,
output reg [DATA_W-1:0] dividend_o,
output reg [DATA_W-1:0] divisor_o,
output reg ... | 7.616411 |
module div_softmax (
(* DONT_TOUCH = "TRUE" *) input aclk, // input wire aclk
(* DONT_TOUCH = "TRUE" *) input rst_n,
(* DONT_TOUCH = "TRUE" *) input div_in_tvalid, // input wire s_axis_divisor_tvalid
(* DONT_TOUCH = "TRUE" *) output div_in_tready, // output wire s_axis_divisor_tready
(* DONT_TOUC... | 6.973936 |
module div_su (
clk,
ena,
z,
d,
q,
s,
div0,
ovf
);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width / 2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width-1:0] z; // divident
input [d_width-... | 7.088676 |
module div_subshift_frac #(
parameter DATA_W = 32
) (
input clk,
input rst,
input start,
output done,
input [DATA_W-1:0] dividend,
input [DATA_W-1:0] divisor,
output [DATA_W-1:0] quotient,
output [DATA_W-1:0] remainder
);
reg [DATA_W-1:0] divisor_reg;
always @(posedge clk,... | 7.432441 |
module div_subshift_frac_tb;
parameter clk_frequency = `CLK_FREQ;
parameter clk_period = 1e9 / clk_frequency; //ns
parameter DATA_W = 8;
parameter TEST_SZ = 100;
reg clk = 0;
reg rst = 0;
reg start = 0;
wire done;
//data
reg ... | 7.432441 |
module div_subshift_tb;
parameter clk_frequency = `CLK_FREQ;
parameter clk_period = 1e9 / clk_frequency; //ns
parameter DATA_W = 8;
parameter TEST_SZ = 1000;
reg clk = 0;
reg rst = 0;
reg start = 0;
wire done;
//data
reg [DAT... | 7.432441 |
module div_tb;
reg clk;
reg rst;
reg signed_div_i;
reg [23:0] opdata1_i;
reg [23:0] opdata2_i;
reg start_i;
reg annul_i;
//wire[47:0] result_o;
wire [23:0] quotient_o;
wire [23:0] remainder_o;
wire ready_o;
div div0 (
.clk(clk),
.rst(rst),
.signed_div_i(signed_div_i),
... | 7.423404 |
module DIV_temp (
input [31:0] dividend,
input [31:0] divisor,
input start,
input clock,
input reset,
output reg [31:0] q,
output reg [31:0] r,
output reg busy
);
wire ready;
wire [31:0] q_select;
wire [31:0] r_select;
wire [31:0] divide;
wire [31:0] diviso;
wire [31:0] middl... | 6.66627 |
module div_u (
input wire cpu_clk, //cpu clock
input wire cpu_rstn, //cpu clock
input wire start, //start divider
output wire done, //divider done
input wire [`DATA_WIDTH - 1 : 0] div_src_data1, //source data1 for divider
input wire [`DATA_WIDTH - 1 : 0] div_src_data2, //source data2 ... | 7.48277 |
module Div_UD_counter #(
parameter bus_width = 4
) (
input clk, // Synchronous Clock
input rst, // Synchronous Reset
input [bus_width - 1 : 0] D, // Input Data
input ld, // Control Signal - load
input ... | 6.997164 |
module div_umc_nor (
a,
b,
x
);
input wire a;
input wire b;
output wire x;
nor (x, a, b);
endmodule
| 6.668948 |
module div_umc_dlatch (
d,
en,
nq,
q
);
input wire d;
input wire en;
output wire nq;
output wire q;
reg dout;
always @(d or en) begin
if (en == 1'b1 && (d == 1'b0 || d == 1'b1)) dout <= d; // Use non-blocking
end
assign q = dout;
assign nq = ~dout;
initial dout <= 1'b0;
en... | 7.404428 |
module div_umc_not (
a,
x
);
input wire a;
output wire x;
not (x, a);
endmodule
| 6.892836 |
module div_umc_mux (
sel,
a0,
a1,
x
);
input wire sel;
input wire a0;
input wire a1;
output wire x;
assign x = sel ? a1 : a0;
endmodule
| 7.079873 |
module div_unit #(
parameter N = 32
) (
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] res, /* result */
output [N-1:0] rem /* remainder */
);
assign res = a / b;
assign rem = a % b;
endmodule
| 7.541329 |
module AL_DFF_0 (
ar,
as,
clk,
d,
en,
sr,
ss,
q
);
input ar;
input as;
input clk;
input d;
input en;
input sr;
input ss;
output q;
wire al_00000286DC2E4020;
wire al_00000286DC2E4BD0;
wire al_00000286DC2E4FF0;
AL_MUX_release al_00000286E4BCE450 (
.i0 (q),
... | 6.538648 |
module AL_MUX_release (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.086364 |
module AL_DFF_release (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.837635 |
module div_uu (
clk,
ena,
z,
d,
q,
s,
div0,
ovf
);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width / 2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width... | 7.103697 |
module div_uu (
clk,
ena,
z,
d,
q,
s,
div0,
ovf
);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width / 2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width... | 7.103697 |
module FA1(CO,S,A,B,CI,number);
module subtract(A,B,S,co,number);
input [4:0]A,B;
output [4:0]S;
output co;
output [50:0] number;
wire c0,c1,c2,c3,c4,c5;
wire [50:0] num0,num1,num2,num3,num4,num5,num6,num7,num8,num9,num10,num11;
//FA1 fa1(c1,S[0],A[0],B[0],1'b1,num5);
OR2 or1(c1,A[0],B[0],num4);
EN eo2(S[0],... | 6.66777 |
module REGP #(
parameter BW = 2
) (
input clk,
input rst_n,
output [BW-1:0] Q,
input [BW-1:0] D,
output [50:0] number
);
wire [50:0] numbers[0:BW-1];
genvar i;
generate
for (i = 0; i < BW; i = i + 1) begin
FD2 f0 (
Q[i],
D[i],
clk,
rst_n,... | 8.289611 |
module div_wrapper (
input clock,
input reset,
input start,
input flag_unsigned,
input [31:0] operand1,
input [31:0] operand2,
output [63:0] result,
output done
);
parameter DIV_CYCLES = 36;
wire [31:0] abs_opa1;
wire [31:0] abs_opa2;
wire [31:0] tmp_quotient;
wire... | 6.600708 |
module diy_uart (
input clk24MHz,
input btn_a,
output serial
);
wire baudclk;
wire busy;
reg [7:0] data = 0;
clock c (
.i_clk(clk24MHz),
.o_clk(baudclk)
);
simpleUARTtx u1 (
.i_data (data),
.i_start(~btn_a),
.i_clk (baudclk),
.o_busy (busy),
.o_lin... | 6.854335 |
module di_i2c_master #(
parameter NUM_ADDR_BYTES = 2,
parameter NUM_DATA_BYTES = 1
) (
input ifclk,
input resetb,
input [ 6:0] i2c_chip_addr, // physical address of i2c device
input [15:0] i2c_term_addr, // terminal address, often same as i2c_chip_addr
input [11:0] i2c_clk_... | 7.225593 |
module DJ (
input clock,
input resetn,
input [5:0] user_input,
input [5:0] other_sound,
output [31:0] sound_out
);
//TESTING
parameter //DELAY1 = 20'd1, //C4 261.63Hz
//DELAY2 = 20'd2, //D4 293.66Hz
//DELAY3 = 20'd3, //E4 329.63Hz
//DELAY4 = 20'd4, //F4 349.23Hz
//DELAY5 = 20'd5, //G... | 7.927634 |
module oscillator ( //gonna need 3-1 mux to make custom sound work
input clock,
input resetn,
input user_input,
input other_sound,
input [19:0] delay,
output [31:0] amplitude_out
);
wire flip;
wire [31:0] amplitude;
assign amplitude = flip ? 32'd100000000 : -32'd100000000; //volume lev... | 7.545427 |
module delay_counter (
input clock,
input resetn,
input [19:0] delay,
output reg flip
);
reg [19:0] count;
always @(posedge clock) begin
if (resetn) begin
flip <= 1'd0;
count <= 20'd0;
end else if (count == delay) begin //DELAY IS == TO 50MHz / DESIRED FREQUENCY
flip <= ... | 6.853164 |
module two_to_one_mux_large (
input [31:0] x,
input [31:0] y,
input select,
output [31:0] out
);
assign out = select ? x : y;
endmodule
| 7.326213 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b00... | 7.584821 |
module ram_1024_8 (
input I_CLK,
input [9:0] I_ADDR,
input [7:0] I_D,
input I_CE,
input I_WE,
output [7:0] O_D
);
wire [7:0] W_DO;
assign O_D = I_CE ? W_DO : 8'h00;
dpram #(10, 8) ram_1024_8 (
.clock_a(I_CLK),
.address_a(I_ADDR),
.data_a(I_D),
.wren_a(I_WE),
... | 6.598457 |
module ram_2N (
input I_CLK,
input [7:0] I_ADDR,
input [3:0] I_D,
input I_CE,
input I_WE,
output [3:0] O_D
);
dpram #(8, 4) ram_256_4 (
.clock_a(I_CLK),
.address_a(I_ADDR),
.data_a(I_D),
.wren_a(I_WE),
.enable_a(I_CE),
.q_a(O_D),
.clock_b(I_CLK)
);... | 7.010616 |
module double_scan (
input I_CLKA,
I_CLKB,
input [8:0] I_ADDRA,
I_ADDRB,
input [7:0] I_DA,
I_DB,
input I_CEA,
I_CEB,
input I_WEA,
I_WEB,
output [7:0] O_DA,
O_DB
);
dpram #(9, 8) ram_512_8 (
.clock_a(I_CLKA),
.address_a(I_ADDRA),
.data_a(I_DA),
.... | 7.220569 |
module ram_2048_8_8 (
input I_CLKA,
I_CLKB,
input [10:0] I_ADDRA,
I_ADDRB,
input [7:0] I_DA,
I_DB,
input I_CEA,
I_CEB,
input I_OEA,
I_OEB,
input I_WEA,
I_WEB,
output [7:0] O_DA,
O_DB
);
wire [7:0] W_DOA, W_DOB;
assign O_DA = I_CEA & I_OEA ? W_DOA : 8'h00;
a... | 6.558609 |
module dkong3_col_pal (
input I_CLK_24M,
input I_CLK_6M,
input [ 5:0] I_VRAM_D,
input [ 5:0] I_OBJ_D,
input I_CMPBLKn,
input [ 1:0] I_CPAL_SEL,
input I_DLCLK,
input [17:0] I_DLADDR,
input [ 7:0] I_DLDATA,
input I_DLWR,
output [3:0] O_R,
... | 8.124967 |
module dkong3_hv_count (
input I_CLK, // 24.576MHz
input I_RST_n,
input I_VFLIP,
output O_CLK,
output [9:0] H_CNT,
output [7:0] V_CNT,
output [7:0] VF_CNT,
output H_BLANKn,
output V_BLANKn,
output C_BLANKn,
output H_SYNCn,
output V_... | 7.44748 |
module DLROM #(
parameter AW,
parameter DW
) (
input CLK0,
input [(AW-1):0] AD0,
output reg [(DW-1):0] DO0,
input CLK1,
input [(AW-1):0] AD1,
input [(DW-1):0] DI1,
input WE1
);
reg [DW-1:0] core[0:((2**AW)-1)];
always @(posedge CLK0) ... | 6.544719 |
module DLROMB #(
parameter AW,
parameter DW
) (
input CLK0,
input [(AW-1):0] AD0,
output reg [(DW-1):0] DO0,
input CLK1,
input [(AW-1):0] AD1,
input [(DW-1):0] DI1,
input WE1
);
dpram #(AW, DW) dprom (
.clock_a(CLK1),
.wren_a... | 6.663645 |
module CLUT_PROM_512_8 (
input I_CLK,
input [8:0] I_ADDR,
output [7:0] O_DATA,
input I_DLCLK,
input [16:0] I_DLADDR,
input [ 7:0] I_DLDATA,
input I_DLWR
);
wire [7:0] dt;
DLROM #(9, 8) prom1d (
I_CLK,
I_ADDR,
dt,
I_DLCLK,
I_DLADDR[8:... | 6.761174 |
module CLUT_PROM_512_4 (
input I_CLK,
input [8:0] I_ADDR,
output [3:0] O_DATA,
input I_DLCLK,
input [16:0] I_DLADDR,
input [ 7:0] I_DLDATA,
input I_DLWR
);
wire [3:0] dt;
DLROM #(9, 4) prom1c (
I_CLK,
I_ADDR,
dt,
I_DLCLK,
I_DLADDR[8:... | 6.761174 |
module COL_PROM_256_4 (
input I_CLK,
input [7:0] I_ADDR,
output [3:0] O_DATA,
input I_DLCLK,
input [16:0] I_DLADDR,
input [ 7:0] I_DLDATA,
input I_DLWR
);
wire [3:0] dt;
DLROM #(8, 4) prom2n (
I_CLK,
I_ADDR,
dt,
I_DLCLK,
I_DLADDR[7:0... | 6.768249 |
module.
//----------------------------------------------------------------------------
module dkong3_video
(
input I_CLK_24M,
input I_CLK_12M,
input I_RESETn,
input [9:0]I_CPU_A,
input [7:0]I_CPU_D,
input I_VRAM_WRn,
input I_VRAM_RDn,
input [7:0]I_3E_Q,
... | 6.659433 |
module dkong3_vram (
input I_CLK_24M,
input I_CLK_12M,
input [ 9:0] I_AB,
input [ 7:0] I_DB,
input I_VRAM_WRn,
input I_VRAM_RDn,
input I_FLIP,
input [ 9:0] I_H_CNT,
input [ 7:0] I_VF_CNT,
input I_CMPBLK,
input I_GFXBANK,
i... | 7.844024 |
module DL #(
parameter INIT = 1'b0
) (
input G,
input D,
output Q
);
reg _l_Q;
initial begin
_l_Q = INIT;
end
always @(G or D) begin
if (G) begin
_l_Q = D;
end
end
assign Q = _l_Q;
endmodule
| 6.525841 |
module cpu (
input reset,
input clk,
input [3:0] btn,
output [3:0] led,
output [3:0] adr,
input [7:0] dout
);
wire [4:0] op = dout[7:3];
wire [2:0] sss = dout[2:0]; // Instruction set (op is operator,sss is operalnd)
reg c_flag;
reg [3:0] regs[7:0];
assign led = regs[6];
assign adr... | 6.869387 |
module madd_0 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_0 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.38934 |
module madd_core_0 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 7.075576 |
module madd_1 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_1 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.378703 |
module madd_core_1 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 6.72729 |
module madd_2 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_2 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.822756 |
module madd_core_2 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 7.29891 |
module madd_3 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_3 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.460978 |
module madd_core_3 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 6.94262 |
module madd_4 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_4 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.213472 |
module madd_core_4 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 7.237288 |
module madd_5 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_5 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.624669 |
module madd_core_5 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 7.25243 |
module madd_6 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_6 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.792297 |
module madd_core_6 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 7.174136 |
module madd_7 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_7 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.199545 |
module madd_core_7 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 6.978479 |
module madd_8 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_8 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.510954 |
module madd_core_8 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 7.230733 |
module madd_9 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_9 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 8.333964 |
module madd_core_9 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;
... | 7.097491 |
module madd_10 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_10 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.268501 |
module madd_core_10 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;... | 6.887625 |
module madd_11 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_11 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.459453 |
module madd_core_11 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;... | 7.050067 |
module madd_12 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_12 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 8.083752 |
module madd_core_12 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0;... | 7.503245 |
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