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11.5
module madd_63 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_63 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.13676
module madd_core_63 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.026573
module madd_64 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_64 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.939918
module madd_core_64 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.432946
module madd_65 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_65 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.328459
module madd_core_65 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.947373
module madd_66 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_66 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.684317
module madd_core_66 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.160887
module madd_67 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_67 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.438511
module madd_core_67 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.227197
module madd_68 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_68 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.027857
module madd_core_68 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.115283
module madd_69 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_69 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.631681
module madd_core_69 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.030274
module madd_70 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_70 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.435232
module madd_core_70 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.090102
module madd_71 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_71 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.285968
module madd_core_71 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.033219
module multiplier_core_0 ( input CLK, input update, input [32-1:0] a, input [16-1:0] b, output [48-1:0] c ); reg signed [32-1:0] _a; reg signed [16-1:0] _b; wire signed [48-1:0] _mul; reg signed [48-1:0] _pipe_mul0; reg signed [48-1:0] _pipe_mul1; assign _mul = _a * _b; assign c =...
6.701364
module madd_72 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_72 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.772702
module madd_core_72 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.279743
module madd_73 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_73 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.358724
module madd_core_73 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.068206
module madd_74 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_74 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.349505
module madd_core_74 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.203017
module madd_75 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_75 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.103612
module madd_core_75 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.828493
module madd_76 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_76 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.425147
module madd_core_76 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.010291
module madd_77 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_77 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.962909
module madd_core_77 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.987065
module madd_78 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_78 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.771826
module madd_core_78 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.894031
module madd_79 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_79 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.450523
module madd_core_79 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.798434
module madd_80 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_80 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.878092
module madd_core_80 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.850961
module madd_81 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_81 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.022567
module madd_core_81 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.835567
module madd_82 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_82 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.479733
module madd_core_82 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.080386
module madd_83 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_83 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.45416
module madd_core_83 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.16249
module madd_84 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_84 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.78102
module madd_core_84 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.311377
module madd_85 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_85 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.36101
module madd_core_85 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.91454
module madd_86 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_86 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.608334
module madd_core_86 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.136299
module madd_87 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_87 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.302816
module madd_core_87 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.17607
module madd_88 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_88 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.102819
module madd_core_88 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.077287
module madd_89 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_89 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.45375
module madd_core_89 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.881693
module madd_90 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_90 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.795502
module madd_core_90 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.889497
module madd_91 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_91 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.697527
module madd_core_91 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.9619
module madd_92 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_92 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.867858
module madd_core_92 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.124792
module madd_93 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_93 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.286898
module madd_core_93 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.971947
module madd_94 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_94 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.628797
module madd_core_94 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.07661
module madd_95 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_95 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.198144
module madd_core_95 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.842721
module madd_96 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_96 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_96 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.107403
module madd_97 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_97 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_97 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
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module madd_98 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_98 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_98 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.92784
module madd_99 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_99 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_99 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
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module madd_100 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_100 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_100 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
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module madd_101 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_101 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_101 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.978528
module madd_102 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_102 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_102 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.256444
module madd_103 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_103 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_103 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.07666
module madd_104 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_104 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_104 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.17913
module madd_105 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_105 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_105 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.036982
module madd_106 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_106 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_106 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.158483
module madd_107 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_107 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_107 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.14358
module madd_108 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_108 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_108 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.122351
module madd_109 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_109 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_109 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.110672
module madd_110 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_110 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_110 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.848549
module madd_111 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_111 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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module madd_core_111 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.876545
module madd_112 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_112 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
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