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11.5
module madd_13 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_13 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.615394
module madd_core_13 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.166958
module madd_14 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_14 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.883577
module madd_core_14 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.311735
module madd_15 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_15 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.348819
module madd_core_15 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.108038
module madd_16 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_16 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.75619
module madd_core_16 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.286311
module madd_17 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_17 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.547298
module madd_core_17 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.095855
module madd_18 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_18 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.42845
module madd_core_18 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.978232
module madd_19 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_19 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.900591
module madd_core_19 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.252818
module madd_20 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_20 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.367202
module madd_core_20 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.150609
module madd_21 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_21 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.374002
module madd_core_21 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.01558
module madd_22 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_22 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.54798
module madd_core_22 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.32209
module madd_23 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_23 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.223919
module madd_core_23 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.11513
module madd_24 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_24 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.481331
module madd_core_24 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.397771
module madd_25 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_25 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.042304
module madd_core_25 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.905388
module madd_26 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_26 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.090223
module madd_core_26 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.945875
module madd_27 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_27 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.118292
module madd_core_27 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.912787
module madd_28 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_28 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.033495
module madd_core_28 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.89989
module madd_29 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_29 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.50618
module madd_core_29 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.893056
module madd_30 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_30 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.745506
module madd_core_30 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.72693
module madd_31 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_31 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.213954
module madd_core_31 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.779198
module madd_32 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_32 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
8.219739
module madd_core_32 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.261807
module madd_33 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_33 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.393849
module madd_core_33 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.950566
module madd_34 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_34 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.434105
module madd_core_34 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.027071
module madd_35 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_35 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.431819
module madd_core_35 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.872168
module madd_36 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_36 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.439192
module madd_core_36 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.033348
module madd_37 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_37 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.446357
module madd_core_37 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.96283
module madd_38 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_38 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.201671
module madd_core_38 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.07303
module madd_39 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_39 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.857237
module madd_core_39 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.968193
module madd_40 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_40 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.270389
module madd_core_40 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.851155
module madd_41 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_41 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.481271
module madd_core_41 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.917561
module madd_42 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_42 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.886019
module madd_core_42 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.1649
module madd_43 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_43 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.340119
module madd_core_43 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.122479
module madd_44 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_44 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.780669
module madd_core_44 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.30118
module madd_45 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_45 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.327906
module madd_core_45 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.938778
module madd_46 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_46 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.003571
module madd_core_46 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.006858
module madd_47 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_47 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.856003
module madd_core_47 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.918249
module madd_48 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_48 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.411129
module madd_core_48 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.370275
module madd_49 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_49 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.990335
module madd_core_49 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.134738
module madd_50 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_50 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.899295
module madd_core_50 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.859006
module madd_51 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_51 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.211407
module madd_core_51 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.920656
module madd_52 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_52 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.742611
module madd_core_52 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.177167
module madd_53 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_53 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.594019
module madd_core_53 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.122018
module madd_54 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_54 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.651738
module madd_core_54 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.145022
module madd_55 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_55 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.275774
module madd_core_55 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.928258
module madd_56 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_56 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.740809
module madd_core_56 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.16285
module madd_57 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_57 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.207506
module madd_core_57 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.117638
module madd_58 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_58 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.958486
module madd_core_58 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.095416
module madd_59 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_59 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.523132
module madd_core_59 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.04707
module madd_60 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_60 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.727946
module madd_core_60 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.022488
module madd_61 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_61 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.435546
module madd_core_61 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
6.977378
module madd_62 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_62 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.948095
module madd_core_62 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0;...
7.303843