code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module d_latch_nand (
d,
en,
q,
q_bar
);
input en;
input d;
output wire q, q_bar;
wire w1, w2;
nand n0 (w1, d, en);
nand n1 (w2, en, ~d);
nand n2 (q, w1, q_bar);
nand n3 (q_bar, w2, q);
endmodule
| 7.403983 |
module d_latch_nand_tb ();
reg en, d;
wire q, q_bar;
d_latch_nand tb (
d,
en,
q,
q_bar
);
initial begin
en = 0;
d = 0;
#10 en = 1;
d = 0;
#10 en = 1;
d = 1;
#10 en = 1;
d = 0;
#10 en = 0;
#10 en = 1;
d = 1;
end
endmodule
| 6.777034 |
module d_latch_nor (
d,
en,
q,
q_bar
);
input en;
input d;
output wire q, q_bar;
wire w1, w2;
nor n0 (w1, d, en);
nor n1 (w2, en, ~d);
nor n2 (q, w1, q_bar);
nor n3 (q_bar, w2, q);
endmodule
| 7.704355 |
module d_latch_nor_tb ();
reg en, d;
wire q, q_bar;
d_latch_nor tb (
d,
en,
q,
q_bar
);
initial begin
en = 1;
d = 0;
#10 en = 0;
d = 0;
#10 en = 0;
d = 1;
#10 en = 0;
d = 0;
end
endmodule
| 6.702869 |
module dlatch_reset (
data, // Data Input
en, // LatchInput
reset, // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, en, reset;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code St... | 6.986929 |
module DLatch_Test;
// Input and outputs
logic [7:0] d8, q8;
logic [15:0] d16, q16;
// CLK and RST pins
logic clk, rst;
// Instantiate modules
DLatch #(
.WIDTH(8)
) latch8bit (
.d (d8),
.clk(clk),
.q (q8),
.rst(rst)
);
DLatch #(
.WIDTH(16)
) latch16bit (
... | 6.874266 |
module dlatch_using_always ();
reg q;
reg d, enable;
always @(d or enable)
if (enable) begin
q = d;
end
initial begin
$monitor(" ENABLE = %b D = %b Q = %b", enable, d, q);
#1 enable = 0;
#1 d = 1;
#1 enable = 1;
#1 d = 0;
#1 d = 1;
#1 d = 0;
#1 enable = 0;
#... | 7.025348 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge ... | 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
in... | 8.55547 |
module inverse_winograd_adder_30_3 (
input clock,
input [29:0] data0x,
input [29:0] data1x,
input [29:0] data2x,
input [29:0] data3x,
input [29:0] data4x,
input [29:0] data5x,
output [29:0] result
);
reg [32:0] pipeline_0_0;
reg [32:0] pipeline_0_1;
reg [32:0] pipeline_0_2;
reg ... | 7.392105 |
module winograd_adder_16_20_4 (
input clken,
input clock,
input [15:0] data0x,
input [15:0] data1x,
input [15:0] data2x,
input [15:0] data3x,
input [15:0] data4x,
input [15:0] data5x,
input [15:0] data6x,
input [15:0] data7x,
input [15:0] data8x,
input [15:0] data9x,
... | 7.269446 |
module winograd_dsp_16 (
input clk,
input ena,
input aclr,
input [15:0] ay,
input [15:0] by,
input [2:0] coefsela,
input [2:0] coefselb,
output [15:0] resulta,
output [15:0] resultb
);
reg [15:0] coefa, coefb, ay_reg, by_reg, resa_reg, resb_reg;
assign resulta = resa_reg;
assi... | 7.261044 |
module stream_buffer_5_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_15 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_5_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_05 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_5_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_35 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_5_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_25 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_4_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_04 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_4_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_14 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_4_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_24 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_4_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_34 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_2_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_22 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_2_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_32 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_2_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_02 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_2_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_12 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module weight_cache_2048_8_0_weight_init_21 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_20 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_23 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_22 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_25 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_24 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module dot_product_16_8_30_4 (
input clk,
input i_reset,
input [15:0] i_features_0,
input [7:0] i_weights_0,
input [15:0] i_features_1,
input [7:0] i_weights_1,
input [15:0] i_features_2,
input [7:0] i_weights_2,
input [15:0] i_features_3,
input [7:0] i_weights_3,
output [23:... | 7.079393 |
module weight_cache_2048_8_0_weight_init_02 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_03 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_01 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_00 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_05 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_04 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module stream_buffer_1_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_11 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_1_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_01 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_1_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_31 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_1_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_21 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_0_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_00 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_0_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_10 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_0_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_20 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_0_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_30 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module pipelined_xor_tree_16 (
input clk,
input reset,
input [15:0] signal,
output reduced_signal
);
reg pipeline_0_0;
reg pipeline_0_1;
reg pipeline_0_2;
reg pipeline_1_0;
reg pipeline_1_1;
reg pipeline_1_2;
reg pipeline_2_0;
reg pipeline_2_1;
reg pipeline_2_2;
reg pipeline_3_0;
... | 7.420117 |
module pooling (
input clk,
input i_valid,
input i_reset,
input [15:0] i_result_0,
input [15:0] i_result_1,
input [15:0] i_result_2,
input [15:0] i_result_3,
output [15:0] o_result,
output o_valid
);
reg [15:0] buffer_0_0;
reg [15:0] buffer_0_1;
reg [15:0] buffer_1_0;
reg [1... | 6.556182 |
module stream_buffer_3_3 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_33 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_3_2 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_23 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_3_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_13 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module stream_buffer_3_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [13:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [13:0... | 6.648114 |
module buffer_16_12100_buffer_init_03 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 7.192169 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge ... | 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module inverse_winograd_adder_30_3 (
input clock,
input [29:0] data0x,
input [29:0] data1x,
input [29:0] data2x,
input [29:0] data3x,
input [29:0] data4x,
input [29:0] data5x,
output [29:0] result
);
reg [32:0] pipeline_0_0;
reg [32:0] pipeline_0_1;
reg [32:0] pipeline_0_2;
reg ... | 7.392105 |
module winograd_adder_16_20_4 (
input clken,
input clock,
input [15:0] data0x,
input [15:0] data1x,
input [15:0] data2x,
input [15:0] data3x,
input [15:0] data4x,
input [15:0] data5x,
input [15:0] data6x,
input [15:0] data7x,
input [15:0] data8x,
input [15:0] data9x,
... | 7.269446 |
module winograd_dsp_16 (
input clk,
input ena,
input aclr,
input [15:0] ay,
input [15:0] by,
input [2:0] coefsela,
input [2:0] coefselb,
output [15:0] resulta,
output [15:0] resultb
);
reg [15:0] coefa, coefb, ay_reg, by_reg, resa_reg, resb_reg;
assign resulta = resa_reg;
assi... | 7.261044 |
module stream_buffer_5_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_15 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module stream_buffer_5_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_05 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module dot_product_16_8_30_2 (
input clk,
input i_reset,
input [15:0] i_features_0,
input [7:0] i_weights_0,
input [15:0] i_features_1,
input [7:0] i_weights_1,
output [23:0] o_result
);
wire [63:0] chains_0;
wire [23:0] res;
reg [15:0] f_pipeline_0_0;
reg [7:0] w_pipeline_0_0;
re... | 7.079393 |
module weight_cache_2048_8_0_weight_init_05 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_03 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_02 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_01 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_00 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module weight_cache_2048_8_0_weight_init_04 (
input clk,
input wen0,
input wen1,
input [10:0] addr0,
input [7:0] wdata0,
output [7:0] data0,
input [10:0] addr1,
input [7:0] wdata1,
output [7:0] data1
);
reg [10:0] addr0_reg;
wire [10:0] addr0_wire;
reg [ 7:0] data0_reg;
wi... | 7.595113 |
module stream_buffer_4_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_04 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module stream_buffer_4_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_14 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module stream_buffer_2_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_02 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module stream_buffer_2_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_12 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module stream_buffer_1_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
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