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11.5
module madd_212 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_212 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
8.021595
module madd_core_212 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.558275
module madd_213 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_213 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.478409
module madd_core_213 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.078695
module madd_214 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_214 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.889576
module madd_core_214 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.342409
module madd_215 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_215 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.399203
module madd_core_215 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.151178
module multiplier_2 ( input CLK, input update, input [32-1:0] a, input [16-1:0] b, output [48-1:0] c ); multiplier_core_2 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule
7.420757
module multiplier_core_2 ( input CLK, input update, input [32-1:0] a, input [16-1:0] b, output [48-1:0] c ); reg signed [32-1:0] _a; reg signed [16-1:0] _b; wire signed [48-1:0] _mul; reg signed [48-1:0] _pipe_mul0; reg signed [48-1:0] _pipe_mul1; assign _mul = _a * _b; assign c =...
6.701364
module madd_216 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_216 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.993033
module madd_core_216 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.41103
module madd_217 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_217 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.535654
module madd_core_217 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.288362
module madd_218 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_218 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.282179
module madd_core_218 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.071176
module madd_219 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_219 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.702161
module madd_core_219 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.28672
module madd_220 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_220 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.351189
module madd_core_220 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.906476
module madd_221 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_221 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.383561
module madd_core_221 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.093031
module madd_222 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_222 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.629639
module madd_core_222 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.063583
module madd_223 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_223 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.195357
module madd_core_223 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.028063
module madd_224 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_224 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.569993
module madd_core_224 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.355196
module madd_225 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_225 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.67207
module madd_core_225 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.10454
module madd_226 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_226 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.172302
module madd_core_226 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.020729
module madd_227 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_227 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.161535
module madd_core_227 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.057499
module madd_228 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_228 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.211374
module madd_core_228 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.942227
module madd_229 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_229 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.585942
module madd_core_229 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.882529
module madd_230 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_230 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.860601
module madd_core_230 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.803058
module madd_231 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_231 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.119056
module madd_core_231 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.795827
module madd_232 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_232 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.919814
module madd_core_232 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.605803
module madd_233 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_233 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.280618
module madd_core_233 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.987966
module madd_234 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_234 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.175196
module madd_core_234 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.42808
module madd_235 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_235 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.246048
module madd_core_235 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.904299
module madd_236 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_236 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.231941
module madd_core_236 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.88181
module madd_237 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_237 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.184606
module madd_core_237 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.948401
module madd_238 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_238 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.936719
module madd_core_238 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.9448
module madd_239 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_239 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.620094
module madd_core_239 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.036675
module madd_240 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_240 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.325472
module madd_core_240 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.037842
module madd_241 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_241 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.743063
module madd_core_241 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.943163
module madd_242 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_242 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.513565
module madd_core_242 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.239928
module madd_243 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_243 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.06572
module madd_core_243 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.016362
module madd_244 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_244 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.230749
module madd_core_244 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.282273
module madd_245 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_245 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.868346
module madd_core_245 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.989294
module madd_246 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_246 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.278154
module madd_core_246 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.069938
module madd_247 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_247 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.100856
module madd_core_247 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.963508
module madd_248 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_248 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.156997
module madd_core_248 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.963922
module madd_249 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_249 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.651657
module madd_core_249 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.169825
module madd_250 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_250 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.85112
module madd_core_250 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.757697
module madd_251 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_251 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.573656
module madd_core_251 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.853614
module madd_252 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_252 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.22199
module madd_core_252 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.136533
module madd_253 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_253 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.849815
module madd_core_253 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.903962
module madd_254 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_254 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.850619
module madd_core_254 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.258374
module madd_255 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_255 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.27014
module madd_core_255 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.077342
module madd_256 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_256 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.374284
module madd_core_256 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.148856
module madd_257 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_257 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.681481
module madd_core_257 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.013165
module madd_258 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_258 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.687903
module madd_core_258 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.934743
module madd_259 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_259 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
7.399785
module madd_core_259 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
7.066334
module madd_260 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); madd_core_260 madd ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c), .d(d) ); endmodule
6.945514
module madd_core_260 ( input CLK, input update, input [8-1:0] a, input [8-1:0] b, input [16-1:0] c, output [16-1:0] d ); reg signed [ 8-1:0] _a; reg signed [ 8-1:0] _b; reg signed [16-1:0] _c; wire signed [16-1:0] _mul; wire signed [16-1:0] _madd; reg signed [16-1:0] _pipe_madd0...
6.864328