code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module buffer_16_24200_buffer_init_11 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module stream_buffer_1_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_01 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module stream_buffer_0_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_00 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module stream_buffer_0_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_10 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module pipelined_xor_tree_16 (
input clk,
input reset,
input [15:0] signal,
output reduced_signal
);
reg pipeline_0_0;
reg pipeline_0_1;
reg pipeline_0_2;
reg pipeline_1_0;
reg pipeline_1_1;
reg pipeline_1_2;
reg pipeline_2_0;
reg pipeline_2_1;
reg pipeline_2_2;
reg pipeline_3_0;
... | 7.420117 |
module pooling (
input clk,
input i_valid,
input i_reset,
input [15:0] i_result_0,
input [15:0] i_result_1,
input [15:0] i_result_2,
input [15:0] i_result_3,
output [15:0] o_result,
output o_valid
);
reg [15:0] buffer_0_0;
reg [15:0] buffer_0_1;
reg [15:0] buffer_1_0;
reg [1... | 6.556182 |
module stream_buffer_3_1 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_13 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module stream_buffer_3_0 (
input clk,
input i_reset,
input i_wen0,
input i_wen1,
input [15:0] i_ddr,
input [15:0] i_pool,
input i_eltwise_sel,
input [15:0] i_eltwise,
input [14:0] i_waddr,
output [15:0] o_feature_0,
output [15:0] o_feature_1,
output o_done
);
reg [14:0... | 6.648114 |
module buffer_16_24200_buffer_init_03 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [... | 6.6434 |
module DLF (
input clk,
input reset,
input dirSig,
input enable,
input [3:0] kMode,
output carry,
output borrow,
// For debug
output reg [19:0] count
);
//reg [19:0]count;
reg [19:0] kTop;
always @(kMode) begin
case (kMode)
4'b0001: kTop <= 7;
4'b0010: kTop <=... | 6.934305 |
module DLL_DELAY_ELEMENT (
out,
pass,
ret,
en,
sel_n,
in
);
output out;
output pass;
input ret;
input en;
input sel_n;
input in;
wire r0_out;
wire r1_out;
wire p1_out;
`ifdef SIM
assign #1 r0_out = ~(en & sel_n);
assign #1 r1_out = ~(in & r0_out);
assign #1 p1_out = ~r0... | 6.539854 |
module dll_divider (
input clock,
input [DEN_WIDTH-1:0] denom,
input [NUM_WIDTH-1:0] numer,
output wire [NUM_WIDTH-1:0] quotient,
output wire [DEN_WIDTH-1:0] remain
);
parameter NUM_WIDTH = 9;
parameter DEN_WIDTH = 9;
lpm_divide lpm_divide_component (
... | 7.732776 |
module DLL_MON (
SCLK,
reset_n,
code_update,
dll_dly_diff,
dfi_ctrlupd_req
);
input SCLK;
input reset_n;
// Port: System
output code_update;
input dll_dly_diff;
// Port: NWL_PHY
input dfi_ctrlupd_req;
/// I/O_End <<<---
assign code_update = 1'b0;
/// Components_Start -... | 6.501484 |
module dll_multiplier (
input clock,
input [INPUT_A_WIDTH-1:0] dataa,
input [INPUT_B_WIDTH-1:0] datab,
output wire [ OUTPUT_WIDTH-1:0] result
);
parameter INPUT_A_WIDTH = 9;
parameter INPUT_B_WIDTH = 9;
localparam OUTPUT_WIDTH = INPUT_A_WIDTH + INPUT_B_WIDTH;... | 6.834784 |
module dll_priority_enc(
input clk,
input [18:0] in,
output wire [4:0] out);
//The priority encoder is divided into a two-
//stage pipeline for timing requirements.
//FIXME Parameters with preprocessor or defines.
`PRESERVE reg [12:8] in_km1;
`PRESERVE reg [4:0] pos;... | 7.622492 |
module dll_truncate (
input [ 4:0] index,
input [18:0] in,
output reg [10:0] out
);
//FIXME Parameters with preprocessor or defines.
parameter INDEX_WIDTH = 1;
parameter INPUT_WIDTH = 1;
parameter OUTPUT_WIDTH = 1;
always @(index or in) begin
case (index)
/*generate
... | 7.940961 |
module DLN #(
parameter INIT = 1'b0
) (
input G,
input D,
output Q
);
reg _l_Q;
initial begin
_l_Q = INIT;
end
always @(G or D) begin
if (~G) begin
_l_Q = D;
end
end
assign Q = _l_Q;
endmodule
| 6.654252 |
module dlsc_absdiff #(
parameter WIDTH = 32,
parameter META = 1
) (
input wire clk,
input wire rst,
input wire in_valid,
input wire [META-1:0] in_meta,
input wire [WIDTH-1:0] in0,
input wire ... | 7.48364 |
module dlsc_address_decoder #(
parameter ADDR = 32,
parameter RANGES = 1,
parameter RANGESB = 1,
parameter [(RANGES*ADDR)-1:0] MASKS = {(RANGES*ADDR){1'b0}}, // selects address bits that don't have to match BASES
parameter [(RANGES*ADDR)-1:0] BASES = {(RANGES * ADDR) {1'b0}}
) (
input wire [... | 7.669847 |
module dlsc_apb_bfm #(
parameter ADDR = 32,
parameter DATA = 32,
parameter STRB = (DATA / 8)
) (
// System
input wire clk,
input wire rst,
// APB
output reg [ADDR-1:0] apb_addr,
output reg apb_sel,
output reg apb_enable,
output reg apb_wr... | 6.998642 |
module dlsc_apb_to_wb #(
parameter REGISTER = 1, // enable registering on interfaces (otherwise module is purely combinational)
parameter ADDR = 32,
parameter DATA = 32,
// derived; don't touch
parameter STRB = (DATA / 8)
) (
// system
input wire clk,
input wire rst,
// ** A... | 7.552358 |
module dlsc_arbiter #(
parameter CLIENTS = 2
) (
input wire clk,
input wire rst,
input wire update,
input wire [CLIENTS-1:0] in,
output wire [CLIENTS-1:0] out
);
generate
if (CLIENTS > 1) begin : GEN_ARB
// one-hot select for highest priority
reg [CLIENTS-1:0] pri;
... | 7.360296 |
module dlsc_axi_router_channel_arbiter #(
parameter SOURCES = 1,
parameter SOURCESB = 1,
parameter SINKS = 1,
parameter SINKSB = 1,
parameter LANES = 1,
parameter LANESB = 1
) (
// System
input wire clk,
input wire rst,
// Lanes status
input wire [LANES-1:0] lane_... | 6.612306 |
module dlsc_axi_router_channel_lane #(
parameter DATA = 32,
parameter SOURCES = 1,
parameter SOURCESB = 1,
parameter SINKS = 1,
parameter SINKSB = 1
) (
// System
input wire clk,
input wire rst,
// Lane status
output wire lane_next_idle,
// Lane arbitration
in... | 6.612306 |
module dlsc_axid_slave_dummy #(
parameter WIDTH = 32
) (
input wire clk,
input wire rst,
output reg axid_ar_ready,
input wire axid_ar_valid,
input wire [31:0] axid_ar_addr,
input wire [ 3:0] axid_ar_len,
input wire axid_r_ready,
output reg ... | 6.641134 |
module dlsc_bin2gray #(
parameter BITS = 4
) (
input wire [BITS-1:0] bin,
output wire [BITS-1:0] gray
);
assign gray = (bin >> 1) ^ bin;
endmodule
| 7.721214 |
module dlsc_cfgreg #(
parameter INDEX = 0, // address of this register
parameter DATA = 1, // width of register
parameter ADDR = 4, // width of write address input
parameter CFG_DATA = DATA, // width of write data input
parameter WARNINGS = 1 // enable warnings about los... | 9.407683 |
module dlsc_cfgreg_loader #(
parameter ADDR = 4, // bits for cfgreg select address; must be enough for DEPTH+1 (all 1's is invalid)
parameter DEPTH = (2**ADDR)-1, // number of cfgregs to load; this is also the length of the configuration stream
parameter CFG_DATA = ... | 7.380916 |
module dlsc_cfgreg_slice #(
parameter DATA = 1, // width of register
parameter RESET = {DATA{1'bx}}, // reset value for register
parameter IN_DATA = DATA, // width of input port
parameter WARNINGS = 1 // enable warnings about lost MSbits
) (
// system
i... | 7.260009 |
module dlsc_cfgrom #(
parameter DATA = 4, // bits for data (output)
parameter ADDR = 4, // bits for address (input)
parameter DEPTH = (2**ADDR), // entries in memory
parameter RESET = 0, // output register reset value
parameter PI... | 8.441823 |
module dlsc_cfgroq #(
parameter DATA = 4, // bits for data
parameter ADDR = 4, // bits for address
parameter DEPTH = (2 ** ADDR) // entries in memory
) (
// system
input wire clk,
// config
// memory must be populated by writing sequentially from back to front
inp... | 7.642793 |
module dlsc_clkdetect #(
parameter PROP = 15, // max allowable prop delay from clk through clk_monitor and back to clk domain
parameter FILTER = 15 // number of changes that must be detected before clock is declared active
) (
// system
input wire clk,
input wire rst,
... | 7.124559 |
module dlsc_clocksynth #(
parameter FREQ_IN = 100000000,
parameter FREQ_OUT = 115200
) (
// input clock
input wire clk,
input wire rst,
// enable for synthesized clock
// (will always be enabled in reset, and on 1st cycle following reset)
output wire clk_en_out
);
`include "dlsc_clo... | 7.238749 |
module dlsc_compex #(
parameter DATA = 16,
parameter ID = 1,
parameter PIPELINE = 0
) (
// system
input wire clk,
// input
input wire [ID-1:0] in_id0,
input wire [ID-1:0] in_id1,
input wire [DATA-1:0] in_data0,
input wire ... | 8.761165 |
module dlsc_cpu1_alu #(
parameter DEVICE = "GENERIC"
) (
// control
input wire [3:0] alu_op,
input wire alu_signed,
// input operands
input wire [31:0] in_a, // from register
input wire [31:0] in_b, // from register or constant
// output
output wire [31:0] out_d, // to reg... | 7.246531 |
module dlsc_cpu1_icache_way #(
parameter SIZE = 9, // cache size is 2**SIZE words
parameter LINE = 4, // line size is 2**LINE (have 2**(SIZE-LINE) tags)
parameter DATA = 32, // width of word
parameter TAG = 32, // width of tag
parameter PREFETCH = 0 // enable prefetcher
) (... | 7.855419 |
module dlsc_csr_bfm #(
parameter ADDR = 32,
parameter DATA = 32
) (
// System
input wire clk,
input wire rst,
// CSR Command
output reg csr_cmd_valid,
output reg csr_cmd_write,
output reg [ADDR-1:0] csr_cmd_addr,
output reg [DATA-1:0] csr_cmd_data,
// ... | 7.109414 |
module dlsc_delayline_channel #(
parameter DATA = 1, // width of data to be delayed
parameter INERTIAL = 0, // use inertial rather than transport delay
parameter DELAY = 32, // maximum delay
parameter DB = 5 // bits to select delay
) (
// system
input wire clk,
// timeb... | 7.451488 |
module dlsc_demosaic_vng6_absdiff #(
parameter DATA = 8
) (
input wire clk,
input wire clk_en,
input wire [DATA-1:0] in0,
input wire [DATA-1:0] in1,
output wire [DATA-1:0] out
);
`include "dlsc_synthesis.vh"
reg [DATA:0] diff;
// tak... | 7.47206 |
module dlsc_demosaic_vng6_compex #(
parameter DATA = 16,
parameter PIPELINE = 0
) (
input wire clk,
input wire clk_en,
input wire [DATA-1:0] in_data0,
input wire [DATA-1:0] in_data1,
output wire [DATA-1:0] out_data0,
output wire ... | 7.47206 |
module dlsc_demosaic_vng6_diag_green #(
parameter DATA = 8
) (
input wire clk,
input wire clk_en,
input wire [3:0] st,
input wire px_push,
input wire [DATA-1:0] px_in,
output wire [DATA-1:0] adj_absdiff,
output wire diag_green_push,
output reg [DATA : 0] di... | 7.47206 |
module dlsc_demosaic_vng6_diff #(
parameter DATA = 8
) (
input wire clk,
input wire clk_en,
input wire [3:0] st,
// from _sum
input wire [DATA+3:0] sum_red,
input wire [DATA+3:0] sum_green,
input wire [DATA+3:0] sum_blue,
input wire [ 3:0] sum_cnt,
// output
output reg... | 7.47206 |
module dlsc_demosaic_vng6_grad_slice #(
parameter DATA = 8,
parameter [47:0] INDEX = 0,
parameter [11:0] CLEAR = 0,
parameter [11:0] MULT2 = 0
) (
input wire clk,
input wire clk_en,
input wire [3:0] st,
input wire absdiff_push,
input wire [DATA-1:0] absdiff_in,
... | 7.47206 |
module dlsc_demosaic_vng6_rom #(
parameter DATA = 4,
parameter [(DATA*12)-1:0] ROM = 0
) (
input wire clk,
input wire [3:0] st,
output reg [DATA-1:0] out
);
always @(posedge clk) begin
out <= {DATA{1'bx}};
case (st)
0: out <= ROM[(DATA*11)+:DATA];
1: out... | 7.47206 |
module dlsc_demosaic_vng6_shiftreg #(
parameter DATA = 8,
parameter [47:0] INDEX = {48{1'b0}}
) (
input wire clk,
input wire clk_en,
input wire [3:0] st,
input wire push,
input wire [DATA-1:0] in,
ou... | 7.47206 |
module dlsc_demosaic_vng6_sum_slice #(
parameter DATA = 8,
parameter [47:0] INDEX_RED = 0,
parameter [47:0] INDEX_GREEN = 0,
parameter [47:0] INDEX_BLUE = 0
) (
input wire clk,
input wire clk_en,
input wire [3:0] st,
input wire red_push,
input wire [DATA... | 7.47206 |
module dlsc_demosaic_vng6_sum_slice_comp #(
parameter DATA = 8,
parameter [47:0] INDEX = 0
) (
input wire clk,
input wire clk_en,
input wire [3:0] st,
input wire px_push,
input wire [DATA : 0] px,
input wire sum_rst,
input wire grad_comp,
output reg [DATA+... | 7.47206 |
module dlsc_divu_hybrid #(
parameter CYCLES = 1, // cycles allowed per division (>= 2; < QB)
parameter NB = 8, // bits for numerator/dividend
parameter DB = NB, // bits for denominator/divisor
parameter QB = NB, // bits for quotient
parameter QSKIP = 0 // MS... | 6.540652 |
module dlsc_dma_cmdsplit #(
parameter ADDR = 30,
parameter ILEN = 30, // bits for input command length (must be >= OLEN)
parameter OLEN = 4 // bits for output command length
) (
// system
input wire clk,
input wire rst,
// command input
output wire in_ready,
input wi... | 7.554939 |
module dlsc_dma_read #(
parameter DATA = 32,
parameter ADDR = 32,
parameter LEN = 4,
parameter LSB = 2,
parameter BUFA = 9, // size of buffer is 2**BUFA words
parameter MOT = 16,
parameter TRIG = 8 // 1-16
) (
// System
input wire clk,
input wire rst,
// Control/stat... | 8.219721 |
module into a wire (use for simplifying parameterized
// async crossings).
module dlsc_domaincross #(
parameter BYPASS = 0,
parameter DATA = 32,
`ifndef ICARUS
// Icarus crashes with explicit parameter size; Verilator fails without it.
parameter [DATA-1:0] RESET = {... | 7.399067 |
module into a wire (use for simplifying parameterized
// async crossings).
module dlsc_domaincross_pulse #(
parameter BYPASS = 0,
parameter DEPTH = 1 // number of pulses that can be buffered internally
) (
// source domain
input wire in_clk,
input wire ... | 7.399067 |
module into a wire (use for simplifying parameterized
// async crossings).
module dlsc_domaincross_rvh #(
parameter BYPASS = 0,
parameter DATA = 32,
parameter DEPTH = 2, // depth of synchronizers on handshake signals... | 7.399067 |
module dlsc_domaincross_rvh_test #(
parameter DATA = 32,
parameter RESET = {DATA{1'b0}}
) (
input wire rst,
// source domain
input wire in_clk,
output wire in_ready,
input wire in_valid,
input wire [DATA-1:0] in_data,
// consumer domain
input wire out_... | 7.524871 |
module dlsc_domaincross_slice #(
parameter RESET = 1'b0
) (
// input
input wire in_clk,
input wire in_rst,
input wire in_en,
input wire in_data,
// output
input wire out_clk,
input wire out_rst,
input wire out_en,
output wire out_data
);
//(* IOB="FALSE", SHIFT_EXTRACT... | 7.524871 |
module dlsc_fifo_async #(
parameter WR_CYCLES = 1, // max input rate
parameter RD_CYCLES = 1, // max output rate
parameter WR_PIPELINE = 0, // delay from wr_push to wr_data being valid (0 or 1)
parameter RD_PIPELINE = 0, // delay from rd_pop to rd_data being valid (0 or 1)
parameter DATA = 8, /... | 9.133957 |
module dlsc_fifo_async_rvh #(
parameter WR_CYCLES = 1, // max input rate
parameter RD_CYCLES = 1, // max output rate
parameter DATA = 8, // width of data in FIFO
parameter ADDR = 4, // depth of FIFO is 2**ADDR
// use block RAMs (instead of LUTs)
parameter BR... | 9.133957 |
module dlsc_fifo_async_rvho #(
parameter WR_CYCLES = 1, // max input rate
parameter RD_CYCLES = 1, // max output rate
parameter WR_PIPELINE = 0, // delay from wr_push to wr_data being valid (0 or 1)
parameter DATA = 8, // width of data in FIFO
parameter ADDR =... | 9.133957 |
module dlsc_fifo_one #(
parameter DATA = 8, // width of data in FIFO
parameter ALMOST_FULL = 0, // assert almost_full when <= ALMOST_FULL free spaces remain (0 makes it equivalent to full)
parameter ALMOST_EMPTY = 0, // assert almost_empty when <= ALMOST_EMPTY valid entries remain (0 makes it equi... | 8.248064 |
module dlsc_fifo_rvh (
// system
clk,
rst,
// input
wr_ready,
wr_valid,
wr_data,
wr_almost_full,
// output
rd_ready,
rd_valid,
rd_data,
rd_almost_empty
);
`include "dlsc_clog2.vh"
`include "dlsc_synthesis.vh"
// ** Parameters **
// one of these must be set:
paramet... | 7.508754 |
module dlsc_fifo_rvho (
// system
clk,
rst,
// input
wr_push,
wr_data,
wr_full,
wr_almost_full,
wr_free,
// output
rd_ready,
rd_valid,
rd_data,
rd_almost_empty
);
`include "dlsc_clog2.vh"
`include "dlsc_synthesis.vh"
// ** Parameters **
// one of these must be ... | 7.508754 |
module dlsc_fifo_shiftreg #(
parameter DATA = 8, // width of data in FIFO
parameter DEPTH = 0, // depth of FIFO
parameter ALMOST_FULL = 0, // assert almost_full when <= ALMOST_FULL free spaces remain (0 makes it equivalent to full)
parameter ALMOST_EMPTY = 0, // assert almost_empty when <= AL... | 8.700267 |
module dlsc_fifo_two #(
parameter DATA = 8, // width of data in FIFO
parameter ALMOST_FULL = 0, // assert almost_full when <= ALMOST_FULL free spaces remain (0 makes it equivalent to full)
parameter ALMOST_EMPTY = 0, // assert almost_empty when <= ALMOST_EMPTY valid entries remain (0 ma... | 8.402973 |
module dlsc_grayscale_core #(
parameter BITS = 8, // bits per pixel
parameter CBITS = 4 // bits for coefficients
) (
// system
input wire clk,
input wire rst,
// configuration
input wire [CBITS-1:0] cfg_mult_r,
input wire [CBITS-1:0] cfg_mult_g,
input wire [CBITS-1:0] cfg_mult_b... | 7.067126 |
module dlsc_lutmult #(
parameter AB = 4, // bits for A input
parameter BB = 4, // bits for B input
parameter OB = 4, // bits for output
parameter SCALE = (OB < (AB+BB)), // scale output to use full range
paramete... | 7.104675 |
module dlsc_madd_cascade #(
parameter DEVICE = "GENERIC",
parameter SLICES = 1, // number of slices to cascade
parameter REVERSE = 0, // reverse order of cascade (start at N-1 instead of 0)
parameter SIGNED = 0, // treat inputs as signed values
paramet... | 6.917912 |
module dlsc_median_3x3_slice #(
parameter BITS = 8 // bits for data
) (
// system
input wire clk,
// input (unsorted)
input wire [BITS-1:0] c0_data0,
input wire [BITS-1:0] c0_data1,
input wire [BITS-1:0] c0_data2,
// output (s... | 7.651531 |
module dlsc_mult #(
parameter DEVICE = "GENERIC",
parameter SIGNED = 0, // set for signed multiplication
parameter DATA0 = 1, // total bits for first operand (including sign bit and fractional bits)
parameter DATA1 = 1, // total bits for second operand ("")... | 7.616104 |
module dlsc_multu #(
parameter DATA0 = 17, // width of first operand
parameter DATA1 = 17, // width of second operand
parameter OUT = (DATA0 + DATA1), // width of output
parameter PIPELINE = 4 // pipeline delay (recommend 3-4 for Xilinx DSP48 block... | 8.94811 |
module dlsc_mult_generic #(
parameter SIGNED = 0, // set for signed multiplication
parameter DATA0 = 1, // width of first operand (should typically be >= DATA1)
parameter DATA1 = 1, // width of second operand
parameter OUT = 1, // width of output
parameter PIPELINE = 4 // pipeline... | 8.066136 |
module dlsc_pcie_cplbytes (
input wire [ 9:0] len,
input wire [ 3:0] be_first,
input wire [ 3:0] be_last,
input wire type_mem,
output reg [11:0] bytes_remaining,
output reg [ 1:0] byte_offset
);
// calculate bytes remaining
// (why does PCIe make this so complicated??)
reg [... | 6.583073 |
module dlsc_pcie_s6_inbound_dispatch #(
parameter TOKN = 4
) (
// System
input wire clk,
input wire rst,
// TLP header input
output wire tlp_h_ready,
input wire tlp_h_valid,
input wire tlp_h_write,
// TLP read headers
input wire rd_h_ready,
output wire ... | 8.257643 |
module dlsc_pcie_s6_inbound_read_rcb #(
parameter MAX_SIZE = 4096, // max read completion size
parameter REGISTER = 1
) (
// System
input wire clk,
input wire rst,
// TLP header input
output wire tlp_h_ready,
input wire tlp_h_valid,
input wire tlp_h_mem,
... | 8.257643 |
module dlsc_pcie_s6_inbound_trans #(
parameter ADDR = 32,
parameter [ADDR-1:0] TRANS_BAR0_MASK = {ADDR{1'b1}},
parameter [ADDR-1:0] TRANS_BAR0_BASE = {ADDR{1'b0}},
parameter [ADDR-1:0] TRANS_BAR1_MASK = {ADDR{1'b1}},
parameter [ADDR-1:0] TRANS_BAR1_BASE = {ADDR{1'b0}},
para... | 8.257643 |
module dlsc_pcie_s6_outbound_write_cmdmerge #(
parameter ADDR = 32,
parameter LEN = 4,
parameter MAX_SIZE = 128 // maximum write payload size
) (
// system
input wire clk,
input wire rst,
// command stream input
output wire cmd_ready,
input wire cmd_... | 8.257643 |
module dlsc_pcie_s6_outbound_write_cmdsplit #(
parameter ADDR = 32,
parameter LEN = 4
) (
// system
input wire clk,
input wire rst,
// AXI write command input
output wire axi_aw_ready,
input wire axi_aw_valid,
input wire [ADDR-1:2] axi_aw_addr,
input wi... | 8.257643 |
module dlsc_pcie_s6_rstcontrol (
// PCIe side
input wire pcie_rst, // PCIe reset from pcie_clk domain
// AXI/bridge side
input wire clk, // clock for AXI bus and bridge logic
input wire rst, // reset for AXI bus
output wire cross_rst, // reset for domain crossing logic
output wire bri... | 8.257643 |
module dlsc_pcie_s6_tlpfifo #(
parameter DATA = 8, // width of data in FIFO
parameter ADDR = 4 // depth of FIFO is 2**ADDR
) (
// input
input wire wr_clk,
input wire wr_rst,
output wire wr_ready,
input wire wr_valid,
input wire ... | 8.257643 |
module dlsc_pipedelay #(
parameter DATA = 32,
parameter DELAY = 1,
parameter FANOUT = 0 // Set if output of module drives a high fanout net.
) (
input wire clk,
input wire [DATA-1:0] in_data,
output wire [DATA-1:0] out_data
);
`include "dlsc_synthes... | 6.698811 |
module dlsc_pipedelay_clken #(
parameter DATA = 32,
parameter DELAY = 1
) (
input wire clk,
input wire clk_en,
input wire [DATA-1:0] in_data,
output wire [DATA-1:0] out_data
);
generate
integer i;
genvar j;
if (DELAY == 0) begin : GEN_DELAY0
assign out_data = in_data;
... | 6.698811 |
module supports three different reset modes, selected by FAST_RESET.
// In all modes, 'out_data' is always driven to RESET 1 cycle after 'rst' is
// asserted. The modes differ in their requirements regarding the 'rst' and
// 'in_data' input signals.
//
// FAST_RESET = 1:
// Module can accept a 'rst' pulse that is ... | 7.165454 |
module dlsc_pipedelay_rst_clken_slice #(
parameter DELAY = 1, // delay from input to output (>= 1)
parameter DATA = 1, // width of delayed data
parameter RESET = {DATA{1'b0}} // reset value for data
) (
input wire clk,
input wire ... | 6.698811 |
module dlsc_pipedelay_valid #(
parameter DATA = 32,
parameter DELAY = 1
) (
input wire clk,
input wire rst,
input wire in_valid,
input wire [DATA-1:0] in_data,
output wire out_valid,
output wire [DATA-1:0] out_data
);
dlsc_pipedelay_rst #(
.DATA (1),
... | 6.698811 |
module dlsc_pipereg #(
parameter DATA = 32,
parameter PIPELINE = 0
) (
input wire clk,
input wire [DATA-1:0] in_data,
output wire [DATA-1:0] out_data
);
`include "dlsc_synthesis.vh"
generate
integer i;
genvar j;
if(PIPELINE == 0) begin:GEN_DELAY0
... | 7.147115 |
module dlsc_ram_dp #(
parameter DATA = 32,
parameter ADDR = 9,
parameter DEPTH = (2**ADDR),
parameter PIPELINE_WR = 0, // 0 or more
parameter PIPELINE_WR_DATA = PIPELINE_WR, // 0 or more
parameter PIPELINE_RD = 1, // 1 or more (minimu... | 8.531306 |
module dlsc_ram_dp_slice #(
parameter DATA = 72,
parameter ADDR = 9,
parameter DEPTH = (2**ADDR),
parameter PIPELINE = 0, // enable additional pipeline register on output
parameter WARNINGS = 1
) (
// write port
input wire write_clk,
... | 9.150369 |
modules can only accept data at a slower rate (and don't provide their own rate
// limiting function).
module dlsc_rate_limiter #(
parameter CYCLES = 1, // limit data acceptance rate to 1 value every CYCLES clock cycles
parameter UNIFORM = 0 // force each accepted value to be an exact multiple of C... | 7.507805 |
module dlsc_rowbuffer #(
parameter ROW_WIDTH = 537, // width of each row
parameter BUF_DEPTH = ROW_WIDTH, // depth of buffer (BUF_DEPTH >= ROW_WIDTH)
parameter IN_ROWS = 1, // number of rows to input in parallel
parameter OUT_ROWS = 1, // ... | 8.482228 |
module dlsc_rstsync #(
parameter DOMAINS = 1,
parameter DEPTH = 8
) (
input wire rst_in, // asynchronous reset input
input wire [DOMAINS-1:0] clk, // clocks to synchronize resets to
output wire [DOMAINS-1:0] rst_out // synchronous reset outputs
);
generate
genvar j;
... | 8.891523 |
module dlsc_rstsync_slice (
clk, // clock (which the reset will be synchronized to)
rst_in, // asynchronous reset input
rst_out // synchronous reset output
);
/* verilator lint_off SYNCASYNCNET */
`include "dlsc_synthesis.vh"
parameter DEPTH = 8; // TODO
input clk;
input rst_in;
ou... | 8.550573 |
module dlsc_rvh_decoupler #(
parameter WIDTH = 32
) (
// system
input wire clk,
input wire rst,
// source
input wire in_en, // clk_en for source
output reg in_ready,
input wire in_valid,
input wire [WIDTH-1:0] in_data,
// sink
inp... | 8.102431 |
module for CPU ALU.
// TODO: work-in-progress
module dlsc_shift32 (
input wire clk,
input wire left, // shift left (instead of right)
input wire sign, // sign-extend (instead of zero-filling)
input wire [4:0] shift, // amount to shift by
... | 7.54849 |
module dlsc_shiftreg #(
parameter DATA = 32,
parameter ADDR = 4,
parameter DEPTH = (2**ADDR),
parameter WARNINGS = 1
) (
input wire clk, // writes synchronous to this clock
input wire write_en, // write enable
input wire ... | 9.54796 |
module.pl
// using Perl Algorithm::Networksort
// algorithm: batcher
// inputs: 2
// levels: 1
// comparators: 1
module dlsc_sortnet_2 #(
parameter META = 1, // width of bypassed metadata
parameter DATA = 16, // width of data for each element
parameter ID = 1, ... | 6.801341 |
module dlsc_sp605_clocks #(
parameter IN_DIV = 5,
parameter IN_MULT = 24,
parameter CLK_DIV = 12,
parameter PX_DIV = 40
) (
input wire clk200_in,
input wire rst_in,
output wire clk, // 80 MHz
output wire rst,
output wire px_clk, // 24 MHz
output wire px_rst
);
wire locke... | 6.893849 |
modules required to process
// multiple disparities levels per pass. Data for the right image is cascaded
// between pipe instances (with each pipe adding a 1 cycle delay) so that each
// pipe works on a different disparity level.
module dlsc_stereobm_multipipe #(
parameter MULT_D = 8,
parameter MULT_R ... | 8.19898 |
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