code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module madd_261 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_261 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.731789 |
module madd_core_261 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.90046 |
module madd_262 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_262 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.338072 |
module madd_core_262 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.088017 |
module madd_263 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_263 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.838793 |
module madd_core_263 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.967139 |
module madd_264 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_264 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.437236 |
module madd_core_264 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.101828 |
module madd_265 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_265 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.131224 |
module madd_core_265 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.056969 |
module madd_266 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_266 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.096067 |
module madd_core_266 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.989851 |
module madd_267 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_267 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.853058 |
module madd_core_267 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.024866 |
module madd_268 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_268 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.983461 |
module madd_core_268 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.109606 |
module madd_269 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_269 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.264086 |
module madd_core_269 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.979742 |
module madd_270 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_270 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.380725 |
module madd_core_270 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.993867 |
module madd_271 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_271 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.817381 |
module madd_core_271 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.967533 |
module madd_272 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_272 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.379694 |
module madd_core_272 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.137947 |
module madd_273 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_273 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.963483 |
module madd_core_273 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.078456 |
module madd_274 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_274 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.039376 |
module madd_core_274 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.372801 |
module madd_275 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_275 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.875474 |
module madd_core_275 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.890205 |
module madd_276 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_276 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.271898 |
module madd_core_276 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.972058 |
module madd_277 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_277 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.949507 |
module madd_core_277 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.068641 |
module madd_278 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_278 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.130527 |
module madd_core_278 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.926265 |
module madd_279 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_279 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.524158 |
module madd_core_279 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.836324 |
module madd_280 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_280 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.627876 |
module madd_core_280 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.740434 |
module madd_281 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_281 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.6003 |
module madd_core_281 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.80309 |
module madd_282 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_282 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.294069 |
module madd_core_282 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.094742 |
module madd_283 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_283 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.78799 |
module madd_core_283 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.937495 |
module madd_284 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_284 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.988677 |
module madd_core_284 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 7.284896 |
module madd_285 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_285 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.010583 |
module madd_core_285 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.828269 |
module madd_286 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_286 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 7.028405 |
module madd_core_286 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.998106 |
module madd_287 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
madd_core_287 madd (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c),
.d(d)
);
endmodule
| 6.799559 |
module madd_core_287 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
input [16-1:0] c,
output [16-1:0] d
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
reg signed [16-1:0] _c;
wire signed [16-1:0] _mul;
wire signed [16-1:0] _madd;
reg signed [16-1:0] _pipe_madd0... | 6.993844 |
module multiplier_3 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
multiplier_core_3 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 7.677432 |
module multiplier_core_3 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
reg signed [32-1:0] _a;
reg signed [16-1:0] _b;
wire signed [48-1:0] _mul;
reg signed [48-1:0] _pipe_mul0;
reg signed [48-1:0] _pipe_mul1;
assign _mul = _a * _b;
assign c =... | 6.701364 |
module multiplier_4 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
multiplier_core_4 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.802131 |
module multiplier_core_4 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
reg signed [32-1:0] _a;
reg signed [16-1:0] _b;
wire signed [48-1:0] _mul;
reg signed [48-1:0] _pipe_mul0;
reg signed [48-1:0] _pipe_mul1;
assign _mul = _a * _b;
assign c =... | 6.701364 |
module multiplier_5 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
multiplier_core_5 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.783128 |
module multiplier_core_5 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
reg signed [32-1:0] _a;
reg signed [16-1:0] _b;
wire signed [48-1:0] _mul;
reg signed [48-1:0] _pipe_mul0;
reg signed [48-1:0] _pipe_mul1;
assign _mul = _a * _b;
assign c =... | 6.701364 |
module multiplier_6 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
multiplier_core_6 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.982267 |
module multiplier_core_6 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
reg signed [32-1:0] _a;
reg signed [16-1:0] _b;
wire signed [48-1:0] _mul;
reg signed [48-1:0] _pipe_mul0;
reg signed [48-1:0] _pipe_mul1;
assign _mul = _a * _b;
assign c =... | 6.701364 |
module multiplier_7 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
multiplier_core_7 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.798586 |
module multiplier_core_7 (
input CLK,
input update,
input [32-1:0] a,
input [16-1:0] b,
output [48-1:0] c
);
reg signed [32-1:0] _a;
reg signed [16-1:0] _b;
wire signed [48-1:0] _mul;
reg signed [48-1:0] _pipe_mul0;
reg signed [48-1:0] _pipe_mul1;
assign _mul = _a * _b;
assign c =... | 6.701364 |
module multiplier_8 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_8 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.729442 |
module multiplier_core_8 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
re... | 6.701364 |
module multiplier_9 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_9 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.970171 |
module multiplier_core_9 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
re... | 6.701364 |
module multiplier_10 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_10 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.669625 |
module multiplier_core_10 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_11 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_11 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.805095 |
module multiplier_core_11 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_12 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
output [16-1:0] c
);
multiplier_core_12 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 7.358334 |
module multiplier_core_12 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
output [16-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
wire signed [16-1:0] _mul;
reg signed [16-1:0] _pipe_mul0;
reg signed [16-1:0] _pipe_mul1;
reg signed [16-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_13 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
output [16-1:0] c
);
multiplier_core_13 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 7.163869 |
module multiplier_core_13 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
output [16-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
wire signed [16-1:0] _mul;
reg signed [16-1:0] _pipe_mul0;
reg signed [16-1:0] _pipe_mul1;
reg signed [16-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_14 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
output [16-1:0] c
);
multiplier_core_14 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 7.102243 |
module multiplier_core_14 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
output [16-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
wire signed [16-1:0] _mul;
reg signed [16-1:0] _pipe_mul0;
reg signed [16-1:0] _pipe_mul1;
reg signed [16-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_15 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
output [16-1:0] c
);
multiplier_core_15 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.984851 |
module multiplier_core_15 (
input CLK,
input update,
input [8-1:0] a,
input [8-1:0] b,
output [16-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 8-1:0] _b;
wire signed [16-1:0] _mul;
reg signed [16-1:0] _pipe_mul0;
reg signed [16-1:0] _pipe_mul1;
reg signed [16-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_16 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_16 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 7.195801 |
module multiplier_core_16 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_core_17 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_core_18 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_19 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_19 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.691469 |
module multiplier_core_19 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_20 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_20 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 7.337133 |
module multiplier_core_20 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_21 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_21 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 7.140691 |
module multiplier_core_21 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_22 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_22 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.740915 |
module multiplier_core_22 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module multiplier_23 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
multiplier_core_23 mult (
.CLK(CLK),
.update(update),
.a(a),
.b(b),
.c(c)
);
endmodule
| 6.897203 |
module multiplier_core_23 (
input CLK,
input update,
input [8-1:0] a,
input [5-1:0] b,
output [13-1:0] c
);
reg signed [ 8-1:0] _a;
reg signed [ 5-1:0] _b;
wire signed [13-1:0] _mul;
reg signed [13-1:0] _pipe_mul0;
reg signed [13-1:0] _pipe_mul1;
reg signed [13-1:0] _pipe_mul2;
r... | 6.701364 |
module sub__saxi_register_fsm #(
parameter _saxi_maskwidth = 4,
parameter _saxi_shift = 2,
parameter _saxi_mask = {_saxi_maskwidth{1'd1}}
) (
input CLK,
input RST,
output reg [32-1:0] _saxi_register_fsm,
input i__tmp_2,
input i__tmp_1,
input [32-1:0] i__tmp_0,
input i_saxi_rready... | 7.490583 |
module DFF (
In,
enable,
reset,
Out
);
input In, enable, reset;
output reg Out;
always @(posedge enable or posedge reset) begin
if (reset) Out = 1'b0;
else Out = In;
end
endmodule
| 7.462457 |
module dlatch1 (
input d, // 1-bit input pin for data
input en, // 1-bit input pin for enabling the latch
input rstn, // 1-bit input pin for active-low reset
output reg q // 1-bit output pin for data output
);
// This always block is "always" triggered whenever en/rstn/d c... | 8.362533 |
module tb_latch;
// Declare variables that can be used to drive values to the design
reg d;
reg en;
reg rstn;
reg [2:0] delay;
reg [1:0] delay2;
integer i;
// Instantiate design and connect design ports with TB signals
dlatch1 dl0 (
.d(d),
.en(en),
.rstn(rstn),
.q(q)
);
/... | 7.348239 |
module dlatch2 (
input d, // 1-bit input pin for data
input en, // 1-bit input pin for enabling the latch
input rstn, // 1-bit input pin for active-low reset
output reg q // 1-bit output pin for data output
);
// This always block is "always" triggered whenever en/rstn/d c... | 8.735843 |
module tb_latch ();
// Declare variables that can be used to drive values to the design
reg d;
reg en;
reg rstn;
reg [2:0] delay;
reg [1:0] delay2;
integer i;
// Instantiate design and connect design ports with TB signals
dlatch2 dl0 (
.d (d ),
... | 7.161421 |
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