code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_13 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_12 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_11 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_10 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_9 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_8 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_7 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_6 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_5 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_4 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_3 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_2 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_FILE_WIDTH32_LENGTH5_1 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7088;
wire net7090;
wire net7092;
wire net7093;
wire net7096;
wire net7099;
assign net7088 = EN;
assign net7090 = CLK;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH5_0 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7070;
wire net7072;
wire net7074;
wire net7075;
wire net7078;
wire net7081;
assign net7070 = EN;
assign net7072 = CLK;
assign... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_FFD_0 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7016;
wire net7018;
wire net7020;
wire net7021;
wire net7024;
wire net7027;
assign net7016 = EN;
assign net7018 = CLK;
assign ENCLK = net7020;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_12 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assi... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_11 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assi... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_10 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assi... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_9 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assig... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_8 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assig... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_7 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assig... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_6 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assig... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_5 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assig... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_4 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assig... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH5_2 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7070;
wire net7072;
wire net7074;
wire net7075;
wire net7078;
wire net7081;
assign net7070 = EN;
assign net7072 = CLK;
assign... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_3 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assig... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_2 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assig... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH5_1 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7070;
wire net7072;
wire net7074;
wire net7075;
wire net7078;
wire net7081;
assign net7070 = EN;
assign net7072 = CLK;
assign... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_FFD_2 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7016;
wire net7018;
wire net7020;
wire net7021;
wire net7024;
wire net7027;
assign net7016 = EN;
assign net7018 = CLK;
assign ENCLK = net7020;
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_REGISTER_GENERIC_WIDTH32_1 (
CLK,
EN,
ENCLK,
TE
);
input CLK;
input EN;
output ENCLK;
input TE;
// Internal wires
wire net7052;
wire net7054;
wire net7056;
wire net7057;
wire net7060;
wire net7063;
assign net7052 = EN;
assign net7054 = CLK;
assig... | 6.575704 |
module dly (
input clk,
input i,
output o
);
parameter ticks = 3'd5;
localparam width = $clog2(ticks + 1);
reg [width-1:0] counter = ticks;
always @(posedge clk) begin
case (i)
1'b1: if (|counter) counter <= counter - 1'b1;
1'b0: counter <= ticks;
endcase
end
assign o =... | 7.155484 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module dly30ns (
input clk,
input reset,
input in,
output p
);
reg [1-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 1'b1;
if (in) r <= 1;
end
end
assign p = r == 1;
endmodule
| 7.309 |
module dly45ns (
input clk,
input reset,
input in,
output p
);
reg [2-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 2'b1;
if (in) r <= 1;
end
end
assign p = r == 2;
endmodule
| 7.246164 |
module dly50ns (
input clk,
input reset,
input in,
output p
);
reg [2-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 2'b1;
if (in) r <= 1;
end
end
assign p = r == 2;
endmodule
| 6.904944 |
module dly65ns (
input clk,
input reset,
input in,
output p
);
reg [2-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 2'b1;
if (in) r <= 1;
end
end
assign p = r == 3;
endmodule
| 7.288999 |
module dly70ns (
input clk,
input reset,
input in,
output p
);
reg [2-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 2'b1;
if (in) r <= 1;
end
end
assign p = r == 3;
endmodule
| 7.139772 |
module dly75ns (
input clk,
input reset,
input in,
output p
);
reg [2-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 2'b1;
if (in) r <= 1;
end
end
assign p = r == 3;
endmodule
| 7.022475 |
module dly90ns (
input clk,
input reset,
input in,
output p
);
reg [3-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 3'b1;
if (in) r <= 1;
end
end
assign p = r == 4;
endmodule
| 7.019753 |
module dly100ns (
input clk,
input reset,
input in,
output p
);
reg [3-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 3'b1;
if (in) r <= 1;
end
end
assign p = r == 5;
endmodule
| 6.748313 |
module dly115ns (
input clk,
input reset,
input in,
output p
);
reg [3-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 3'b1;
if (in) r <= 1;
end
end
assign p = r == 5;
endmodule
| 6.911963 |
module dly140ns (
input clk,
input reset,
input in,
output p
);
reg [3-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 3'b1;
if (in) r <= 1;
end
end
assign p = r == 7;
endmodule
| 6.71632 |
module dly150ns (
input clk,
input reset,
input in,
output p
);
reg [3-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 3'b1;
if (in) r <= 1;
end
end
assign p = r == 7;
endmodule
| 6.6159 |
module dly165ns (
input clk,
input reset,
input in,
output p
);
reg [4-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 4'b1;
if (in) r <= 1;
end
end
assign p = r == 8;
endmodule
| 6.861537 |
module dly190ns (
input clk,
input reset,
input in,
output p
);
reg [4-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 4'b1;
if (in) r <= 1;
end
end
assign p = r == 9;
endmodule
| 7.039198 |
module dly200ns (
input clk,
input reset,
input in,
output p
);
reg [4-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 4'b1;
if (in) r <= 1;
end
end
assign p = r == 10;
endmodule
| 6.621048 |
module dly215ns (
input clk,
input reset,
input in,
output p
);
reg [4-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 4'b1;
if (in) r <= 1;
end
end
assign p = r == 10;
endmodule
| 6.764559 |
module dly300ns (
input clk,
input reset,
input in,
output p
);
reg [4-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 4'b1;
if (in) r <= 1;
end
end
assign p = r == 15;
endmodule
| 6.78988 |
module dly335ns (
input clk,
input reset,
input in,
output p
);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 5'b1;
if (in) r <= 1;
end
end
assign p = r == 16;
endmodule
| 7.09374 |
module dly400ns (
input clk,
input reset,
input in,
output p
);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 5'b1;
if (in) r <= 1;
end
end
assign p = r == 20;
endmodule
| 6.922458 |
module dly450ns (
input clk,
input reset,
input in,
output p
);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 5'b1;
if (in) r <= 1;
end
end
assign p = r == 22;
endmodule
| 6.94033 |
module ldly500ns (
input clk,
input reset,
input in,
output p,
output reg l
);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) begin
r <= 0;
l <= 0;
end else begin
if (r) r <= r + 5'b1;
if (in) begin
r <= 1;
l <= 1;
end... | 6.554502 |
module dly500ns (
input clk,
input reset,
input in,
output p
);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 5'b1;
if (in) r <= 1;
end
end
assign p = r == 25;
endmodule
| 6.70083 |
module dly550ns (
input clk,
input reset,
input in,
output p
);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 5'b1;
if (in) r <= 1;
end
end
assign p = r == 27;
endmodule
| 7.010619 |
module dly750ns (
input clk,
input reset,
input in,
output p
);
reg [6-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 6'b1;
if (in) r <= 1;
end
end
assign p = r == 37;
endmodule
| 7.104098 |
module dly800ns (
input clk,
input reset,
input in,
output p
);
reg [6-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 6'b1;
if (in) r <= 1;
end
end
assign p = r == 40;
endmodule
| 6.528214 |
module dly1us (
input clk,
input reset,
input in,
output p
);
reg [6-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 6'b1;
if (in) r <= 1;
end
end
assign p = r == 50;
endmodule
| 6.605677 |
module ldly1_5us (
input clk,
input reset,
input in,
output p,
output reg l
);
reg [7-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) begin
r <= 0;
l <= 0;
end else begin
if (r) r <= r + 7'b1;
if (in) begin
r <= 1;
l <= 1;
end... | 6.543494 |
module dly2_8us (
input clk,
input reset,
input in,
output p
);
reg [8-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 8'b1;
if (in) r <= 1;
end
end
assign p = r == 140;
endmodule
| 6.918348 |
module ldly66us (
input clk,
input reset,
input in,
output p,
output reg l
);
reg [12-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) begin
r <= 0;
l <= 0;
end else begin
if (r) r <= r + 12'b1;
if (in) begin
r <= 1;
l <= 1;
en... | 6.98301 |
module dly2_1ms (
input clk,
input reset,
input in,
output p
);
reg [17-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 17'b1;
if (in) r <= 1;
end
end
assign p = r == 105000;
endmodule
| 6.921157 |
module dly2_5ms (
input clk,
input reset,
input in,
output p
);
reg [17-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 17'b1;
if (in) r <= 1;
end
end
assign p = r == 125000;
endmodule
| 6.980789 |
module dly5ms (
input clk,
input reset,
input in,
output p
);
reg [18-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) r <= 0;
else begin
if (r) r <= r + 18'b1;
if (in) r <= 1;
end
end
assign p = r == 250000;
endmodule
| 6.884726 |
module ldly5ms (
input clk,
input reset,
input in,
output p,
output reg l
);
reg [18-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) begin
r <= 0;
l <= 0;
end else begin
if (r) r <= r + 18'b1;
if (in) begin
r <= 1;
l <= 1;
end... | 6.555289 |
module ldly40ms (
input clk,
input reset,
input in,
output p,
output reg l
);
reg [21-1:0] r;
always @(posedge clk or posedge reset) begin
if (reset) begin
r <= 0;
l <= 0;
end else begin
if (r) r <= r + 21'b1;
if (in) begin
r <= 1;
l <= 1;
en... | 6.982549 |
module DLY_NR_ASGN (
clk,
rst,
port_a,
port_b
);
input clk;
input rst;
input port_a;
output port_b;
reg port_b;
always @(posedge clk or negedge rst)
if (!rst) port_b <= #1 1'b0;
else port_b <= #1 port_a;
endmodule
| 6.745599 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module DMA8 (
input wire clk,
input wire reset_n,
input wire [11:0] port,
input wire [7:0] iodin,
input wire iowrin,
output reg iowrout,
output reg [23:0] dma1_addr,
input wire [7:0] dma1_din,
input wire dma1_rdin,
output reg dma1_rdout,
output wire [7:0] dma1_dout,
in... | 6.62488 |
module DMAC_fifo (
clk,
reset_n,
rd_en,
wr_en,
din0,
din1,
din2,
dout0,
dout1,
dout2,
data_count,
full,
empty,
wr_ack,
wr_err,
rd_ack,
rd_err
);
input clk, reset_n, rd_en, wr_en; // clock, reset, read, write enable
input [31:0] din0, din1, din2; ... | 7.179695 |
module _dff_3_r (
clk,
reset_n,
d,
q
); // 3bits resettable flip flop
input clk, reset_n; // clock, reset
input [2:0] d;
output reg [2:0] q;
always @ (posedge clk or negedge reset_n) // whenever clk is rising edge or reset is falling edge
begin
if (reset_n == 0) q <= 1'b0;
else q <... | 7.635159 |
module _dff_4_r (
clk,
reset_n,
d,
q
); // 4bit resettable flip flop
input clk, reset_n; // clock, reset
input [3:0] d;
output reg [3:0] q;
always @ (posedge clk or negedge reset_n) // whenever clk is rising edge or reset is falling edge
begin
if (reset_n == 0) q <= 1'b0;
else q <=... | 7.354482 |
module _DFF31 (
clk,
reset_n,
d,
q
); // resettable 32bit flip flop
input clk, reset_n; // input
input [31:0] d;
output reg [31:0] q; // output reg
always@(posedge clk or negedge reset_n) // whenever clk is rising edge or reset is falling edge
begin
if (reset_n == 0) q <= 32'b0;
el... | 7.769167 |
module fifo_ns (
rd_en,
wr_en,
state,
data_count,
next_state
); // fifo_ns logic
input rd_en, wr_en; // input
input [2:0] state;
input [3:0] data_count; // 8 bits data count
output reg [2:0] next_state;
parameter IDLE = 3'b000; // define IDLE
parameter WRITE = 3'b001; // define WRI... | 8.162289 |
module fifo_cal (
state,
data_count,
head,
tail,
re,
we,
next_data_count,
next_head,
next_tail
); //fifo_cal
input [2:0] state, head, tail; // input
input [3:0] data_count;
output reg re, we; // output reg
output reg [3:0] next_data_count;
output reg [2:0] next_head, nex... | 7.80673 |
module fifo_out (
state,
data_count,
empty,
full,
rd_ack,
rd_err,
wr_ack,
wr_err
); //fifo_out
input [2:0] state; // input
input [3:0] data_count;
output reg empty, full, rd_ack, rd_err, wr_ack, wr_err; // output reg
parameter IDLE = 3'b000; // define
parameter WRITE = 3'b... | 8.52606 |
module register32_8 (
clk,
reset_n,
en,
d_in,
d_out0,
d_out1,
d_out2,
d_out3,
d_out4,
d_out5,
d_out6,
d_out7
); // register32_8
input clk, reset_n; // input
input [7:0] en;
input [31:0] d_in;
output [31:0] d_out0, d_out1, d_out2, d_out3, d_out4, d_out5, d_out6, ... | 6.986702 |
module register32_r_en (
clk,
reset_n,
d_in,
d_out,
en
); // 32bits register reset,enable
input clk, reset_n, en; // input
input [31:0] d_in;
output [31:0] d_out; // output
// instance by using 4 register8_r_en
register8_r_en U0_register_r_en (
.clk(clk),
.reset_n(reset_n),... | 7.531 |
module register8_r_en (
clk,
reset_n,
d_in,
d_out,
en
); // register8_r_en
input clk, reset_n, en; // input
input [7:0] d_in;
output [7:0] d_out; // output
// instance by using 8 _dff_r_en
_dff_r_en U0_dff_r_en (
.clk(clk),
.reset_n(reset_n),
.en(en),
.d(d_in[0]... | 6.93382 |
module _dff_r_en (
clk,
reset_n,
en,
d,
q
); // reset, enable d flip flop
input clk, reset_n, en, d; // input
output reg q; // output
always@(posedge clk or negedge reset_n) begin // whenever clock is rising edge or reset is falling edge
if (~reset_n) q <= 1'b0;
else if (en) q <= d... | 7.589853 |
module write_operation (
Addr,
we,
to_reg
); // write operation
input we; // input
input [2:0] Addr;
output [7:0] to_reg; // output
wire [7:0] write_wire; // wire
// instance by using each modules
_3_to_8_decoder U0_3_to_8_decoder (
.d(Addr),
.q(write_wire)
);
_and2 U1_and2... | 6.871522 |
module _3_to_8_decoder (
d,
q
); //3_to_8_decoder
input [2:0] d; // input
output reg [7:0] q; // output reg
always @(d) begin
case (d)
3'b000: q = 8'b00000001; // one-hot encoding
3'b001: q = 8'b00000010;
3'b010: q = 8'b00000100;
3'b011: q = 8'b00001000;
3'b100: ... | 8.989213 |
module read_operation (
Addr,
Data,
from_reg0,
from_reg1,
from_reg2,
from_reg3,
from_reg4,
from_reg5,
from_reg6,
from_reg7
); // read_operation
input [31:0] from_reg0, from_reg1, from_reg2, from_reg3, from_reg4, from_reg5, from_reg6, from_reg7; // input
input [2:0] Addr;... | 7.921226 |
module _8_to_1_MUX (
a,
b,
c,
d,
e,
f,
g,
h,
sel,
d_out
); // _8_to_1 mux
input [31:0] a, b, c, d, e, f, g, h; // input
input [2:0] sel;
output reg [31:0] d_out; // output reg
always @(sel, a, b, c, d, e, f, g, h) begin
case (sel) // depend on sel
3'b000: ... | 8.105509 |
module mx2_to_ff (
d0,
d1,
s,
y
); //32bits mx
input [31:0] d0, d1; // 32bits input d0,d1
input s; // input
output [31:0] y; // 32bits output
assign y = (s == 1'b0) ? d0 : d1; //if s = 0, y=d0, else, y=d1
endmodule
| 6.841177 |
module DMAC_Top (
Clk,
reset_n,
M_grant,
M_din,
S_sel,
S_wr,
S_address,
S_din,
M_req,
M_wr,
M_address,
M_dout,
S_dout,
Interrupt
);
input Clk, reset_n; // Clock, Active low reset
input M_grant, S_sel, S_wr; // Master Grant,Slave Select, Write/read
input [7... | 7.505911 |
module name - dmac_tsntag_distinguish
// Version: V3.2.0.20210722
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
// judge whether descriptor is descriptor of standard ethernet packet
// or descriptor of tsn packet.
////////... | 7.338673 |
module DmAdConv (
input [15:0] mm_addr, // Memory mapped address
input mm_en, // Memory mapping enable
output [15:0] dm_addr, // Data SRAM address
output dm_en, // Data SRAM enable
output [ 7:0] io_addr, // I/O register address
output io_en // I/O regist... | 7.218765 |
module DMAhandler (
input reset_n,
input clk,
input DMA_begin,
input DMA_end,
input Bus_Request,
output Bus_Grant,
output [2 * `WORD_SIZE : 0] DMA_command,
// Memory communication
output MEMORY_readM,
output MEMORY_writeM,
output [`WORD_SIZE - 1 : 0] MEMORY_address,
... | 7.44394 |
module TransferSplitter_1 ( // @[:@814.2]
output io_xferIn_done, // @[:@817.4]
input [31:0] io_xferIn_length, // @[:@817.4]
input io_xferIn_valid, // @[:@817.4]
input io_xferOut_done, // @[:@817.4]
output [31:0] io_xferOut_length, // @[:@817.4]
output ... | 7.143572 |
module DMATransceiver (
clk,
dma_tx_en,
dma_tx_data,
dma_tx_ack,
dma_rx_en,
dma_rx_data,
dma_rx_ack,
tx_done,
tx_busy,
tx_src_addr,
tx_dst_addr,
tx_op,
tx_addr,
tx_len,
tx_en,
tx_rd,
tx_raddr,
tx_buf_out,
rx_ready,
rx_en,
rx_src_addr,
... | 7.143374 |
module DMATransceiverCore (
clk,
dma_tx_en,
dma_tx_data,
dma_tx_ack,
dma_rx_en,
dma_rx_data,
dma_rx_ack,
tx_done,
tx_busy,
tx_src_addr,
tx_dst_addr,
tx_op,
tx_addr,
tx_len,
tx_en,
tx_rd,
tx_raddr,
tx_buf_out,
rx_ready,
rx_en,
rx_src_add... | 7.143374 |
module DMATransceiverCore_rx(
clk,
dma_rx_en, dma_rx_data, dma_rx_ack,
rx_ready, rx_en, rx_src_addr, rx_dst_addr, rx_op, rx_addr, rx_len, rx_we, rx_buf_waddr, rx_buf_wdata,
rx_state_header_2
);
`include "DMARouter_constants.v"
//////////////////////////////////////////////////////////////////////////////////... | 7.143374 |
module DMATransceiverCore_tx (
clk,
dma_tx_en,
dma_tx_data,
dma_tx_ack,
tx_done,
tx_busy,
tx_src_addr,
tx_dst_addr,
tx_op,
tx_addr,
tx_len,
tx_en,
tx_rd,
tx_raddr,
tx_buf_out
);
`include "DMARouter_constants.v"
///////////////////////////////////////////... | 7.143374 |
module dma_ahb_master (
hclk,
n_hreset,
hready,
hgrant,
hbusreq,
hlock,
ahb_request,
addr_drive,
data_drive
);
//==================
// Port Declarations
//==================
input hclk;
input n_hreset;
input hready;
input hgrant;
output hbusreq;
output hlock;
in... | 8.294089 |
module dma_ahb_slave (
clk,
reset_n,
ahb_slave_addr,
ahb_slave_en,
ahb_slave_wen,
ahb_slave_din,
ahb_slave_ready,
ahb_slave_dout,
ahb_slave_resp
);
input clk;
input reset_n;
input [15:0] ahb_slave_addr;
input ahb_slave_en;
input [1:0] ahb_slave_wen;
input [15:0] ahb_s... | 6.831487 |
module dma_axi32_apb_mux (
clk,
reset,
pclken,
psel,
penable,
pwrite,
paddr,
prdata,
pslverr,
pready,
psel0,
prdata0,
pslverr0,
psel1,
prdata1,
pslverr1,
psel_reg,
prdata_reg,
pslverr_reg
);
input clk;
input reset;
input pclken;
input... | 7.053823 |
module dma_axi64_apb_mux (
clk,
reset,
pclken,
psel,
penable,
pwrite,
paddr,
prdata,
pslverr,
pready,
psel0,
prdata0,
pslverr0,
psel1,
prdata1,
pslverr1,
psel_reg,
prdata_reg,
pslverr_reg
);
input clk;
input reset;
input pclken;
input... | 6.992558 |
module dma_axis_control_if #(
parameter C_s_axis_TDATA_WIDTH = 32,
parameter C_m_axis_TDATA_WIDTH = 32,
parameter C_m_axis_START_COUNT = 32,
parameter C_S_AXIS_RXS_TDATA_WIDTH = 32,
parameter C_M_AXIS_TXC_TDATA_WIDTH = 32,
parameter C_m_axis_txc_START_COUNT = 32,
parameter ENABLE_LEN = 1
) (... | 8.324129 |
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