code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DMux8Way_tb ();
integer file;
reg in = 1'b0;
reg [2:0] sel = 3'b000;
wire a;
wire b;
wire c;
wire d;
wire e;
wire f;
wire g;
wire h;
DMux8Way DMUX8WAY (
.in (in),
.sel(sel),
.a (a),
.b (b),
.c (c),
.d (d),
.e (e),
.f (f),
.g ... | 7.550335 |
module dmux_1_16 #(
parameter width = 1,
parameter width_out = 16
) (
input [3:0] sel0,
input [width-1:0] in0,
input const_va,
output [width_out-1:0] out0
);
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin
assign out0[(i+1)*width-1:i*width] = (sel0 == i) ? in0 : {width{co... | 8.19875 |
module of our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang... | 6.78689 |
module of our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang... | 6.78689 |
module of our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang... | 6.78689 |
module dmux_cell (
output o, // Output
input d1, // Data 1
input d2, // Data 2
input s // Data selection
);
// mux
assign o = s ? d1 : d2;
endmodule
| 7.635071 |
module dmux_fft #(
parameter width = 24
) (
input sel0,
input [width-1:0] in0,
output [width-1:0] out0,
output [width-1:0] out1
);
assign out0 = (sel0) ? 0 : in0;
assign out1 = (sel0) ? in0 : 0;
endmodule
| 8.168368 |
module DMX (
output out1,
output out2,
output out3,
output out4,
input [0:1] sel
);
and AND1 (out1, ~sel[0], ~sel[1]);
and AND1 (out2, ~sel[0], sel[1]);
and AND1 (out3, sel[0], ~sel[1]);
and AND1 (out4, sel[0], sel[1]);
endmodule
| 6.883716 |
module Dmx2to4 (
input [1:0] sel,
input en,
output [3:0] out
);
assign out[3:0] = (en) ? (1 << sel[1:0]) : 4'h0;
endmodule
| 7.954735 |
module Dmx4to16 (
input [3:0] sel,
input en,
output [15:0] out
);
assign out[15:0] = (en) ? (1 << sel[3:0]) : 16'h0000;
endmodule
| 7.558391 |
module dmx_dpram #(
parameter depth = 9,
parameter width = 8
) (
input clk,
input [depth-1:0] a,
input we,
input [width-1:0] di,
output reg [width-1:0] do,
input [depth-1:0] a2,
input we2,
input [width-1:0] di2,
output reg [width-1:0] do2
);
reg [width-1:0] ram[0:(1 << depth)-1];
always @(posedge clk) be... | 7.202689 |
module dmx (
output [3:0] outp,
input inp,
input [1:0] addr
);
reg [3:0] x;
parameter // state identifiers
start = 2'b00, id01 = 2'b01, id10 = 2'b10, id11 = 2'b11;
always @(addr) begin
case (addr)
start: x = 4'b1000;
id01: x = 4'b0100;
id10: x = 4'b0010;
id11: x = 4'b0... | 8.139085 |
module mux (
output [7:0] outp,
input [7:0] i0,
input [7:0] i1,
input [7:0] i2,
input [7:0] i3,
input [1:0] addr
);
reg [7:0] x;
parameter // state identifiers
start = 2'b00, id01 = 2'b01, id10 = 2'b10, id11 = 2'b11;
always @(addr) begin
case (addr)
start: x = i0;
... | 7.812393 |
module dmx_brg (
input wire rst_n,
input wire clk,
output reg baudEn
);
parameter DIVISOR = 4;
reg [7:0] baudCount;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
baudCount <= 0;
baudEn <= 0;
end else begin
if (baudCount == DIVISOR) begin
baudCou... | 6.885456 |
module dmx_dpram #(
parameter depth = 9,
parameter width = 8
) (
input clk,
input [depth-1:0] a,
input we,
input [width-1:0] di,
output reg [width-1:0] do,
input [depth-1:0] a2,
input we2,
input [width-1:0] di2,
output reg [width-1:0] do2
);
reg [width-1:0] ram[0:(1 << depth)-1];
always @(posedge clk) be... | 7.202689 |
module dmx_tb ();
parameter duration = 175000;
reg clk = 0;
always #1 clk = ~clk;
wire dmx_signal;
dmx d0 (
.dmxclk(clk),
.signal(dmx_signal)
);
initial begin
$dumpfile(`DUMPSTR(`VCD_OUTPUT));
$dumpvars(0, dmx_tb);
#(duration) $display("END of simulation");
$finish;
end
endm... | 7.420861 |
module DM_1M (
input clk, //时钟信号
input reset, //复位信号
input [31:0] addr, //32位地址线
input [31:0] data_in, //要写入的数据
input [3:0] mem_op, //数据存储器操作码
output reg [31:0] data_out //读出数据
);
reg [7:0] mem[0:1024*1024-1]; //1MB存储器
initial begin
$readmemh("D:\\verilog\\riscv-cpu\\hello_data.h... | 7.465124 |
module dm_4k (
Addr,
Din,
We,
Clk,
Dout
);
input [31:0] Addr, Din;
input Clk, We;
output [31:0] Dout;
reg [31:0] Ram[1024:0];
assign Dout = Ram[Addr[6:2]];
always @(posedge Clk) begin
if (We) Ram[Addr[6:2]] <= Din;
end
integer i;
initial begin
for (i = 0; i < 32; i = i +... | 7.080037 |
module dm_8k #(
parameter NONE = 2'b00,
parameter WORD = 2'b01,
parameter HALF = 2'b10,
parameter BYTE = 2'b11
) (
input clock,
input reset,
input [ 1:0] EX_MEM_LS_bit,
input EX_MEM_MemWrite,
input EX_MEM_Ext_op,
input [31... | 8.31374 |
module DM_block (
ans_dm,
ans_ex,
DM_data,
mem_en_ex,
mem_rw_ex,
mem_mux_sel_dm,
clk,
reset
);
input [15:0] ans_ex;
input [15:0] DM_data;
input mem_en_ex;
input mem_rw_ex;
input mem_mux_sel_dm;
input clk;
input reset;
output [15:0] ans_dm;
wire [15:0] DM_out;
reg ... | 7.4095 |
module DM_block_tb;
// Inputs
reg [15:0] ans_ex;
reg [15:0] DM_data;
reg mem_en_ex;
reg mem_rw_ex;
reg mem_mux_sel_dm;
reg clk;
reg reset;
// Outputs
wire [15:0] ans_dm;
// Instantiate the Unit Under Test (UUT)
DM_block uut (
.ans_dm(ans_dm),
.ans_ex(ans_ex),
.DM_data(DM_dat... | 7.067377 |
module dm_control (
input [2:0] dop, // deside how many bytes (funct3)
input we, // enable write to memory
input rst, // form rst key
input clk, // for SAVE till next clock
... | 7.524102 |
module DM_extend (
input [2:0] DM_ext,
input [31:0] rdata,
output reg [31:0] DM_ext_out
);
always @(*) begin
case (DM_ext)
3'b000: DM_ext_out <= {24'b0, rdata[7:0]};
3'b001: DM_ext_out <= {{24{rdata[7]}}, rdata[7:0]};
3'b010: DM_ext_out <= {18'b0, rdata[15:0]};
3'b011: DM_ext_o... | 8.538562 |
module dm_reg (
clk,
memout,
memout_reg
); //存储dm输出数据
input clk;
input [31:0] memout;
output reg [31:0] memout_reg;
always @(posedge clk) memout_reg <= memout;
endmodule
| 7.619905 |
module dm_sel (
input clk,
input [31:0] addr,
input wen,
input [31:0] wdata,
input [23:0] kg,
output reg [31:0] rdata,
output [7:0] r1,
output [7:0] r2,
output [7:0] r3,
output [7:0] r4,
output [23:0] lights
);
reg dram_wen, led_wen, dig_wen;
dig mydig (
clk,
... | 7.233671 |
module tb_DM_20090121;
// DM_20090121 Parameters
parameter PERIOD = 10;
// DM_20090121 Inputs
reg clk = 0;
reg MemWrite = 0;
reg reset = 0;
reg [31:0] pc_alu = 0;
reg [31:0] data_rt = 0;
// DM_20090121 Outputs
wire [31:0] data_out;
initial begin
forever #(PERIOD... | 6.639265 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module: DM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DM_TF;
// Inputs
reg [63:0] Address;
reg [63:0] DataWrite;
reg MemRead;
reg MemWrite;
// Outputs
wire [63:0] DataR... | 7.012672 |
module dm_warpper (
output [13:0] dm_addr, // dm interface
output reg [31:0] dm_din,
input [31:0] dm_dout,
output reg [31:0] D,
input [31:0] A,
D_in,
input [1:0] data_len, // 00 - byte, 01 - half, 11 - word
input load_sign
);
wire [1:0] addr_low2 = A[1:0];
assign dm_addr = {A[13:... | 7.933068 |
module dn #(
parameter [ 0:0] area = 1.0
) (
input real pos,
input real neg
);
wire real pos, neg;
/* Not modeled, for LVS purposes only */
endmodule
| 6.590202 |
module dn3 #(
parameter [ 0:0] area = 1.0
) (
input real pos,
input real neg
);
wire real pos, neg;
/* Not modeled, for LVS purposes only */
endmodule
| 6.520175 |
module dnano_interface (
/* Human Interface */
button_n,
dip,
leds,
/* Controller Interface */
haddr, // RW-FIFO- data1
busy, // RW-FIFO- full
wr_enable, // WR-FIFO- write
wr_data, // WR-FIFO- data2
rd_enable, //RO-FIFO- write
rd_data, //RI-FIFO- data
rd_rdy, /... | 7.696143 |
module axi_dna (
input rst_n,
input clk_48,
input avalid,
output aready,
input [2:2] aaddr,
output reg bvalid,
output reg [31:0] bdata
);
wire [56:0] dna;
wire dna_ready;
dnareader dna0 (
.rst(!rst_n),
.clk_48(clk_48),
.dna(dna),
.ready(dna_ready)
);
assi... | 6.540112 |
module DNA_PORTE2 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000
) (
output DOUT,
input CLK,
input DIN,
input READ,
input SHIFT
);
reg [95:0] SIM_DNA_VALUE_reg = SIM_DNA_VALUE;
// include dynamic regist... | 7.484518 |
module dobby_top (
input I_CLK,
input I_A_RESET_L,
input [ 1:0] I_INTR_H,
input I_BUS_RDY,
output O_BUS_EN,
output O_BUS_WEN,
output [ 1:0] O_BUS_SIZE,
output [15:0] O_BUS_ADDR,
inout [31:0] B_BUS_DATA,
output [ 1:0] O_INTR_ACK,
inout ... | 6.859761 |
module dobling_tb ();
reg [ 8:0] sum_one_ten;
reg [ 8:0] sum_hundred_thousand;
wire [10:0] total_sum;
doubling test (
sum_one_ten,
sum_hundred_thousand,
total_sum
);
initial begin
sum_one_ten = 9'd92;
sum_hundred_thousand = 9'd10;
end
endmodule
| 7.028862 |
module decoder_2_4 (
input wire [1:0] in,
output reg [3:0] out
);
always @(*) begin
case (in)
2'b00: begin
out = 4'b0001;
end
2'b01: begin
out = 4'b0010;
end
2'b10: begin
out = 4'b0100;
end
2'b11: begin
out = 4'b1000;
end
... | 7.833664 |
module initalizeBoarder (
clk,
color,
x,
y,
plot,
finished
);
input clk;
output reg [2:0] color;
output reg [7:0] x;
output reg [6:0] y;
output reg plot;
output reg finished;
reg [3:0] total_counter;
reg [2:0] current_state, next_state;
reg [7:0] plot_counter;
localparam P... | 7.240759 |
module dodge_game (
input clk,
input [3:0] keys_in,
input reset,
output vga_h_sync,
output vga_v_sync,
output reg [3:0] vga_R,
output reg [3:0] vga_G,
output reg [3:0] vga_B,
output [6:0] hex_0,
output [6:0] hex_1,
output [6:0] hex_2,
output [6:0] hex_3
);
parameter RI... | 6.605701 |
module doff_change (
change,
dumpoff,
dumpoffin0,
dumpoffin1,
dumpoffin2
);
input [1:0] change;
input dumpoffin0;
input dumpoffin1;
input dumpoffin2;
output dumpoff;
assign dumpoff = (change == 0) ? dumpoffin0 : 1'bz;
assign dumpoff = (change == 1) ? dumpoffin1 : 1'bz;
assign dum... | 6.915065 |
module DOG (
clk,
rst,
valid_in,
data_in,
valid_dog,
data_dog1,
data_dog2,
data_dog3,
data_gus2
);
parameter WIDE = 230,
HIGN = 235,
KERNEL1 = 56'h01_0D_2B_3F_2B_0D_01,
KERNEL2 = 56'h04_0E_1F_28_1F_0E_04,
KERNEL3 = 56'h06_0D_15_19_15_0D_06,
KERN... | 6.672043 |
module DOGImage (
input clk,
input irst_n,
input [8:0] idata_a,
input [8:0] idata_b,
output reg [8:0] odata
);
reg [8:0] r_data_a;
reg [8:0] r_data_b;
always @(posedge clk or negedge irst_n) begin
if (!irst_n) begin
r_data_a <= 0;
r_data_b <= 0... | 7.101366 |
module DOGPyramid (
input iclk,
input irst_n,
input [8:0] GaussianImageData1,
input [8:0] GaussianImageData2,
input [8:0] GaussianImageData3,
input [8:0] GaussianImageData4,
output [8:0] DOGImageData1,
output [8:0] DOGImageData2,
output [8:0] DOGImageData3
);
DOG... | 7.923592 |
module dok (
input clk_sys,
input rin,
input zw,
input int_ext,
output dok_trig,
output dok
);
localparam IDLE = 2'd0;
localparam TRIG = 2'd1;
localparam DOK = 2'd2;
reg [1:0] state;
always @(posedge clk_sys) begin
case (state)
IDLE: if (~zw & rin & int_ext) state <= T... | 7.169169 |
module DOMmul (
port_a,
port_b,
port_u_0
);
input [0:0] port_a;
input [0:0] port_b;
output [0:0] port_u_0;
AND2_X1 U1 (
.A1(port_a[0]),
.A2(port_b[0]),
.ZN(port_u_0[0])
);
endmodule
| 6.587872 |
module DOM (
port_a,
port_b,
port_c,
clk,
reset
);
input [0:0] port_a;
input [0:0] port_b;
output [0:0] port_c;
input clk, reset;
wire mul_port_u_0_0_, ref_1_port_v_0_0_;
DOMmul mul (
.port_a (port_a[0]),
.port_b (port_b[0]),
.port_u_0(mul_port_u_0_0_)
);
DOMref ... | 6.588448 |
module DOMmul (
port_a,
port_b,
port_u_0,
port_u_1
);
input [1:0] port_a;
input [1:0] port_b;
output [1:0] port_u_0;
output [1:0] port_u_1;
AND2_X1 U1 (
.A1(port_b[1]),
.A2(port_a[1]),
.ZN(port_u_1[1])
);
AND2_X1 U2 (
.A1(port_a[1]),
.A2(port_b[0]),
.Z... | 6.587872 |
module DOM (
port_a,
port_b,
port_c,
port_r,
clk,
reset
);
input [1:0] port_a;
input [1:0] port_b;
output [1:0] port_c;
input [0:0] port_r;
input clk, reset;
wire [1:0] mul_port_u_0;
wire [1:0] mul_port_u_1;
wire [1:0] ref_1_port_v_0;
wire [1:0] ref_1_port_v_1;
DOMmul mul (... | 6.588448 |
module DOMmul (
port_a,
port_b,
port_u_0,
port_u_1,
port_u_2
);
input [2:0] port_a;
input [2:0] port_b;
output [2:0] port_u_0;
output [2:0] port_u_1;
output [2:0] port_u_2;
AND2_X1 U1 (
.A1(port_b[2]),
.A2(port_a[2]),
.ZN(port_u_2[2])
);
AND2_X1 U2 (
.A1(por... | 6.587872 |
module DOM (
port_a,
port_b,
port_c,
port_r,
clk,
reset
);
input [2:0] port_a;
input [2:0] port_b;
output [2:0] port_c;
input [2:0] port_r;
input clk, reset;
wire [2:0] mul_port_u_0;
wire [2:0] mul_port_u_1;
wire [2:0] mul_port_u_2;
wire [2:0] ref_1_port_v_0;
wire [2:0] ref_... | 6.588448 |
module DOMmul (
port_a,
port_b,
port_u_0,
port_u_1,
port_u_2,
port_u_3
);
input [3:0] port_a;
input [3:0] port_b;
output [3:0] port_u_0;
output [3:0] port_u_1;
output [3:0] port_u_2;
output [3:0] port_u_3;
AND2_X1 U1 (
.A1(port_b[3]),
.A2(port_a[3]),
.ZN(port_u_... | 6.587872 |
module DOM (
port_a,
port_b,
port_c,
port_r,
clk,
reset
);
input [3:0] port_a;
input [3:0] port_b;
output [3:0] port_c;
input [5:0] port_r;
input clk, reset;
wire [3:0] mul_port_u_0;
wire [3:0] mul_port_u_1;
wire [3:0] mul_port_u_2;
wire [3:0] mul_port_u_3;
wire [3:0] ref_1_... | 6.588448 |
module DOMmul (
port_a,
port_b,
port_u_0,
port_u_1,
port_u_2,
port_u_3,
port_u_4
);
input [4:0] port_a;
input [4:0] port_b;
output [4:0] port_u_0;
output [4:0] port_u_1;
output [4:0] port_u_2;
output [4:0] port_u_3;
output [4:0] port_u_4;
AND2_X1 U1 (
.A1(port_b[4]),
... | 6.587872 |
module DOM (
port_a,
port_b,
port_c,
port_r,
clk,
reset
);
input [4:0] port_a;
input [4:0] port_b;
output [4:0] port_c;
input [9:0] port_r;
input clk, reset;
wire [4:0] mul_port_u_0;
wire [4:0] mul_port_u_1;
wire [4:0] mul_port_u_2;
wire [4:0] mul_port_u_3;
wire [4:0] mul_po... | 6.588448 |
module domain_cross #(
parameter AXIS_TDATA_WIDTH = 32
) (
(* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
input wire [AXIS_TDATA_WIDTH-1:0] S_AXIS_CH1_tdata,
input wire S_AXIS_CH1_tvalid,
output wire S_AXIS_CH1_tready, (* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
output wire [AXIS_TDATA_... | 7.223081 |
module bmux (
ctl,
in_0,
in_1,
z
);
input ctl;
input [3:0] in_0, in_1;
output [3:0] z;
CDN_bmux2 g1 (
.sel0(ctl),
.data0(in_0[3]),
.data1(in_1[3]),
.z(z[3])
);
CDN_bmux2 g2 (
.sel0(ctl),
.data0(in_0[2]),
.data1(in_1[2]),
.z(z[2])
);
CDN_bmu... | 6.96567 |
module CDN_flop (
clk,
d,
sena,
aclr,
apre,
srl,
srd,
q
);
input clk, d, sena, aclr, apre, srl, srd;
output q;
reg qi;
assign #1 q = qi;
always @(posedge clk or posedge apre or posedge aclr)
if (aclr) qi <= 0;
else if (apre) qi <= 1;
else if (srl) qi <= srd;
els... | 7.219105 |
module bmux (
ctl,
in_0,
in_1,
z
);
input ctl;
input [3:0] in_0, in_1;
output [3:0] z;
CDN_bmux2 g1 (
.sel0(ctl),
.data0(in_0[3]),
.data1(in_1[3]),
.z(z[3])
);
CDN_bmux2 g2 (
.sel0(ctl),
.data0(in_0[2]),
.data1(in_1[2]),
.z(z[2])
);
CDN_bmu... | 6.96567 |
module CDN_flop (
clk,
d,
sena,
aclr,
apre,
srl,
srd,
q
);
input clk, d, sena, aclr, apre, srl, srd;
output q;
reg qi;
assign #1 q = qi;
always @(posedge clk or posedge apre or posedge aclr)
if (aclr) qi <= 0;
else if (apre) qi <= 1;
else if (srl) qi <= srd;
els... | 7.219105 |
module bmux (
ctl,
in_0,
in_1,
z
);
input ctl;
input [8:0] in_0, in_1;
output [8:0] z;
CDN_bmux2 g1 (
.sel0(ctl),
.data0(in_0[8]),
.data1(in_1[8]),
.z(z[8])
);
CDN_bmux2 g2 (
.sel0(ctl),
.data0(in_0[7]),
.data1(in_1[7]),
.z(z[7])
);
CDN_bmu... | 6.96567 |
module CDN_flop (
clk,
d,
sena,
aclr,
apre,
srl,
srd,
q
);
input clk, d, sena, aclr, apre, srl, srd;
output q;
reg qi;
assign #1 q = qi;
always @(posedge clk or posedge apre or posedge aclr)
if (aclr) qi <= 0;
else if (apre) qi <= 1;
else if (srl) qi <= srd;
els... | 7.219105 |
module bmux (
ctl,
in_0,
in_1,
z
);
input ctl;
input [15:0] in_0, in_1;
output [15:0] z;
CDN_bmux2 g1 (
.sel0(ctl),
.data0(in_0[15]),
.data1(in_1[15]),
.z(z[15])
);
CDN_bmux2 g2 (
.sel0(ctl),
.data0(in_0[14]),
.data1(in_1[14]),
.z(z[14])
);
... | 6.96567 |
module CDN_flop (
clk,
d,
sena,
aclr,
apre,
srl,
srd,
q
);
input clk, d, sena, aclr, apre, srl, srd;
output q;
reg qi;
assign #1 q = qi;
always @(posedge clk or posedge apre or posedge aclr)
if (aclr) qi <= 0;
else if (apre) qi <= 1;
else if (srl) qi <= srd;
els... | 7.219105 |
module bmux (
ctl,
in_0,
in_1,
z
);
input ctl;
input [24:0] in_0, in_1;
output [24:0] z;
CDN_bmux2 g1 (
.sel0(ctl),
.data0(in_0[24]),
.data1(in_1[24]),
.z(z[24])
);
CDN_bmux2 g2 (
.sel0(ctl),
.data0(in_0[23]),
.data1(in_1[23]),
.z(z[23])
);
... | 6.96567 |
module CDN_flop (
clk,
d,
sena,
aclr,
apre,
srl,
srd,
q
);
input clk, d, sena, aclr, apre, srl, srd;
output q;
reg qi;
assign #1 q = qi;
always @(posedge clk or posedge apre or posedge aclr)
if (aclr) qi <= 0;
else if (apre) qi <= 1;
else if (srl) qi <= srd;
els... | 7.219105 |
module DontCare_z (
input wire rule,
input wire addr,
output wire cout
);
reg n_t;
always @(addr or rule) begin
casez (rule)
1'bx: n_t <= 1'b1;
1'b1: begin
if (addr == 1) n_t <= 1'b1;
else n_t <= 1'b0;
end
1'b0: begin
if (addr == 0) n_t <= 1'b1;
... | 7.302121 |
module holds the state of the doodle.
*
* MAX_JUMP_HEIGHT: how heigh the doodle jumps. a constant int which shows that
* the maximum y value for the doodle is base + MAX_JUMP_HEIGHT.
* base is the Y of the platform doodle is jumping from
*
* falling: shows if the doodle is moving down ward
* hasCollide: if doodle has ... | 8.435863 |
module doodle_x (
input doodle_clk,
input rst,
//Joystick Value
input wire [9:0] posData,
//Vertcial platform positions
input wire [9:0] p1_vpos,
input wire [9:0] p2_vpos,
input wire [9:0] p3_vpos,
input wire [9:0] p4_vpos,
input wire [9:0] p5_vpos,
input wire [9:0] p6_vpos,
... | 7.796983 |
module Door #(
parameter CLK_PER_OPEN = 5
) ( //second
input clk,
input enable,
input reset,
input [2:0] currentFloor,
input [1:0] currentDirection,
input [1:0] currentFloorButton,
input [9:1] internalButton,
output reg door... | 6.953719 |
module doorControl (
reset,
clk,
door_sensor,
open_btn,
close_btn,
door_state,
openDoor,
closeDoor
);
input reset, clk, door_sensor, open_btn, close_btn, door_state;
output openDoor, closeDoor;
wire count_done;
wire [7:0] seconds;
assign seconds = 8'd15;
counter c1 (
re... | 7.603907 |
module doorlock(SW, CLOCK_25, CLOCK_50, GPIO, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR, LEDG);
input CLOCK_25, CLOCK_50;
inout [35:0] GPIO;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
output [17:0] LEDR;
input [17:0] SW;
output [8:0] LEDG;
//wire led_on=1'b1;
wire [25:0]sensor_output;
wire binary_Signal... | 7.361782 |
module: https://github.com/mohammadmoustafa/CSCB58-Winter-2018-Project
// By Alexei Coreiba, Kanstantsin Ilioukevitch, Mohamed Moustafa, Ahmad Shanqiti
// This module was used afte rtaking the permission of the above group.
module usensor(distance, trig, echo, clock);
input clock, echo;
output reg [25:0] distance... | 6.601759 |
module unlock_signal_binary (
input [10:0] inp,
output reg signal,
input clock
);
always @(posedge clock) begin
if (inp < 10'd10) begin
signal <= 1'b1;
end else begin
signal <= 1'b0;
end
end
endmodule
| 7.228072 |
module two_hz_clk (
input inputclock,
output reg outputclock
);
reg [24:0] counter;
initial begin
counter = 0;
outputclock = 0;
end
always @(posedge inputclock) begin
if (counter == 0) begin
counter <= 19999999;
outputclock <= ~outputclock;
end else begin
counter <= co... | 6.741194 |
module hexout (
input unlock_signal,
output reg [6:0] hex_output0,
output reg [6:0] hex_output1,
output reg [6:0] hex_output2,
output reg [6:0] hex_output3,
output reg [6:0] hex_output4,
output reg [6:0] hex_output5
);
always @(*) begin
if (unlock_signal) begin
hex_output0 = 7'b0... | 6.688022 |
module DoorLockProject (
Reset,
SetPass,
PassIn,
Enter,
Access,
Count,
Alarm
);
input Reset, Enter;
input [11:0] SetPass, PassIn;
output Access, Alarm;
output [1:0] Count;
wire Check;
assign Check = !(SetPass ^ PassIn);
modN_ctr Counter (
Enter,
!Check,
Reset... | 7.426184 |
module modN_ctr (
clk,
E,
rstn,
cnt,
Access,
Alarm
);
parameter N = 4;
parameter WIDTH = 2;
input clk, rstn, E;
output reg Access, Alarm;
output reg [WIDTH-1:0] cnt;
always @(posedge clk, posedge rstn)
if (rstn) begin
Alarm <= 0;
cnt <= 0;
end else if (E & cnt ... | 8.160896 |
module door_led_mgmt (
input clk,
input pulse,
output reg led,
output reg close
);
reg [28:0] counter;
parameter max_count = 300000000;
always @(posedge clk) begin
close = 0;
if (pulse) begin
led = 1;
counter = 0;
end
if (led) begin
if (counter >= max_count) be... | 6.5363 |
module door_lock_top (
i_digit,
i_confirm_getter,
i_confirm_FSM,
i_hard_reset,
i_switch,
i_enable_display,
i_clk,
o_LED_correct,
o_LED_incorrect,
o_trials_7seg,
o_pass_7seg_0,
o_pass_7seg_1,
o_pass_7seg_2,
o_input_7seg,
o_state_7seg
);
input [3:0] i_digit;
... | 6.809962 |
module dostring_wave (
output wire led1,
output wire led2,
output wire mosi,
output wire sck,
input wire dostring_reset,
input wire dostring_clk
);
localparam
STR_WAIT_FOR_LED = 0,
STR_LOAD_COLORS = 1,
STR_SEND_COLORS = 2,
STR_CHECK_COUNTERS = 3,
STR_CLEAR_START = 4,
STR_INCREME... | 6.613902 |
module dos_rom_altera (
address,
clock,
q
);
input [12:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsy... | 6.729044 |
module dos_rom_altera (
address,
clock,
q
);
input [12:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.729044 |
module std_mult_pipe (
E,
\out[31]_i_17 ,
clk,
reset,
\done_buf_reg[2] ,
Q,
DSP_A_B_DATA_INST
);
output [0:0] E;
output [31:0] \out[31]_i_17 ;
input clk;
input reset;
input \done_buf_reg[2] ;
input [31:0] Q;
input [31:0] DSP_A_B_DATA_INST;
wire [31:0] DSP_A_B_DATA_INST;
wi... | 7.504255 |
module std_mult_pipe (
E,
\out[31]_i_17 ,
clk,
reset,
\done_buf_reg[2] ,
Q,
DSP_A_B_DATA_INST
);
output [0:0] E;
output [31:0] \out[31]_i_17 ;
input clk;
input reset;
input \done_buf_reg[2] ;
input [31:0] Q;
input [31:0] DSP_A_B_DATA_INST;
wire [31:0] DSP_A_B_DATA_INST;
wi... | 7.504255 |
module std_mult_pipe (
E,
\out[31]_i_17 ,
clk,
reset,
\done_buf_reg[2] ,
Q,
DSP_A_B_DATA_INST
);
output [0:0] E;
output [31:0] \out[31]_i_17 ;
input clk;
input reset;
input \done_buf_reg[2] ;
input [31:0] Q;
input [31:0] DSP_A_B_DATA_INST;
wire [31:0] DSP_A_B_DATA_INST;
wi... | 7.504255 |
module std_mult_pipe (
E,
\out[31]_i_17 ,
clk,
reset,
\done_buf_reg[2] ,
Q,
DSP_A_B_DATA_INST
);
output [0:0] E;
output [31:0] \out[31]_i_17 ;
input clk;
input reset;
input \done_buf_reg[2] ;
input [31:0] Q;
input [31:0] DSP_A_B_DATA_INST;
wire [31:0] DSP_A_B_DATA_INST;
wi... | 7.504255 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
... | 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] o... | 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0]... | 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH... | 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
... | 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
out... | 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
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