code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dma_axi_mux #(
parameter ADDRWIDTH = 11,
parameter NUMLANES = 8,
parameter WIDTH = 16
) (
input [NUMLANES*ADDRWIDTH-1:0] dma_addr,
input [ NUMLANES*WIDTH-1:0] dma_data,
input [ NUMLANES-1:0] dma_rden,
input [ NUMLANES-1:0] dma_wren,
output reg [NUMLANES*WIDTH... | 7.592121 |
module dma_axi_simple
#(parameter AXI_MST_ID =1 // Master ID
, AXI_WIDTH_CID=4
, AXI_WIDTH_ID =4 // ID width in bits
, AXI_WIDTH_AD =32 // address width
, AXI_WIDTH_DA =32 // data width
, AXI_WIDTH_DS =(AXI_W... | 6.936052 |
module dma_bridge #(
parameter DATA_WIDTH = 256,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 31,
parameter BURSTCOUNT_WIDTH = 8,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1,
parameter SYNC_RESET = 0
) (
input wire ... | 7.448531 |
module dma_core_read_read_fifo (
// Inputs
input clk_i
, input rst_i
, input [31:0] data_in_i
, input push_i
, input pop_i
// Outputs
, output [31:0] data_out_o
, output accept_o
, output valid_o
);
//-----------------------------... | 7.321103 |
module dma_core_read_read_fifo_ram_dp_32_5 (
// Inputs
input clk0_i
, input rst0_i
, input [ 4:0] addr0_i
, input [31:0] data0_i
, input wr0_i
, input clk1_i
, input rst1_i
, input [ 4:0] addr1_i
, input [31:0] data1_i
, input wr1_i... | 7.321103 |
module dma_core_write_write_fifo (
// Inputs
input clk_i
, input rst_i
, input [31:0] data_in_i
, input push_i
, input pop_i
// Outputs
, output [31:0] data_out_o
, output accept_o
, output valid_o
, output [ 5:0] level_o
);
/... | 7.217425 |
module dma_core_write_write_fifo_ram_dp_32_5 (
// Inputs
input clk0_i
, input rst0_i
, input [ 4:0] addr0_i
, input [31:0] data0_i
, input wr0_i
, input clk1_i
, input rst1_i
, input [ 4:0] addr1_i
, input [31:0] data1_i
, input wr1... | 7.217425 |
module Dma_Ctrl (
input clk_i,
input rst_i,
input trig_i,
input DMA_Active_i,
input ASSP_DMA_Done_i,
output DMA_Done_o,
output DMA_Clr_o,
input DMA_Enable_i,
output DMA_REQ_o
);
reg dma_req;
reg dma_active_i_1ff;
reg dma_active_i_2ff;
wire dreq_reset;
assign dre... | 6.952083 |
module dma_detect (
clk,
pc,
dma_addr,
dma_en,
irq,
reset,
);
input clk;
input [15:0] pc;
input [15:0] dma_addr;
input dma_en;
input irq;
output reset;
// MACROS ///////////////////////////////////////////
parameter SMEM_BASE = 16'hA000;
parameter SMEM_SIZE =... | 7.174934 |
module dma_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports... | 7.384361 |
module dma_fifo_oneshot (
input wire clk,
input wire rst_n,
input wire wr_stb, // write strobe: writes data from wd to the current wptr, increments wptr
input wire rd_stb, // read strobe: increments rptr
output wire wdone, // write done - all 512 bytes are written (end of write operation)
... | 6.828575 |
module dma_mem (
clk_125_clk_in_clk,
clk_125_clk_in_reset_reset_n,
ddr3_top_memory_mem_a,
ddr3_top_memory_mem_ba,
ddr3_top_memory_mem_ck,
ddr3_top_memory_mem_ck_n,
ddr3_top_memory_mem_cke,
ddr3_top_memory_mem_cs_n,
ddr3_top_memory_mem_dm,
ddr3_top_memory_mem_ras_n,
ddr3_top_m... | 6.939299 |
module dma_mem_cpu_memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "dma_mem_cpu_memory.hex";
output [15:0] readdata;
input [17:0] address;
input [1:0] byteenable... | 6.726555 |
module dma_mem_onchip_memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "dma_mem_onchip_memory.hex";
output [15:0] readdata;
input [17:0] address;
input [1:0] byte... | 6.603503 |
module dma_mem_sdram_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "fals... | 7.646167 |
module dma_mem_sdram_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire... | 7.646167 |
module dma_mem_sdram_p0_flop_mem (
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter REA... | 7.646167 |
module dma_mem_sdram_p0_fr_cycle_extender (
clk,
reset_n,
extend_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have the... | 7.646167 |
module dma_mem_sdram_p0_fr_cycle_shifter (
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their... | 7.646167 |
module dma_mem_sdram_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
.ir_out(),
... | 7.646167 |
module dma_mem_sdram_p0_read_valid_selector (
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2 ** MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] l... | 7.646167 |
module dma_mem_sdram_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
... | 7.646167 |
module dma_mem_sdram_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since... | 7.646167 |
module dma_mp3 (
input wire clk,
input wire rst_n,
output wire [7:0] md_din, // mp3 data interface
output wire md_start, //
input wire md_rdy, //
input wire md_dreq, //
// signals for ports.v
//
input wire [7:0] din, // input and output from ports.v
... | 7.147218 |
module dma_fifo_ram #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input [DATA_WIDTH-1 : 0] wr_data,
input [ADDR_WIDTH-1 : 0] wr_addr,
input [ADDR_WIDTH-1 : 0] rd_addr,
input wr_en,
input rd_en,
input clk,
out... | 7.62771 |
module dma_fifo_ram_mem_size #(
parameter DATA_WIDTH = 32,
parameter MEM_SIZE = 200
) (
wr_data,
wr_addr,
rd_addr,
wr_en,
rd_en,
clk,
rd_data
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin... | 6.748344 |
module dma_prog_rom #(
parameter ROM_SIZE = 6
) (
input clk,
input rst,
input [ 7:0] i_rom_addr,
input i_rom_wr_strobe,
input [31:0] i_rom_data,
output reg o_rom_data_valid,
output [31:0] o_rom_data,
output o_src_address,
output o_dest_address,
... | 7.473381 |
module mux (
signalout,
signal1,
signal2,
sel
);
output reg signalout;
input wire signal1, signal2, sel;
always @(signal1 or signal2 or sel) begin
if (sel == 0) signalout = signal1;
else if (sel == 1) signalout = signal2;
else signalout = 1'bx;
end
endmodule
| 6.536109 |
module addressmux (
signalout,
signal1,
signal2,
sel
);
output reg [7:0] signalout;
input wire [7:0] signal1, signal2;
input wire sel;
always @(signal1 or signal2 or sel) begin
if (sel == 0) signalout = signal1;
else if (sel == 1) signalout = signal2;
else signalout = 1'bx;
end
end... | 6.925373 |
module dma_psdpram #(
// RAM size
parameter SIZE = 4096,
// RAM segment count
parameter SEG_COUNT = 2,
// RAM segment data width
parameter SEG_DATA_WIDTH = 128,
// RAM segment address width
parameter SEG_ADDR_WIDTH = 8,
// RAM segment byte enable width
parameter SEG_BE_WIDTH = SE... | 7.236099 |
module dma_read_arbiter #(
parameter p_paths = 2
) (
input wire i_clk,
input wire i_rst,
input wire [p_paths*32-1:0] ar_dma_read_addr,
input wire [p_paths*10-1:0] ar_dma_read_len,
input wire [p_paths-1:0] ar_dma_read_valid,
output reg [p_paths-1:0] ar_dma_done,
output reg [31:0] dma_r... | 7.055315 |
module dma_read_fifo_4x32 (
// PCI Signals
input [31:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [31:0] dout, // Data out
input delete_en, // Permanently remove an item from the buffer
input undo, // Undo all non-dele... | 8.560977 |
module dma_rw(clk, ce, reset_n, iaddr, oaddr, odata, idata, owren, nblocks, ready, ospi_data, ispi_data, ospi_wr, ispi_dsr, debug);
parameter IDLE=4'd0, BUSY=4'd1, BLOCK=4'd2, OVER=4'd3, NBYTE=4'd4;
parameter BLOCKSIZE=10'd512;
input clk; // clock
input ce; // clock enable
input reset_n; // reset
inpu... | 7.861878 |
module dma_rx (
input wire clock_clk, // clock.clk
input wire reset_n_reset_n, // reset_n.reset_n
input wire [ 31:0] csr_writedata, // csr.writedata
input wire csr_write, //... | 7.695764 |
module fifo512_oneshot (
input wire clk,
input wire rst_n,
input wire init, // initializes fifo: wptr=rptr=0
input wire wr_stb, // write strobe: writes data from wd to the current wptr, increments wptr
input wire rd_stb, // read strobe: increments rptr
output wire wdone, // write done - ... | 6.934062 |
module rr_arbiter (
/*input wire [DEVNUM-1:0]*/ reqs,
/*input wire [DEVNUM-1:0]*/ prev,
/*output wire [DEVNUM-1:0]*/ next
);
parameter DEVNUM = 4;
input wire [DEVNUM-1:0] reqs;
input wire [DEVNUM-1:0] prev;
output wire [DEVNUM-1:0] next;
genvar i;
// arbitration if there was previous... | 8.666807 |
module dma_tb;
reg clk;
reg reset;
reg writes_en;
reg reads_en;
reg calib_done;
reg [31:0] ib_data;
reg [9:0] ib_count;
reg ib_valid;
reg ib_empty;
reg [9:0] ob_count;
reg rd_empty;
reg [31:0] rd_data;
reg cmd_full;
reg wr_full;
dma dma_ (
.clk(clk),
.reset(reset),
... | 6.948361 |
module dma_tb_top;
// Inputs
reg clk;
reg reset_n;
wire [13:0] per_addr;
wire per_en;
wire [1:0] per_wen;
wire [15:0] per_din;
wire dma_ready_p1;
wire [15:0] dma_dout_p1;
wire dma_resp_p1;
wire dma_ready_p2;
wire [15:0] dma_dout_p2;
wire dma_resp_p2;
// Outputs
wire [15:0] per_dout;
w... | 6.708608 |
module dma_tester (
input wire clk,
input wire can_go,
output reg req,
output reg rnw,
output reg [ 7:0] wd,
output reg [20:0] addr,
input wire ack,
input wire done,
input wire [7:0] rd
);
parameter BEG_ADDR = 21'h00C000;
parameter BLK_SIZE = 21'd00... | 7.84937 |
module dma_test_program (
clk,
reset_n,
per_addr,
per_en,
per_wen,
per_din,
per_dout
);
input clk;
input reset_n;
output reg [13:0] per_addr;
output reg per_en;
output reg [1:0] per_wen;
output reg [15:0] per_din;
input [15:0] per_dout;
initial begin
per_addr = 14... | 6.884179 |
module dma_top (
input wire i_clk,
input wire i_rst,
input wire [ 7:0] i_data,
input wire i_data_valid,
output wire [ 7:0] o_data,
output wire o_data_valid,
output wire [255:0] o_ddr_data,
output wire o_ddr_rd_data_valid,
output wire ... | 7.016041 |
module dma_tx (
input wire clock_clk, // clock.clk
input wire reset_n_reset_n, // reset_n.reset_n
input wire [ 31:0] csr_writedata, // csr.writedata
input wire csr_write, //... | 7.348942 |
module dma_write_arbiter #(
parameter p_paths = 2
) (
input wire i_clk,
input wire i_rst,
input wire [p_paths*32-1:0] ar_dma_write_addr,
input wire [p_paths*10-1:0] ar_dma_write_len,
input wire [p_paths-1:0] ar_dma_write_pending,
output reg [p_paths-1:0] ar_dma_write_done,
input wire ... | 6.590585 |
module dma_X_stack (
clk,
pc,
dma_addr,
dma_en,
reset,
);
input clk;
input [15:0] pc;
input [15:0] dma_addr;
input dma_en;
output reset;
// MACROS ///////////////////////////////////////////
parameter SDATA_BASE = 16'h400;
parameter SDATA_SIZE = 16'hC00;
//
par... | 7.821428 |
module dma_zx(
input clk,
input rst_n,
// ZXBUS-related signals
input dma_zxread_toggle;
input dma_zxwrite_toggle;
output reg dma_reswait_n;
input [7:0] dma_data_written;
output reg [7:0] dma_data_toberead;
// different global & control signals
output reg dma_on;
// signals from ports.v
inp... | 7.833447 |
module M_qpsram_qspi__txm_spi (
in_send,
in_trigger,
in_send_else_read,
out_read,
out_clk,
out_csn,
inout_io0,
inout_io1,
inout_io2,
inout_io3,
reset,
out_clock,
clock
);
input [7:0] in_send;
input [0:0] in_trigger;
input [0:0] in_send_else_read;
output [7:0] ... | 6.905155 |
module M_texture_sampler__gpu_drawer_sampler (
in_smplr_do_bind,
in_smplr_do_fetch,
in_smplr_tex_id,
in_smplr_u,
in_smplr_v,
in_txm_data,
in_txm_data_available,
in_txm_busy,
out_smplr_texel,
out_smplr_ready,
out_txm_in_ready,
out_txm_addr,
reset,
out_clock,
cl... | 6.656424 |
module M_span_drawer__gpu_drawer_mem_depths (
input [ 8-1:0] in_addr0,
output reg [16-1:0] out_rdata0,
output reg [16-1:0] out_rdata1,
input [ 1-1:0] in_wenable1,
input [16-1:0] in_wdata1,
input [ 8-1:0] in_addr1,
input clock0,
input clock1... | 7.034655 |
module HWORD (
`ifdef USE_POWER_PINS
input VPWR,
input VGND,
`endif
input CLK,
input WE,
input SELW,
input SELR,
input [15:0] Di,
output [15:0] Do
);
wire [15:0] q_wire;
wire we_wire;
wire SEL_B;
wire GCLK;
sky130_fd_sc_hd__inv_2 INV (
`ifdef USE_POWER_PI... | 7.189114 |
module LINE16 (
`ifdef USE_POWER_PINS
input VPWR,
input VGND,
`endif
input CLK,
input WE,
input SELW,
input SELR,
input [127:0] Di,
output [127:0] Do
);
wire [7:0] CLK_buf;
sky130_fd_sc_hd__clkbuf_4 CLKBUF[7:0] (
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VP... | 6.829617 |
module DEC5x32_DMC (
`ifdef USE_POWER_PINS
input VPWR,
input VGND,
`endif
input [4:0] A,
output [31:0] SEL
);
wire [3:0] en;
DEC2x4_DMC DEC0 (
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
`endif
.A(A[4:3]),
.SEL(en)
);
generate
genvar i;
for (i = 0; i < 4; i =... | 7.054386 |
module dmd (
input clk25,
input RxD,
output TxD,
output [2:0] TMDSp,
TMDSn,
output clk35,
ram_clk,
TMDSp_clock,
TMDSn_clock
//input RxD,
//output TxD
);
wire hSync, vSync, DrawArea;
wire [7:0] red, green, blue;
dcm_pixels pixel_clock (
.CLKIN_IN(clk25),
.R... | 6.525815 |
module dmd_in
//
module dmd_in(
//inputs
input dmd_dotdata,
input dmd_latch,
input dmd_dotclk,
input dmd_enable,
input dmd_rowclock,
input dmd_firstrow,
//outputs
output [127:0] dmd_data_out,
output [4:0] dmd_addr_out,
output dmd_enable_out,
output dmd_latch_out
);
reg [127:0] dmd_data=0;
reg [127:0]... | 7.613809 |
module dmd_in_tb ();
reg dotdata, latch, dotclk, enable, rowclk, firstrow;
reg [127:0] inputpixels;
reg [7:0] i;
wire [127:0] dmddata;
wire [4:0] dmdaddr;
wire enableout;
wire latchout;
initial begin
dotdata = 0;
latch = 0;
dotclk = 0;
enable = 0;
rowclk = 0;
firstrow = 0;
... | 6.734154 |
module DMEM (
input clk,
input wena,
input [`MemAddrBus] addr,
input [`MemBus] idata,
output [`MemBus] odata
);
//reg [7:0] dmem [0:4096];
//assign odata[31:24] = (wena == `MemLoad) ? dmem[addr + 3] : 8'b0;
//assign odata[23:16] = (wena == `MemLoad) ? dmem[addr + 2] : 8'b0;
//assign odata[1... | 6.844967 |
module
//EE 469 with James Peckol 5/7/16
`timescale 1ns/100ps
`include "dmem.v"
module dmem_tb();
wire [15:0] dataOut, dataIn;
wire [10:0] adrx;
wire clk, read, write;
dmem dut (dataOut, clk, dataIn, adrx, read, write);
dmem_tester tet (dataOut, clk, dataIn, adrx, read, write);
initial begin
$dumpfile ("dmem.... | 7.332082 |
module dmem_tester (
dataOut,
clk,
dataIn,
adrx,
read,
write
);
output reg clk, read, write;
output reg [15:0] dataIn;
output reg [10:0] adrx;
input [15:0] dataOut;
parameter period = 2;
initial clk = 1'b1;
always begin
#(period / 2);
clk = !clk;
end
initial begin
... | 7.226868 |
module dMemModel #(
// Vector processor primary parameters
parameter MEM_WIDTH = 64,
parameter DMEM_NUMWORDS = 128,
parameter MEMWIDTH_BYTES = MEM_WIDTH / 8 // memory width in number of bytes
) (
input clock,
input [MEMWIDTH_BYTES-1:0] byteena,
input [ ... | 8.209933 |
module DMemory (
DataOut,
DataIn,
ReadAddr,
WriteAddr,
regWE,
clk
);
input clk, regWE;
input [9:0] ReadAddr, WriteAddr;
input [31:0] DataIn;
output [31:0] DataOut;
integer index;
reg [31:0] mem[1023:0]; // 1024 rows of 32-bit lines
always @(posedge clk) begin
if (regWE) mem[-... | 7.505571 |
module dmem (
input clk,
we,
input [31:0] a,
wd,
output [31:0] rd
);
reg [31:0] RAM[31:0];
initial begin
$readmemh("memfile.dat", RAM);
end
assign rd = RAM[a[31:2]];
always @(posedge clk) if (we) RAM[a[31:2]] <= wd;
endmodule
| 7.276583 |
module dmemstoreext (
input sw,
sh,
sb,
input [1:0] byteaddr,
output reg [3:0] be
);
always @(*) begin
if (sw === 1) be <= 4'b1111;
else if (sh === 1) begin
if (byteaddr[1] === 1) be <= 4'b1100;
else be <= 4'b0011;
end else if (sb === 1) begin
case (byteaddr)
... | 6.800686 |
module dmem_access_unit #(
parameter W = 32
) (
input [W-1:0] i_MEM_instruction,
output reg MemRead,
output reg MemWrite,
output reg [ 1:0] mode
);
localparam word = 2'b00, half_word = 2'b01, B = 2'b10;
always @(*) begin
case (
`get_op(i_MEM_instruction)
) //... | 8.13148 |
module dmem (
byteena_a,
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [3:0] byteena_a;
input [31:0] data;
input [14:0] rdaddress;
input rdclock;
input [14:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsy... | 7.190694 |
module dmem_bram (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input [12:0] address_a;
input [12:0] address_b;
input [3:0] byteena_a;
input clock_a;
input clock_b;
input [31:0] data_a;
i... | 7.076102 |
module dmem_ctrl (
input [31:0] addr,
output reg [31:0] dataout,
input [31:0] datain,
input rdclk,
input wrclk,
input [2:0] memop,
input we
);
wire [31:0] q;
reg [3:0] byteena_a, byteena_a_t;
reg [31:0] datain_t;
dmem my_mem (
.byteena_a(byteena_a),
.data(datain_t),
... | 7.343898 |
module DMem_Error (
addr,
num,
MemWrite_i,
MemRead_i,
MemWrite_o,
MemRead_o,
error_addressOverflow_o,
error_dataMisalign_o
);
// I/O
input [31:0] addr;
input [1:0] num;
input MemRead_i;
input MemWrite_i;
output MemWrite_o;
output MemRead_o;
output error_addressOverflow_... | 6.737819 |
module dmem_mux (
input [15:0] in_core,
input [15:0] in_d_write,
input [15:0] in_d_read,
input [1:0] addr_mux_select,
output reg [15:0] mux_out
);
always @(in_core or in_d_write or in_d_read or addr_mux_select) begin
case (addr_mux_select)
0:mux_out <= in_core;
1:mux_out <... | 8.382124 |
module dmem_rsel (
input [31:0] addr,
output reg [31:0] dout,
input [31:0] bios_doutb,
input [31:0] dmem_douta,
input trmt_full,
input recv_empty,
input [7:0] recv_data,
input [31:0] counter_cycle,
input [31:0] counter_inst,
input buttons_empty,
input [2:0] buttons,
input... | 7.280162 |
module Dmem_UART (
input clock,
input [0:0] Memwrite,
input [15:0] address,
input [31:0] write_data,
output [31:0] read_data,
// UART Programmer Pinouts
input upg_rst_i, // UPG reset (Active High)
input upg_clk_i, // UPG ram_clk_i (10MHz)
input upg_wen_i, // UPG write enable
i... | 6.602241 |
module DmEnMask (
input [7:0] io_addr, // I/O register address
input io_en_i, // I/O register enable
output io_en_o, // Masked I/O register enable
output sp_l_en, // Stack pointer low byte enable
output sp_h_en, // Stack pointer high byte enable
output s... | 7.26373 |
module dmeo_tb ();
reg clock = 1'b0;
reg memWrite = 1'b0;
reg [31:0] addr = 32'h0000_0010;
reg [31:0] writeData = 32'ha000_0000;
wire [31:0] readData;
dmemory32 uram (
readData,
addr,
writeData,
memWrite,
clock
);
always #50 clock = ~clock;
initial begin
#200 writeDat... | 6.99578 |
module DMEXT (
input [31:0] dextIn,
input [2:0] dmOutOP,
input clk,
input rst,
output [31:0] dmOut
);
reg [31:0] dmOutReg;
always @(posedge clk or posedge rst) begin
if (rst) begin
dmOutReg <= 0;
end else begin
case (dmOutOP)
3'b000: dmOutReg <= {{24{dextIn[7]}}, dex... | 9.137582 |
module DMFF (
input wire [31:0] LdInstrNO_AG,
input wire [31:0] LdAddr_AG,
input wire [31:0] StrAddr_AG,
input wire clk,
input wire WE_AG,
input wire [31:0] store_data_AG,
output reg [31:0] WriteData_DM,
output reg [31:0] LdInstrNO_DM,
output reg [31:0] LdAddr_... | 7.864599 |
module dmg_72_1c9994abe91d1da0 (
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input [3 : 0] a;
input [31 : 0] d;
input [3 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(4),
.C_DEFAUL... | 6.713338 |
module dmg_72_903d17a1900ee539 (
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input [3 : 0] a;
input [31 : 0] d;
input [3 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(4),
.C_DEFAUL... | 6.637839 |
module to allow JTAG configuration to work
module DMITap(
input clock,
input reset,
input dmi_in_dmiClock,
input dmi_in_dmiReset,
output dmi_out_dmi_req_valid,
input dmi_out_dmi_req_ready,
output [ 6:0] dmi_out_dmi_req_bits_addr,
output [ 1:0] dmi_out_dmi_req_bits_op,
output [31:0] d... | 7.795787 |
module DMITap (
input clock,
input reset,
output dmi_out_dmi_req_valid,
input dmi_out_dmi_req_ready,
output [ 6:0] dmi_out_dmi_req_bits_addr,
output [ 1:0] dmi_out_dmi_req_bits_op,
output [31:0] dmi_out_dmi_req_bits_data,
input dmi_out_dmi_resp_valid,
output ... | 8.442014 |
module DMITap (
// These are the system clock and reset
input clock,
input reset,
// These are the JTAG Clock and Reset
// Can be ignored
input dmi_in_dmiClock,
input dmi_in_dmiReset,
output dmi_out_dmi_req_valid,
input dmi_out_dmi_req_ready,
output [ 6:0] dmi_ou... | 8.442014 |
module Synchronizes the signals between JTAG (TCK) and
// processor (clk)
//
//-------------------------------------------------------------------------------------
module dmi_jtag_to_core_sync (
// JTAG signals
input rd_en, // 1 bit Read Enable
input ... | 6.777302 |
module for JTAG_TAP and DMI synchronizer
//
//-------------------------------------------------------------------------------------
module dmi_wrapper(
input scan_mode, // scan mode
// JTAG signals
input trst_n, // JTAG reset
input tck, ... | 6.851387 |
module dtlb_ram (
clk,
rst,
read0_addr,
read0_data,
read1_addr,
read1_data,
read2_addr,
read2_data,
read3_addr,
read3_data,
read4_addr,
read4_data,
read5_addr,
read5_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = `dtlb_width;
l... | 8.400099 |
module dtlb_lru_ram (
clk,
rst,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
localparam DATA_WIDTH = 3;
localparam ADDR_WIDTH = 4;
localparam ADDR_COUNT = 16;
input clk;
input rst;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
input [ADD... | 8.581597 |
module lmux (
input [ 1:0] pos,
input [ 2:0] LOp,
input [31:0] DI,
output [31:0] DO
);
reg [31:0] res;
assign DO = res;
always @(*) begin
case (LOp)
`Mem_LW: res <= DI;
`Mem_LH:
res<=
(pos==2'b00)?{{16{DI[15]}},DI[15:0]}:
(pos==2'b10)?{{16{DI[31]}},DI[31:16]}:
... | 7.173486 |
module smux (
input [ 1:0] pos,
input [ 2:0] SOp,
input [31:0] DI,
output [ 3:0] Byteen,
output [31:0] DO
);
reg [ 3:0] BE;
reg [31:0] res;
assign Byteen = BE;
assign DO = res;
always @(*) begin
case (SOp)
`Mem_SW: begin
BE <= 4'b1111;
res <= DI;
end
... | 7.179673 |
module dmn_last #(
parameter ZERO = 0,
parameter PARA1 = 32'hff9911,
parameter PARA2 = 32'd2,
parameter PARA3 = 32'd8
) (
input wire dmn_en,
output wire dmn_end,
output wire zero,
output wire [31:0] dmn_para1,
output wire [31:0] dmn_para2,
output wire [31:0] dmn_para3
);
as... | 7.097494 |
module dmo_dpbuff_macro__rep_1__width_38 (
din,
dout
);
input [37:0] din;
output [37:0] dout;
buff #(38) d0_0 (
.in (din[37:0]),
.out(dout[37:0])
);
endmodule
| 6.600618 |
module dmo_dpbuff_macro__dbuff_48x__rep_1__stack_none__width_36 (
din,
dout
);
input [35:0] din;
output [35:0] dout;
buff #(36) d0_0 (
.in (din[35:0]),
.out(dout[35:0])
);
endmodule
| 6.600618 |
module dmref (
input wire clk,
input wire [10:0] addr_0,
addr_1,
input wire rd,
output reg [7:0] rdata00,
output reg [7:0] rdata01,
output reg [7:0] rdata02,
output reg [7:0] rdata03,
output reg [7:0] rdata10,
output reg [7:0] rdata11,
output reg [7:0] rdata12,
output reg... | 6.800318 |
module dmr_ext (
input [ 1:0] control, //alu_result[1:0]
input [ 5:0] OP, //instr[31:26]
input [31:0] din, //dm_rd_wb
output reg [31:0] dout //dm_rd_ext
);
always @(*) begin
case (OP)
`OP_LB: begin
case (control)
2'b00: dout = {{24{din[7]}},... | 7.255787 |
module dmStore (
input wire clk,
//input wire [20:0] addr,
input wire [3:0] mvx,
input wire [3:0] mvy
);
reg [20:0] addr;
reg [ 3:0] mem [2097151:0][1:0]; // 32-bit memory with 128 entries
initial begin
addr <= 0;
end
always @(posedge clk) begin
//if (wr) begin
mem[addr][0] <= ... | 6.660122 |
module dmtb;
// Inputs
reg clk;
reg clr;
reg [3:0] be;
reg we;
reg [31:0] addr;
reg [31:0] wd;
// Outputs
wire [31:0] dr;
// Instantiate the Unit Under Test (UUT)
DM uut (
.clk (clk),
.clr (clr),
.be (be),
.we (we),
.addr(addr),
.wd (wd),
.dr (dr)
... | 6.901982 |
module dmux (
in,
sel,
a,
b,
c,
d
);
input [3:0] in;
input [1:0] sel;
output reg [3:0] a, b, c, d;
always @(sel or in) begin
case (sel)
2'b00: {a, b, c, d} = {in, 4'b0, 4'b0, 4'b0};
2'b01: {a, b, c, d} = {4'b0, in, 4'b0, 4'b0};
2'b10: {a, b, c, d} = {4'b0, 4... | 7.328451 |
module dmux1_4 (
ic, //źc
is1, //ѡźs1
is0, //ѡźs0
oz0, //źz0
oz1, //źz1
oz2, //źz2
oz3
); //źz3);
input ic, is1, is0;
output reg oz0, oz1, oz2, oz3;
always @(*) begin
case ({
is1, is0
})
2'b00: {oz0, oz1, oz2, oz3} = {ic, 1'b0, 1'b0, 1'b0};
2'b01: {oz0,... | 6.696341 |
module DMux (
in,
sel,
clk,
p,
q
);
input in, sel, clk;
output reg p, q;
initial begin
p = 0;
q = 0;
end
always @(posedge (clk)) begin
p = (sel) ? 0 : in;
q = (sel) ? in : 0;
end
endmodule
| 6.969211 |
module DMux4Way (
input wire in,
input wire [1:0] sel,
output wire a,
output wire b,
output wire c,
output wire d
);
// your implementation comes here:
// DMux(in=in, sel=sel[1], a=ab, b=cd);
// DMux(in=ab, sel=sel[0], a=a, b=b);
// DMux(in=cd, sel=sel[0], a=c, b=d);
wire ab;
wire cd... | 7.306638 |
module DMux4Way_tb ();
integer file;
reg in = 1'b0;
reg [1:0] sel = 2'b00;
wire a;
wire b;
wire c;
wire d;
DMux4Way DMUX4WAY (
.in (in),
.sel(sel),
.a (a),
.b (b),
.c (c),
.d (d)
);
task display;
#1 $fwrite(file, "|%1b|%2b|%1b|%1b|%1b|%1b|\n", in, sel,... | 8.224379 |
module dmux4x16 (
input en,
input [3:0] sel,
output reg [15:0] d
);
always @(sel or en) begin
d = 16'b0;
if (en) begin
case (sel)
4'b0000: d = 16'b0000000000000001; // R0
4'b0001: d = 16'b0000000000000010; // R1
4'b0010: d = 16'b0000000000000100; // R2
4'b... | 8.809625 |
module dmux4x16_tb;
reg en = 1'b0;
reg [3:0] sel = 4'b0;
wire [15:0] d;
reg [3:0] testvectors[15:0];
integer i;
dmux4x16 UUT (
en,
sel,
d
);
initial begin
testvectors[0] = 4'b0000; // R0
testvectors[1] = 4'b0001; // R1
testvectors[2] = 4'b0010; // R2
testvecto... | 7.688807 |
module DMux8 (
in,
sel,
clk,
a,
b,
c,
d,
e,
f,
g,
h
);
input in, clk;
input [2:0] sel;
output reg a, b, c, d, e, f, g, h;
reg p1;
initial begin
p1 = sel[2] ? 1 : 0;
end
always @(negedge (clk)) begin
if (sel == 3'b000) begin
a = in;
b = 0;
... | 6.50664 |
module DMux8Way (
input wire in,
input wire [2:0] sel,
output wire a,
output wire b,
output wire c,
output wire d,
output wire e,
output wire f,
output wire g,
output wire h
);
// your implementation comes here:
// DMux(in=in, sel=sel[2], a=abcd, b=efgh);
// DMux4Way(in=... | 7.127887 |
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