code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic... | 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
outp... | 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width ... | 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
... | 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
assign out = ~in;
endmodule
| 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left & right;
endmodule
| 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left | right;
endmodule
| 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left ^ right;
endmodule
| 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left < right;
endmodule
| 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left == right;
endmodule
| 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left != right;
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left >= right;
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left <= right;
endmodule
| 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
module std_rsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left >> right;
endmodule
| 8.622539 |
module std_mux #(
parameter WIDTH = 32
) (
input wire logic cond,
input wire logic [WIDTH-1:0] tru,
input wire logic [WIDTH-1:0] fal,
output logic [WIDTH-1:0] out
);
assign out = cond ? tru : fal;
endmodule
| 9.56204 |
module std_reg #(
parameter WIDTH = 32
) (
input wire [ WIDTH-1:0] in,
input wire write_en,
input wire clk,
input wire reset,
// output
output logic [WIDTH - 1:0] out,
output logic done
);
always_ff @(posedge clk) begin
... | 7.672256 |
module std_mem_d1 #(
parameter WIDTH = 32,
parameter SIZE = 16,
parameter IDX_SIZE = 4
) (
input wire logic [IDX_SIZE-1:0] addr0,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0... | 8.560454 |
module std_mem_d2 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [ WIDTH-1:0] write_data,
in... | 8.570777 |
module std_mem_d3 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,... | 9.018781 |
module std_mem_d4 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D3_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4,
parameter D3_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE... | 9.168498 |
module std_mult_pipe (
E,
\out[31]_i_17 ,
clk,
reset,
\done_buf_reg[2] ,
Q,
DSP_A_B_DATA_INST
);
output [0:0] E;
output [31:0] \out[31]_i_17 ;
input clk;
input reset;
input \done_buf_reg[2] ;
input [31:0] Q;
input [31:0] DSP_A_B_DATA_INST;
wire [31:0] DSP_A_B_DATA_INST;
wi... | 7.504255 |
module std_mult_pipe (
E,
\out[31]_i_17 ,
clk,
reset,
\done_buf_reg[2] ,
Q,
DSP_A_B_DATA_INST
);
output [0:0] E;
output [31:0] \out[31]_i_17 ;
input clk;
input reset;
input \done_buf_reg[2] ;
input [31:0] Q;
input [31:0] DSP_A_B_DATA_INST;
wire [31:0] DSP_A_B_DATA_INST;
wi... | 7.504255 |
module std_mult_pipe (
E,
\out[31]_i_17 ,
clk,
reset,
\done_buf_reg[2] ,
Q,
DSP_A_B_DATA_INST
);
output [0:0] E;
output [31:0] \out[31]_i_17 ;
input clk;
input reset;
input \done_buf_reg[2] ;
input [31:0] Q;
input [31:0] DSP_A_B_DATA_INST;
wire [31:0] DSP_A_B_DATA_INST;
wi... | 7.504255 |
module std_mult_pipe (
E,
\out[31]_i_17 ,
clk,
reset,
\done_buf_reg[2] ,
Q,
DSP_A_B_DATA_INST
);
output [0:0] E;
output [31:0] \out[31]_i_17 ;
input clk;
input reset;
input \done_buf_reg[2] ;
input [31:0] Q;
input [31:0] DSP_A_B_DATA_INST;
wire [31:0] DSP_A_B_DATA_INST;
wi... | 7.504255 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
... | 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] o... | 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0]... | 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH... | 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
... | 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
out... | 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic... | 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
outp... | 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width ... | 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
... | 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_not1 _impl (
in,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_not8 _impl (
... | 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_and1 _impl (
left,
right,
out
);
end else if (WIDTH == 32) be... | 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_or1 _impl (
left,
right,
out
);
end else begin
$error("Uns... | 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
// if (WIDTH == x) begin
// lakeroad_xilinx_ultrascale_plus_op _impl(in, out);
// end
// //else begin
$error("Unsupported bitwidth %0d", WI... | 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 2) begin
lakeroad_xilinx_ultrascale_plus_add2 _impl (
left,
right,
out
);
end else if (WIDTH == 3) be... | 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_sub5 _impl (
left,
right,
out
);
end else if (WIDTH == 6) beg... | 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left < right;
endmodule
| 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left == right;
endmodule
| 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left != right;
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left >= right;
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left <= right;
endmodule
| 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
module std_rsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left >> right;
endmodule
| 8.622539 |
module std_mux #(
parameter WIDTH = 32
) (
input wire logic cond,
input wire logic [WIDTH-1:0] tru,
input wire logic [WIDTH-1:0] fal,
output logic [WIDTH-1:0] out
);
assign out = cond ? tru : fal;
endmodule
| 9.56204 |
module std_reg #(
parameter WIDTH = 32
) (
input wire [ WIDTH-1:0] in,
input wire write_en,
input wire clk,
input wire reset,
// output
output logic [WIDTH - 1:0] out,
output logic done
);
always_ff @(posedge clk) begin
... | 7.672256 |
module std_mem_d1 #(
parameter WIDTH = 32,
parameter SIZE = 16,
parameter IDX_SIZE = 4
) (
input wire logic [IDX_SIZE-1:0] addr0,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0... | 8.560454 |
module std_mem_d2 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [ WIDTH-1:0] write_data,
in... | 8.570777 |
module std_mem_d3 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,... | 9.018781 |
module std_mem_d4 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D3_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4,
parameter D3_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE... | 9.168498 |
module dot4x_12_ntsc_clockgen (
output wire clk_dot4x,
input wire reset,
input wire clk_in12mhz,
output locked
);
wire clk_dot4x_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clk... | 7.544694 |
module dot4x_12_pal_clockgen (
output wire clk_dot4x,
input wire reset,
input wire clk_in12mhz,
output locked
);
wire clk_dot4x_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkf... | 7.613074 |
module dot4x_14_ntsc_clockgen (
output wire clk_dot4x,
output wire clk_col16x,
input wire reset,
input wire clk_in14mhz,
output locked
);
wire clk_dot4x_clk_wiz_0;
wire clk_col16x_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout_clk_wiz_0;
wire cl... | 7.606885 |
module dot4x_17_pal_clockgen (
output wire clk_dot4x,
output wire clk_col16x,
input wire reset,
input wire clk_in17mhz,
output locked
);
wire clk_dot4x_clk_wiz_0;
wire clk_col16x_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout_clk_wiz_0;
wire clk... | 7.671837 |
module dot4x_50_ntscclockgen (
output wire clk_dot4x,
output wire clk_col4x,
input wire reset,
input wire clk_in50mhz,
output locked
);
wire clk_dot4x_clk_wiz_0;
wire clk_col4x_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout_clk_wiz_0;
wire clkfb... | 7.081564 |
module dot4x_50_pal_clockgen (
output wire clk_dot4x,
output wire clk_col4x,
input wire reset,
input wire clk_in50mhz,
output locked
);
wire clk_dot4x_clk_wiz_0;
wire clk_col4x_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout_clk_wiz_0;
wire clkfb... | 7.265122 |
module that takes an 8x color clock and
// produces 4x dot clocks. The input 8x color clock will
// either be NTSC or PAL timing. The PLL is configured
// to output both clocks and the correct one should be
// selected based on the chip model.
module dot4x_cc_clockgen
(
input RST,
input CLKIN,
ou... | 6.936489 |
module a;
wire \a.b ;
m \c.d (\a.b );
initial begin
\c.d .\y.z <= 1'b1;
#1;
if (\a.b === 1'b1) $display("PASSED");
else $display("FAILED");
end
endmodule
| 6.540542 |
module DotJpeg (
input wire clk,
input wire Rst, // unused
inout [7:0] JA,
output wire [2:0] vgaRed, //red vga output - 3 bits
output wire [2:0] vgaGreen, //green vga output - 3 bits
output wire [1:0] vgaBlue, //blue vga output - 2 bits
output wire Hsync... | 8.630405 |
module dotMatrix (
input clk,
input rst,
input [2:0] value_input, //哆瑞咪发嗦啦西,001为哆, 没有000
input [1:0] tone_input, //00为低音,10为中音,11为高音
input state,
input [2:0] value_play,
input [1:0] tone_play,
output reg [7:0] row, //点阵行
output reg [7:0] line_r, //点阵列 红色
output reg [7:0] line... | 7.482422 |
module fd (
clk_in,
reset,
clk_out
);
input clk_in, reset;
output reg clk_out;
reg [31:0] count;
always @(posedge clk_in) begin
if (!reset) begin
count <= 32'd0;
clk_out <= 1'b0;
end else begin
if (count == `TimeExpire) begin
count <= 0;
clk_out <= ~clk... | 7.187406 |
module DotMatrixDisplay (
clock,
reset,
dot_row,
dot_col
);
input clock, reset;
output reg [7:0] dot_row, dot_col;
wire clk_div;
reg [2:0] row_count;
fd f1 (
.clk_in (clock),
.reset (reset),
.clk_out(clk_div)
);
always @(posedge clk_div, negedge reset) begin
if (~r... | 6.935856 |
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