code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module encode_8b10b (
datain,
dispin,
dataout,
dispout
);
input [8:0] datain;
input dispin; // 0 = neg disp; 1 = pos disp
output [9:0] dataout;
output dispout;
wire ai = datain[0];
wire bi = datain[1];
wire ci = datain[2];
wire di = datain[3];
wire ei = datain[4];
wire fi = datain[... | 6.524693 |
module encenderswitch (
input CLK100MHZ,
input RST,
output reg [7:0] AN,
output reg [6:0] OUT
);
reg [26:0] CONTADOR_SEG; // Contador para generar segundos segun el CLK de la placa. 134.217.728 (ms) para generar CLK
wire SEGUNDO; // Indicador que paso un segundo.
reg [3:0] DISPLAY; // Numero que... | 6.637088 |
module encender_lucesLED (
input [3:0] bin,
input clk,
input reset,
output [3:0] led
);
//Limite del contador para muestrear el valor en el tiempo deseado
localparam limite = 24999999; //Para obtener una seal dividida de 2 Hz
//Formula para la frecuencia deseada:
//f = 1/T => f = 1/500X10^-3 =... | 8.504935 |
module measures the encoder pulse frequency by counting encoder edges
* within a fixed slow clock (~12 Hz) period. Each new slow clock latches the
* current count and starts a new one. From this measurement the encoder
* frequency can be obtained by dividing the number of counts by the period of
* the fixed slow ... | 6.609054 |
module enc4x2 (
xin,
yout
);
input [3:0] xin;
output [1:0] yout;
reg [1:0] yout;
always @(xin) begin
case (xin)
4'b1000: yout = 2'b00;
4'b0100: yout = 2'b01;
4'b0010: yout = 2'b10;
4'b0001: yout = 2'b11;
endcase
end
endmodule
| 7.197643 |
module encode83b(
input wire [7:0] x,
output reg [2:0] y,
output reg valid
);
integer i;
always @ (*)
begin
y = 0;
valid = 0;
for(i+0;i<=7;i=i+1)
if(x[i]==1)
begin
y = i;
valid = 1;
end
end
endmodule
| 6.549725 |
module encode9_testbench;
reg reset, clk,x;
wire [1:0] y; //输入x为1bit，输出y为2bit
viterbi_encoder r1(x, y, clk, reset);
/*-----------------------------------*/
//时钟周期设定（周期为10ns）
/*-----------------------------------*/
initial begin
clk = 0;
forever begin
#5 clk = 1'b1;
#5 clk = 1'b0;
end
end
initial
b... | 6.554988 |
module EncodedRotatingKnob (
input clk,
input knob,
output reg [17:0] value
);
reg reset;
wire [15:0] vcount;
LineCounter VKnob (
clk,
volt,
reset,
vcount
);
initial begin
reset = 0;
value = 0;
end
endmodule
| 7.432384 |
module encoder42_aha (
a0,
a1,
V,
d0,
d1,
d2,
d3
);
input d0, d1, d2, d3;
output a0, a1, V;
assign a0 = d3 | (d1 & (~d2));
assign a1 = d2 | d3;
assign V = d0 | d1 | d2 | d3;
endmodule
| 7.087466 |
module encoder1 (
input clk,
input [7:0] i_data,
input i_rdisp, //running disparity: RD- = 0, RD+ = 1
output [9:0] o_en_data,
output o_rdisp,
input kin // char type control: 1=contorl 0=data
);
reg [2:0] i_y;
reg [4:0] i_x;
wire [5:0] o_6MSB;
wi... | 7.314034 |
module encoder128PL2S (
input clk,
input cen,
input [127:0] RoundKey,
input [127:0] Din,
output wire [127:0] Q, // output for the next stage
output wire [127:0] Dout // final stage output
);
wire [127:0] m, MCin, s;
wire [127:0] SbxR;
assign Q = m ^ Roun... | 6.527505 |
module encode164 (
out,
in,
en
);
output [3:0] out;
input [15:0] in;
input en;
reg [3:0] out;
always @(en or in) begin
out = 0;
if (en == 1) begin
case (in)
16'b0000000000000010: out = 4'b0001;
16'b0000000000000100: out = 4'b0010;
16'b0000000000001000: ou... | 6.585391 |
module encoder16 (
input wire [ 15:0] in,
output reg [3 : 0] out
);
always @(*) begin
case (in)
16'b0000_0000_0000_0000: out = 4'd0;
16'b0000_0000_0000_0010: out = 4'd1;
16'b0000_0000_0000_0100: out = 4'd2;
16'b0000_0000_0000_1000: out = 4'd3;
16'b0000_0000_0001_0000: out =... | 7.892662 |
module encoder16to4to7segdisplay (
display,
code,
i
);
input [15:0] i;
output [6:0] display;
output [3:0] code;
//wire [3:0]code;
encoder16to4 enc16to4 (
code,
i
);
sevenSegmentDisplayDecoder sevendisplay (
display,
code
);
endmodule
| 6.965093 |
module encoder16to4_tb;
reg [15:0] i;
wire [ 3:0] o;
//D.U.T. instantiation
encoder16to4 enc16_4 (
o,
i
);
//初始化
initial begin
$dumpfile("Simulation/encoder16to4_tb.vcd");
$dumpvars;
$monitor($time, " i=%16b --> o=%4b", i, o);
end
//模擬
initial begin
i = 16'b0000000000... | 6.969993 |
module encoder42 (
en,
in3,
in2,
in1,
in0,
Q1,
Q0,
V
);
input en, in3, in2, in1, in0;
output Q1, Q0, V;
// Q1 = ( in3 + in2 ) en
// Q0 = (in3 + ~in2in1 ) en
assign Q1 = (en) & (in3 | in2);
assign Q0 = (en) & ((in3) | ((~in2) & (in1)));
assign V = (en) & ((in3) | (in2) ... | 6.870394 |
module encoder43gates (
A,
B,
C,
D,
Y2,
Y1,
Y0
);
input A, B, C, D;
output Y2, Y1, Y0;
wire Ai, Bi, Ci, Di;
wire w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15;
not NotA (Ai, A);
not NotB (Bi, B);
not NotC (Ci, C);
not NotD (Di, D);
// Gates for Y2
and U1... | 6.90045 |
module encoder43TB;
reg A, B, C, D;
wire [2:0] Ygates, Yexpression, Ytable;
encoder43gates Encoder43Gates (
A,
B,
C,
D,
Ygates[2],
Ygates[1],
Ygates[0]
);
encoder43expression Encoder43Expression (
A,
B,
C,
D,
Yexpression[2],
Yexpre... | 7.494065 |
module encoder4to2 (
input [3:0] in,
output reg [1:0] out
);
always @(*) begin
case (in)
4'b1000: out = 2'b11;
4'b0100: out = 2'b10;
4'b0010: out = 2'b01;
4'b0001: out = 2'b00;
default: out = 2'b00;
endcase
end
endmodule
| 6.87411 |
module encoder4to2_tb;
reg [3:0] i;
wire [1:0] o;
//D.U.T. instantiation
encoder4to2 enc42 (
o,
i
);
//初始化
initial begin
$dumpfile("Simulation/encoder4to2_tb.vcd");
$dumpvars;
$monitor($time, " i=%4b --> o=%2b", i, o);
i = 4'b0000;
end
//模擬
initial begin
i = 4'b0... | 6.612359 |
module test;
reg [3:0] inline;
wire [1:0] oline;
enc e (
inline,
oline
);
initial begin
$display("input and output show");
$monitor("%b,%b,%b,%b,%b,%b", inline[3], inline[2], inline[1], inline[0], oline[1], oline[0]);
$dumpfile("vcd/Encoder.vcd");
$dumpvars(1, test);
inline ... | 6.635152 |
module enc4x2_tb;
wire [1:0] t_yout;
reg [3:0] t_xin;
enc4x2 m1 (
.xin (t_xin),
.yout(t_yout)
);
initial begin
$monitor("%b %b ", t_xin, t_yout);
$display("Xin yout");
t_xin = 4'b1000;
#5 t_xin = 4'b0100;
#5 t_xin = 4'b0010;
#5 t_xin = 4'b0001;
end
endmodule
| 6.789677 |
module encoder83 (
input [7:0] iData,
output reg [2:0] oData
);
always @(*)
case (iData)
8'b10000000: oData = 3'b111;
8'b01000000: oData = 3'b110;
8'b00100000: oData = 3'b101;
8'b00010000: oData = 3'b100;
8'b00001000: oData = 3'b011;
8'b00000100: oData = 3'b010;
8... | 7.632279 |
module encoder83tb ();
reg en, in7, in6, in5, in4, in3, in2, in1, in0;
wire Q2, Q1, Q0, V;
integer i, j;
encoder83 DUT (
en,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
in0,
Q2,
Q1,
Q0,
V
);
initial begin
in7 = 1'b0;
in6 = 1'b0;
... | 6.516757 |
module encoder83_case (
I,
Y
); //8-3编码器，case实现
input I;
output Y;
wire [7:0] I; //8位
reg [3:1] Y;
always @(I) begin
case (I)
8'b0000_0001: Y = 3'b000;
8'b0000_0010: Y = 3'b001;
8'b0000_0100: Y = 3'b010;
8'b0000_1000: Y = 3'b011;
8'b0001_0000: Y = 3'b100;
8'... | 7.57596 |
module encoder8x3 (
in,
out
);
input [7:0] in;
output [2:0] out;
reg [2:0] out;
always @(in)
case (in)
8'b0000_0001: out = 0;
8'b0000_0010: out = 1;
8'b0000_0100: out = 2;
8'b0000_1000: out = 3;
8'b0001_0000: out = 4;
8'b0010_0000: out = 5;
8'b0100_0000: out... | 7.147976 |
module encoder8_3 (
in,
out
);
output [2:0] out;
reg [2:0] out;
input [7:0] in;
wire [7:0] in;
always @(in) begin
case (in)
8'b00000001: out = 3'b000;
8'b00000010: out = 3'b001;
8'b00000100: out = 3'b010;
8'b00001000: out = 3'b011;
8'b00010000: out = 3'b100;
... | 8.371372 |
module Encoder_4 (
input [3:0] in,
output reg [1:0] out
);
initial begin
out <= 0;
end
always @(in) begin
casex (in)
4'b1xxx: out = 3;
4'b01xx: out = 2;
4'b001x: out = 1;
4'b0001: out = 0;
4'b0000: out = 0;
endcase
end
endmodule
| 7.15416 |
module Encoder_8 (
input [7:0] in,
output reg [2:0] out
);
initial begin
out <= 0;
end
always @(in) begin
casex (in)
8'b1xxxxxxx: out = 7;
8'b01xxxxxx: out = 6;
8'b001xxxxx: out = 5;
8'b0001xxxx: out = 4;
8'b00001xxx: out = 3;
8'b000001xx: out = 2;
8'b000... | 7.21308 |
module encoder_1 #(
parameter BIN_WIDTH = 4 // Binary width
) (
input [ BIN_WIDTH-1:0] bin_in, // Binary input
input enable, // enable signal
output reg [2**BIN_WIDTH-1:0] enc_out // Encoded output
);
integer i;
always @(enable or bin_in) begin
enc_out = 0;
... | 6.733091 |
module is based on the coding method described in ////
//// IEEE Std 802.3-2008 Clause 36 "Physical Coding Sublayer(PCS) ////
//// and Physical Medium Attachment (PMA) sublayer, type ////
//// 1000BASE-X"; see : ////
//// ... | 6.830013 |
module encoder_2pNxN #(
parameter N = 2
) (
input [(2**N)-1:0] IN,
output reg [N-1:0] OUT
);
integer i = 0;
always @(*) begin
OUT = 0;
for (i = (2 ** N) - 1; i >= 0; i = i - 1) begin
if (IN[i] == 1'b1) begin
OUT = i;
end
end
end
endmodule
| 6.936903 |
module encoder_2_1 (
input wire [1:0] input_unencoded,
output wire output_valid,
output wire output_encoded
);
assign output_valid = |input_unencoded;
assign output_encoded = input_unencoded[1];
endmodule
| 7.686801 |
module encoder_2_1_0 (
input_unencoded,
output_valid,
output_encoded
);
input [1:0] input_unencoded;
output output_valid, output_encoded;
assign output_encoded = input_unencoded[1];
OR2X1_HVT U1 (
.A1(input_unencoded[0]),
.A2(input_unencoded[1]),
.Y (output_valid)
);
endmodule
... | 6.760445 |
module encoder_2_1_1 (
input_unencoded,
output_valid,
output_encoded
);
input [1:0] input_unencoded;
output output_valid, output_encoded;
assign output_encoded = input_unencoded[1];
OR2X1_HVT U1 (
.A1(input_unencoded[0]),
.A2(input_unencoded[1]),
.Y (output_valid)
);
endmodule
... | 6.909643 |
module encoder_2_1_2 (
input_unencoded,
output_valid,
output_encoded
);
input [1:0] input_unencoded;
output output_valid, output_encoded;
assign output_encoded = input_unencoded[1];
OR2X1_HVT U1 (
.A1(input_unencoded[0]),
.A2(input_unencoded[1]),
.Y (output_valid)
);
endmodule
... | 6.961495 |
module encoder_2_1_3 (
input_unencoded,
output_valid,
output_encoded
);
input [1:0] input_unencoded;
output output_valid, output_encoded;
assign output_encoded = input_unencoded[1];
OR2X1_HVT U1 (
.A1(input_unencoded[0]),
.A2(input_unencoded[1]),
.Y (output_valid)
);
endmodule
... | 6.942999 |
module encoder_2_1_5 (
input_unencoded,
output_valid,
output_encoded
);
input [1:0] input_unencoded;
output output_valid, output_encoded;
assign output_encoded = input_unencoded[1];
OR2X1_HVT U1 (
.A1(input_unencoded[0]),
.A2(input_unencoded[1]),
.Y (output_valid)
);
endmodule
... | 6.721997 |
module encoder_2_1_6 (
input_unencoded,
output_valid,
output_encoded
);
input [1:0] input_unencoded;
output output_valid, output_encoded;
assign output_encoded = input_unencoded[1];
OR2X1_HVT U1 (
.A1(input_unencoded[0]),
.A2(input_unencoded[1]),
.Y (output_valid)
);
endmodule
... | 6.818994 |
module encoder_2_1_7 (
input_unencoded,
output_valid,
output_encoded
);
input [1:0] input_unencoded;
output output_valid, output_encoded;
assign output_encoded = input_unencoded[1];
OR2X1_HVT U1 (
.A1(input_unencoded[0]),
.A2(input_unencoded[1]),
.Y (output_valid)
);
endmodule
... | 6.648333 |
module encoder_32_5 (
input wire [31:0] encIn,
output reg [ 4:0] encOut
);
always @(encIn) begin
case (encIn)
32'h00000001: encOut <= 5'd0;
32'h00000002: encOut <= 5'd1;
32'h00000004: encOut <= 5'd2;
32'h00000008: encOut <= 5'd3;
32'h00000010: encOut <= 5'd4;
32'h000... | 7.61766 |
module encoder_32_to_5 (
input wire [31:0] encoderInput,
output reg [ 4:0] encoderOutput
);
always @(*) begin
case (encoderInput)
32'h00000001: encoderOutput <= 5'd0;
32'h00000002: encoderOutput <= 5'd1;
32'h00000004: encoderOutput <= 5'd2;
32'h00000008: encoderOutput <= 5'd3;
... | 7.343039 |
module encoder_4 (
i_datain,
o_dataout
);
input [3:0] i_datain;
output reg [1:0] o_dataout = 0;
always @(*) begin
if (i_datain[3]) o_dataout <= 3;
else if (i_datain[2]) o_dataout <= 2;
else if (i_datain[1]) o_dataout <= 1;
else if (i_datain[0]) o_dataout <= 0;
else o_dataout <= 0;
e... | 6.857524 |
module encoder_4to2 (
in,
out
);
input [3:0] in;
output [1:0] out;
reg [1:0] out;
always @(*) begin
case (in)
4'b0001: out = 2'b00;
4'b0010: out = 2'b01;
4'b0100: out = 2'b10;
4'b1000: out = 2'b11;
default: out = 2'bx;
endcase
end
endmodule
| 6.992968 |
module encoder_4to2_gates (
i0,
i1,
i2,
i3,
y
);
input i0, i1, i2, i3;
output [1:0] y;
or o1 (y[0], i1, i3);
or o2 (y[1], i2, i3);
endmodule
| 6.823538 |
module encoder_4x2_tb ();
// 1) Declare local reg and wire identifiers
reg [3:0] w;
wire [1:0] y;
integer k;
// 2) Instantiate the unit under test
encoder_4x2 uut0 (
.w(w),
.y(y)
);
// 3) Specify a stopwatch to stop the simulation
initial #170 $finish;
// 4) Generate stimuli, using in... | 6.667887 |
module encoder_4_2 (
input wire [3:0] I,
output wire [1:0] Y
);
reg [1:0] y_r;
always @(I) begin
casex (I)
4'b1110: y_r = 2'b00; //Se pressionado o botao 4
4'b110x: y_r = 2'b10; //Se pressionado o botao 3
4'b10xx: y_r = 2'b01; //Se pressionado o botao 2
4'b0xxx: y_r = 2'b11;... | 7.957049 |
module encoder_4_2_tb;
// Inputs
reg [3:0] din;
// Outputs
wire [1:0] qout;
// Instantiate the Unit Under Test (UUT)
encoder4x2 uut (
.din (din),
.qout(qout)
);
initial begin
// Initialize Inputs
din <= 4'b0000;
#10;
din <= 4'b0001;
#10;
din <= 4'b0010;
#10;... | 7.175641 |
module encoder_5b6b(
input A,B,C,D,E,
input K,
input COMPLS6,
input SBYTECLK
);
// 5b function datatypes -- ex. n_A_a_B = ~(A & B)
wire n_A_nequal_B, n_nA_a_nB, n_A_a_B, n_C_nequal_D, n_nC_a_nD, n_C_a_D; // intermediate wires of Fig. 3 from top to bottom
wire L40, L04, L13, L31, L22; // output wires o... | 7.910736 |
module encoder_5b_3b (
in,
out
);
input [4:0] in;
output [2:0] out;
reg [2:0] out;
always @(in) begin
out = 3'h0;
case (in)
5'b00001: out = 3'h0;
5'b00010: out = 3'h1;
5'b00100: out = 3'h2;
5'b01000: out = 3'h3;
5'b10000: out = 3'h4;
default: out = 3'h0;
... | 6.785478 |
module Encoder_64bit_4_out (
input en,
input [63:0] in,
output reg [5:0] out_1,
out_2,
out_3,
out_4
);
reg [5:0] encode;
integer i, j, count1;
always @(*) begin
for (i = 1; (i < 63) & (!in[i]); i = i + 1) out_1 = i;
end
endmodule
| 6.705971 |
module encoder_7seg (
x,
y
);
input [3:0] x;
output reg [0:6] y;
always @(x) begin
case (x)
0: y = 7'b0000001;
1: y = 7'b1001111;
2: y = 7'b0010010;
3: y = 7'b0000110;
4: y = 7'b1001100;
5: y = 7'b0100100;
6: y = 7'b0100000;
7: y = 7'b0001111;
8: ... | 6.517953 |
module encoder_8 (
i_datain,
o_dataout
);
input [7:0] i_datain;
output reg [2:0] o_dataout = 0;
always @(*) begin
if (i_datain[7]) o_dataout <= 7;
else if (i_datain[6]) o_dataout <= 6;
else if (i_datain[5]) o_dataout <= 5;
else if (i_datain[4]) o_dataout <= 4;
else if (i_datain[3]) o_... | 7.031528 |
module encoder_83 (
in,
out,
en
);
input [7:0] in;
input en;
output [2:0] out;
reg [2:0] out;
always @(in or en) begin
if (en == 1) begin
out = 3'b000;
case (in)
8'd1: out = 3'b000;
8'd2: out = 3'b001;
8'd4: out = 3'b010;
8'd8: out = 3'b011;
... | 7.157563 |
module: encoder_83
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module encoder_83tb;
// Inputs
reg [7:0] in;
reg en;
wire [2:0] out;
integer i;
// Instantiate the Unit Under Tes... | 7.123176 |
module encoder_8b_10b (
input clk,
input rst_n,
input [7:0] data_8b_in,
input ser_en,
output [9:0] data_10b_out
);
reg [3:0] temp_4b;
reg [5:0] temp_6b;
always @(posedge clk) begin
if (!rst_n) begin
temp_4b <= 4'b0000;
temp_6b <= 6'b000000;
end else ... | 6.651956 |
module Encoder_8to3 (
en,
i,
y
);
// declare
input en;
input [7:0] i;
// store and declare output values
output reg [2:0] y;
always @(en, i) begin
if (en == 1) begin
// priority encoder
// if condition to chose
// output based on priority.
if (i[7] == 1) y = 3'b111;... | 7.311115 |
module Encoder_8to3_tb;
reg [7:0] i;
reg en;
wire [2:0] y;
// instantiate the model: creating
// instance for block diagram
Encoder_8to3 dut (
en,
i,
y
);
initial begin
// monitor is used to display the information.
$monitor("en=%b i=%b y=%b", en, i, y);
// since en and... | 6.686909 |
module encoder_8_3_behavioral (
input [7:0] in, // 8 Inputs
output reg [2:0] out
); // 3 Outputs
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(*) begin
case (in)
8'b00000001: out <= 3'b000;
8'b00000010: out <= 3'b001;
8'b00000100: out <= 3'b010;
... | 6.781021 |
module encoder_8_3_beh (
y,
q
);
input [7:0] y;
output [2:0] q;
reg [2:0] q;
always @(y) begin
case (y)
8'b00000001: begin
q = 3'b000;
end
8'b00000010: begin
q = 3'b001;
end
8'b00000100: begin
q = 3'b010;
end
8'b00001000: begin
... | 6.781021 |
module ENCODER_8_3_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [7:0] IN;
wire [2:0] OUT;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg [2:0] OUTEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
encoder_8_3_behavioral U... | 8.205036 |
module Encoder_8_to_3 (
Out,
In,
Enable
);
input [7:0] In;
input Enable;
output reg [2:0] Out;
always @(Enable, In) begin
if (Enable == 1'b1) begin
Out = 3'b000;
case (In)
8'b00000001: Out = 3'b000;
8'b00000010: Out = 3'b001;
8'b00000100: Out = 3'b010;
... | 6.986111 |
module encoder_8_to_3_behavioral (
in_lines,
out_lines
);
input [7:0] in_lines; // 8-bit vector for input lines
output [2:0] out_lines; // 3-bit vector for output lines
// It is important to declare reg of the same size as the output vector.
reg [2:0] out_lines;
//* Behavioral Modelling
always @... | 7.862463 |
module encoder_8_to_3_behavioral_test;
reg [7:0] in_lines;
wire [2:0] out_lines;
encoder_8_to_3_behavioral wire_driver (
in_lines,
out_lines
);
initial begin
in_lines = 8'b00000001;
#20 in_lines = 8'b00000010;
#20 in_lines = 8'b00000100;
#20 in_lines = 8'b00001000;
#20 in_l... | 7.862463 |
module Encoder_8_to_3_TB;
reg [7:0] In;
reg Enable;
wire [2:0] Out;
integer i;
Encoder_8_to_3 uut (
.Out(Out),
.In(In),
.Enable(Enable)
);
initial begin
$monitor($time, " Enable = %b | In = %b | Out = %b", Enable, In, Out);
end
initial begin
Enable = 0;
i = 0;
for (... | 6.986111 |
module encoder_8b10b (
input [7:0] data_i,
input enable_i,
input valid_i,
output [9:0] out10b_o
);
reg [4:0] h3_msb;
reg [4:0] h3_lsb;
reg [4:0] h2_msb;
reg [4:0] h2_lsb;
reg [4:0] h4_msb;
reg [4:0] h4_lsb;
reg [4:0] h1_msb;
reg [4:0] h1_lsb;
reg [9:0] out10b;
h3_encode h3_upper ... | 6.571404 |
module encoder_case(8 binary_out,encoder_in, enable)
18 always @ (enable or encoder_in)
output [3:0] binary_out; // 4 bit binary output 19 begin
input enable ; //Enable for the encoder 20 binary_out = 0;
input [15:0] encoder_in ; //16-bit input 21 if (enable) begin
reg [3:0] binary_out ; 22 ca... | 6.786896 |
module encoder_controller (
input clk,
rst,
backspace_button,
flag,
input [8:0] encoder_switch,
input [1:0] sw_lc,
input [1:0] sw_sc,
input sw_ss,
input [3:0] key,
output [63:0] seg_out,
output beep
);
//register
wire [63:0] seg_out_same;
register regist (
clk,
... | 7.669419 |
module encoder_display (
input clk,
input rst,
input [3:0] state,
input [7:0] b0,
b1,
b2,
b3,
b4,
b5,
b6,
b7,
output reg [7:0] seg_en,
output reg [7:0] seg_out
);
reg clkout;
reg [31:0] cnt;
reg [2:0] scan_cnt;
parameter period = 200000;
always @(posedge cl... | 6.777733 |
module for encoder using for loop-tricky
module encoder_for (output reg [2:0] y,
input wire [7:0] i
);
reg [7:0] test;
integer j;
initial
$display("debugging complete!");
always @( *) begin:encoder
test=8'b0000_0001;
for (j =0 ;j<8 ; j=(j+1)) begin
if ... | 7.126617 |
module encoder_hamming (
input wire [0:10] data_in,
output reg [0:15] c_h,
input wire enable
);
reg [3:0] p;
reg bit_parity; //bit de paridade
always @(*) begin
if (enable == 1'b1) begin
p[0] = ((data_in[0] ^ data_in[1]) ^ (data_in[3] ^ data_in[4])) ^ ((data_in[6] ^ data_in[8]) ^ data_in[... | 7.570136 |
module encoder_tb;
reg clk;
reg [191:0] data;
reg start;
reg ce;
wire ready;
wire [7:0] data_out;
wire first;
wire last;
wire data_bits;
wire ecc_bits;
wire enc_start;
wire [7:0] enc_in;
initial begin
clk = 0;
ce = 1;
start = 0;
data = 192'h123456789ABCDEF0123456789ABCDEF012... | 7.072985 |
module encoder_test (
input clk,
input rst,
input switch,
input en1a,
input en1b,
input en2a,
input en2b,
output [6:0] seg7
);
wire [7:0] bcd, slowclock;
clk_divider(
.clk_in(clk), .rst(), .clk_out(slowclock)
);
encoder encoder (
.clk(clk),
.rst(~rst),
... | 6.808684 |
module encoder_to_decoder_structural (
input [7:0] in, // 8 Inputs
output [7:0] out // 8 Outputs
);
wire [7:0] connect;
// ENCODER
encoder_8_3_behavioral encoder_8_3 (
.in (in),
.out(connect)
);
// DECODER
decoder_3_8_behavioral decoder_3_8 (
.in (connect),
.out(out)
... | 7.221769 |
module ENCODER_TO_DECODER_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [7:0] IN;
wire [7:0] OUT;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] OUTEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
encoder_to_decoder_structural ... | 7.679013 |
module encode_7seg (
input [3:0] DIN,
output reg [6:0] DOUT
);
/*
bit0
------
| |
bit5| bit6 |bit1
------
| |
bit4| |bit2
------
bit3
*/
always @*
case (DIN)
4'd0 : DOUT = 7'b0111111;
4'd1 : DOUT = 7'b0000110;
4'd2 ... | 7.518789 |
module encode_8b10b_tb;
// Inputs
reg clk;
reg rst;
reg [7:0] d_in;
reg nextword_enable;
// Outputs
wire [9:0] d_out;
// Testvars for runlength-testing
reg [19:0] d_out_history;
reg t_fail;
integer fail_count;
integer i, j;
// Instantiate the Unit Under Test (UUT)
encode_8b10b uut (
.clk(clk),
... | 7.488579 |
module encode_controller (
input EN,
input [3:0] row,
input confirm,
input clk,
input rst,
input [1:0] speed_mode,
input [7 : 0] encoder_switch,
output [3:0] col,
output [7:0] seg_en,
output [7:0] seg_out,
output buzzer,
output [1:0] speed_led
);
assign {speed_led[1], s... | 6.926343 |
module encode_decode_tb;
// Inputs
reg clk;
reg nextword_enable;
reg rst;
reg idle;
reg [7:0] d_in;
// Outputs
wire [9:0] encode_out;
wire [7:0] decode_out;
reg match;
encode_8b10b uut (
.clk(clk),
.nextword_enable(nextword_enable),
.rst(rst),
.idle(idle),
.d_in(d_... | 6.600005 |
module encode_mux_16to1_sel4_32_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 3... | 6.662311 |
module encode_mux_4to1_sel2_32_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
) (
input [31 : 0] din1,
input... | 7.105699 |
module AL_BUFKEEP (
i,
o
);
input i;
output o;
parameter KEEP = "OUT";
buf u1 (o, i);
endmodule
| 6.80915 |
module encorder (
input wire in1,
input wire in2,
input wire in3,
output reg [7:0] out
);
/* always@(*)
if ({{in1},{in2},{in3}}==3'b000)
out = 8'd0;
else if ({{in1},{in2},{in3}}==3'b001)
out = 8'd1;
else if ({{in1},{in2},{in3}}==3'b010)
out = 8'd2;
else if ({{in1},{in2},{in3}}==3'b011)... | 8.43287 |
module EncryptionBox (
DataIn,
Key,
DataOut
);
input [63:0] DataIn;
input [47:0] Key;
output [63:0] DataOut;
wire [31:0] fFunctionOut;
fFunction f (
DataIn[31:0],
Key,
fFunctionOut
);
assign DataOut[31:0] = fFunctionOut ^ DataIn[63:32];
assign DataOut[63:32] = DataIn[31:0]... | 6.741554 |
module encryptionKeyGenerator (
input [7:0] p,
input [7:0] q,
input start,
input clk,
output [7:0] e1,
output reg finish
);
reg [15:0] e;
assign e1 = e[7:0];
reg fin;
wire [15:0] phin;
assign phin = (p - 1) * (q - 1); //calculating phi(n)
reg [15:0] x, y, random, gcd;
wire [15:0... | 6.650931 |
module encryption_key (
clk,
reset_n,
phi_n,
e,
d,
start_compute,
done_compute
);
input clk;
input reset_n;
input [63:0] phi_n;
input start_compute;
output [63:0] e;
output done_compute;
output [63:0] d;
wire clk;
wire reset_n;
wire [63:0] phi_n;
wire start_compute;
... | 6.765354 |
module Encryption_module (
CLK,
AESKEY,
RESET,
PLAIN_TXT,
CIPHER_TXT
);
input CLK, RESET;
input [127:0] PLAIN_TXT, AESKEY;
output [127:0] CIPHER_TXT;
wire [127:0] plain_txt, cipher_txt, aeskey, subkey1, subkey2, subkey3;
wire [127:0] subkey4, subkey5, subkey6, subkey7, subkey8, subkey9, ... | 6.770605 |
module UpperModule (
input clock,
input rst,
input button,
input switch,
output txd,
input rxd
);
reg transmits = 0;
// vector to encrypt
wire [127:0] vec = 128'h48656c6c6f2044722e20416465656c21;
// key for AES encryption
wire [127:0] key = 128'h2b7e151628aed2a6abf7158809cf4f3c;
... | 6.724289 |
module encrypt_ByteSub_ShiftRow_Sbox_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH... | 7.340443 |
module encrypt_ByteSub_ShiftRow_Sbox (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataW... | 7.340443 |
module shift_and_sub (
input [127:0] ss_in,
input op,
output [127:0] ss_out
);
wire [127:0] pre_shift;
wire [127:0] sbox_out;
wire [127:0] sbox_out_r;
assign pre_shift = op ? sbox_out : sbox_out_r;
generate
genvar i;
for (i = 0; i < 16; i = i + 1) begin : gen_tbox
aes_sbox sboxs (
... | 7.395032 |
module mul_by_2 (
input [7:0] mul_in,
output [7:0] mul_out
);
assign mul_out = mul_in[7] ? (mul_in << 1) ^ 8'h1b : mul_in << 1;
endmodule
| 7.695257 |
module add (
input [127:0] add_1,
input [127:0] add_2,
output [127:0] add_res
);
assign add_res = add_1 ^ add_2;
endmodule
| 6.686118 |
module encrypt_mux_4to1_sel2_32_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
) (
input [31 : 0] din1,
inpu... | 7.087484 |
module encrypt_tb;
reg clk;
reg rst_n;
reg en;
reg done;
reg [`CIPHERTEXT_WIDTH-1:0] chan1[`PARALLEL-1:0];
reg [`CIPHERTEXT_WIDTH-1:0] chan2[`PARALLEL-1:0];
reg [`DIM_WIDTH:0] row;
reg [`CIPHERTEXT_WIDTH-1:0] ciphertext;
reg [`CIPHERTEXT_WIDTH-1:0] expected;
always #10 clk = ~clk;
encrypt #(
... | 6.688133 |
module encypher (
input [47:0] key_sch,
input [31:0] left_in,
input [31:0] right_in,
output [31:0] left_out,
output [31:0] right_out
);
wire [31:0] func_key;
// Encipher Equations
// L(i) = R(i-1)
// R(i) = L(i-1) XOR f(R(i-1),K(i))
assign left_out = right_in;
assign right_out = le... | 6.826918 |
module tb;
reg [127:0] key[0:10];
reg [3:0] Nr;
reg clk;
reg rst_n;
reg t_ready;
reg [127:0] plaintext;
reg op;
wire [3:0] Addr;
wire Core_Busy;
wire c_ready;
wire [127:0] Ciphertext;
wire [128:0] Key;
initial
fork
key[0] <= 128'h112233445566778899AABBCCDDEEFF00;
//key[0] <= 128'h2b7... | 6.78728 |
module enc_32to5 (
input r0,
r1,
r2,
r3,
r4,
r5,
r6,
r7,
r8,
r9,
r10,
r11,
r12,
r13,
r14,
r15,
input r16,
r17,
r18,
r19,
r20,
r21,
r22,
r23,
r24,
r25,
r26,
r27,
r28,
r29,
r30,
r31,
output ... | 6.618695 |
module enc_4to2 (
input wire a0,
input wire a1,
input wire a2,
input wire a3,
output wire [1:0] out
);
assign out[1] = a3 | a2;
assign out[0] = a3 | a1;
endmodule
| 7.852547 |
module enc_8to3 (
input wire a0,
input wire a1,
input wire a2,
input wire a3,
input wire a4,
input wire a5,
input wire a6,
input wire a7,
output wire [2:0] out
);
assign out[2] = a7 | a6 | a5 | a4;
assign out[1] = a3 | a2 | a7 | a6;
assign out[0] = a3 | a1 | a7 | a5;
endmodul... | 7.49156 |
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