code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Exemplo0053_e_52_test;
reg clk, reset, x;
wire m1, m2;
mealy1010 mealy1 (
m1,
x,
clk,
reset
);
moore1010 moore1 (
m2,
x,
clk,
reset
);
initial begin
$display("Time X Mealy Moore");
// valores iniciais
clk = 1;
reset = 0;
x = 0... | 7.982341 |
module Exemplo0053;
reg x, reset;
wire clk, m;
//instncia
clock clock1 (clk);
moore1110 moore1 (
m,
x,
clk,
reset
);
initial begin
$display("Exemplo0053 - Moore FSM - Guilherme Diniz de Assumpcao - 462269");
$display("Time x Moore");
//initial values
reset =... | 6.866159 |
module Exemplo0054;
reg clk, reset, x;
wire m1;
mealy1110 mealy1 (
m1,
x,
clk,
reset
);
initial begin
$display("Time X Mealy");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 reset = 1;
#10 x = 1;
#10 x = 1;
#10 x = ... | 7.281196 |
module mealyXequal (
y,
x,
clk,
reset
);
output y;
input x, clk, reset;
reg y;
parameter start = 2'b00, idx = 2'b01, idx0 = 2'b11, idx00 = 2'b10;
reg [1:0] E1;
reg [1:0] E2;
always @(x or E1) begin
y = `notfound;
case (E1)
start: E2 = idx;
idx:
if (x) E2 = idx;... | 6.744698 |
module Exemplo0055;
reg x, reset;
wire m, clk;
clock clock1 (clk);
mealyXequal mealy1 (
m,
x,
clk,
reset
);
initial begin
$display("Mealy 3 bits iguais a 0 - Guilherme Diniz de Assumpcao - 462269");
$display("Time x Mealy");
//valores iniciais
x = 0;
reset ... | 7.048808 |
module Exemplo0055;
reg clk, reset, x;
wire m1;
mealyX000 mealy1 (
m1,
x,
clk,
reset
);
initial begin
$display("Time X Mealy");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 reset = 1;
#10 x = 1;
#10 x = 1;
#10 x = ... | 7.048808 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module nandgate (
output s,
input e,
i
);
assign s = (~(e & i));
endmodule
| 7.298658 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk,
input x
);
reg q, qnot;
initial begin
q <= x;
qnot <= ~x;
end
always @(posedge clk) begin
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module cont_ass_cre (
output [4:0] saida,
input pulse,
input jk,
input clear
);
wire q;
reg preset = 0;
// Chamada dos flip - flops
flip_flop_jk_ass ffjk5 (
q,
saida[0],
jk,
jk,
pulse,
clear,
preset
);
flip_flop_jk_ass ffjk4 (
q,
saida... | 6.518316 |
module testnorgate;
reg a, b;
wire s;
norgate sol (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
initial begin : main
$display("\nExemplo 007 - Debora Deslandes de Almeida Batista");
$display("\nMatricula : 451549");
$display("\nTest NOR gate");
$display... | 6.695863 |
module memoria1x4 (
output [3:0] out,
input clk,
input addr,
input rw,
input in,
input preset,
input clr
);
// Chamada das memrias 1x1
memoria1x1 m1 (
out[3],
clk,
addr,
rw,
in,
preset,
clr
);
memoria1x1 m2 (
out[2],
clk,
a... | 7.053696 |
module exemplo0071;
// ---------------- Definio de dados
wire [3:0] out;
reg clk, addr, rw, in, preset, clr;
// ---------------- Instncia
memoria1x4 memo1_4 (
out,
clk,
addr,
rw,
in,
preset,
clr
);
// ---------------- Preparao
initial begin : start
clk = ... | 7.684499 |
module memoria2x4 (
output [3:0] out0,
output [3:0] out1,
input clk,
input addr,
input rw,
input in,
input preset,
input clr
);
wire addr_n;
not not1 (addr_n, addr);
// Chamada das memrias 1x4
memoria1x4 m1 (
out0,
clk,
addr_n,
rw,
in,
prese... | 7.432032 |
module exemplo0072;
// ---------------- Definio de dados
wire [3:0] out0, out1;
reg clk, addr, rw, in, preset, clr;
// ---------------- Instncia
memoria2x4 memo2_4 (
out0,
out1,
clk,
addr,
rw,
in,
preset,
clr
);
// ---------------- Preparao
initial begi... | 7.744255 |
module memoria1x8 (
output [7:0] out,
input clk,
input addr,
input rw,
input in,
input preset,
input clr
);
// Chamada das memrias 1x4
memoria1x4 m1 (
out[7:4],
clk,
addr,
rw,
in,
preset,
clr
);
memoria1x4 m2 (
out[3:0],
clk,
... | 7.126715 |
module exemplo0073;
// ---------------- Definio de dados
wire [7:0] out;
reg clk, addr, rw, in, preset, clr;
// ---------------- Instncia
memoria1x8 memo1_8 (
out,
clk,
addr,
rw,
in,
preset,
clr
);
// ---------------- Preparao
initial begin : start
clk = ... | 7.501071 |
module memoria2x4 (
output [3:0] out,
input clk,
input addr,
input rw,
input in,
input preset,
input clr
);
// Chamada das memrias 1x4
memoria1x4 m1 (
out,
clk,
addr,
rw,
in,
preset,
clr
);
endmodule
| 7.432032 |
module memoria2x8 (
output [7:0] out,
input clk,
input [1:0] addr,
input rw,
input in,
input preset,
input clr
);
// Chamada das memrias 1x4
memoria2x4 m1 (
out[7:4],
clk,
addr[1],
rw,
in,
preset,
clr
);
memoria2x4 m2 (
out[3:0],
... | 6.912811 |
module exemplo0074;
// ---------------- Definio de dados
wire [7:0] out;
reg [1:0] addr;
reg clk, rw, in, preset, clr;
// ---------------- Instncia
memoria2x8 memo2_8 (
out,
clk,
addr,
rw,
in,
preset,
clr
);
// ---------------- Preparao
initial begin : sta... | 7.633192 |
module memoria8x8 (
output [7:0] out0,
output [7:0] out1,
input clk,
input [3:0] addr,
input rw,
input in,
input preset,
input clr
);
// Chamada das memrias 1x4
memoria2x8 m1 (
out0,
clk,
addr[3:2],
rw,
in,
preset,
clr
);
memoria2x8 m2 ... | 6.869006 |
module exemplo0075;
// ---------------- Definio de dados
wire [7:0] out0, out1;
reg [3:0] addr;
reg clk, rw, in, preset, clr;
// ---------------- Instncia
memoria8x8 memo8_8 (
out0,
out1,
clk,
addr,
rw,
in,
preset,
clr
);
// ---------------- Preparao
... | 7.321101 |
module memoria1x16 (
output [15:0] out,
input clk,
input addr,
input rw,
input in,
input preset,
input clr
);
// Chamada das memrias 1x8
memoria1x8 m1 (
out[15:8],
clk,
addr,
rw,
in,
preset,
clr
);
memoria1x8 m2 (
out[7:0],
clk,... | 6.993402 |
module exemplo0076;
// ---------------- Definio de dados
wire [15:0] out;
reg addr;
reg clk, rw, in, preset, clr;
// ---------------- Instncia
memoria1x16 memo1_16 (
out,
clk,
addr,
rw,
in,
preset,
clr
);
// ---------------- Preparao
initial begin : start
... | 6.96922 |
module memoria4x8 (
output [31:0] out,
input clk,
input [3:0] addr,
input rw,
input in,
input preset,
input clr
);
// Chamada das memrias 1x8
memoria1x8 m1 (
out[31:24],
clk,
addr[3],
rw,
in,
preset,
clr
);
memoria1x8 m2 (
out[23:16],... | 7.253506 |
module exemplo0077;
// ---------------- Definio de dados
wire [31:0] out;
reg [ 3:0] addr;
reg clk, rw, in, preset, clr;
// ---------------- Instncia
memoria4x8 memo4_8 (
out,
clk,
addr,
rw,
in,
preset,
clr
);
// ---------------- Preparao
initial begin : s... | 7.447791 |
module xnorgate (
output s,
input a,
b
);
assign s = (~(a ^ b));
endmodule
| 6.74222 |
module testxnorgate;
reg a, b;
wire s;
xnorgate aguaFresca (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
initial begin : main
$display("Exemplo 0009 - Debora Deslandes de Almeida Batista");
$display("Matricula : 451549");
$display("Test XNOR gate");
$di... | 7.028584 |
module nandgate (
output s,
input a,
b
);
assign s = ((~a) | (~b));
endmodule
| 7.298658 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo001 - Ailton Gomes - 440092");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d ... | 6.932753 |
module testnorgate;
reg a, b;
wire s;
norgate estouNaPraia (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
initial begin : main
$display("\nExemplo 0010 - Debora Deslandes de Almeida Batista");
$display("\nMatricula : 451549");
$display("\nTest NOR gate");
... | 6.695863 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - Guilherme Augusto Bueno Borba - 451564");
$display("Test number system");
a = 5;
b = 10;
... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - Guilherme Augusto Bueno Borba-451564");
$display("Test number system");
a = 5;
b = 10;
... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - Guilherme Augusto Bueno Borba-451564");
$display("Test number system");
a = 5;
b = 10;
... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - Guilherme Augusto Bueno Borba-451564");
$display("Test number system");
a = 5;
b = 10;
... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - Guilherme Augusto Bueno Borba-451564");
$display("Test number system");
a = 5;
b = 10;
... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo002 - Ailton Gomes - 440092");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d ... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo002 - Ailton Gomes - 440092");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d ... | 6.932753 |
module f4 (
output [3:0] s0,
output [3:0] s1,
input [3:0] a,
input [3:0] b
);
and AND1 (s0[3], a[3], b[3]);
or OR1 (s1[3], a[3], b[3]);
and AND1 (s0[2], a[2], b[2]);
or OR1 (s1[2], a[2], b[2]);
and AND1 (s0[1], a[1], b[1]);
or OR1 (s1[1], a[1], b[1]);
and AND1 (s0[0], a[0], b[0]);
or O... | 6.784298 |
module test_f4;
// ------------------------- definir dados
reg [3:0] x;
reg [3:0] y;
wire [3:0] z;
wire [3:0] w;
f4 Teste (
z,
w,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exemplo0031 - Douglas Henrique Silvaa Corra - 466503");
$d... | 6.629466 |
module f1 (
output s,
input x,
input y,
input chave
);
wire temp0, temp1, temp2, temp3, nchave;
and AND1 (temp0, x, y);
or OR1 (temp1, x, y);
//-------Multiplexador---------
not NOT1 (nchave, chave);
and AND2 (temp2, temp0, nchave);
and AND3 (temp3, temp1, chave);
or OR2 (s, temp2, te... | 7.102384 |
module f1 (
output s0,
output s1,
input x,
input y,
input chave
);
wire temp0, temp1, temp2, temp3, mtemp0, mtemp1, mtemp2, mtemp3, nchave;
and AND1 (temp0, x, y);
or OR1 (temp1, x, y);
nand NAND1 (temp2, x, y);
nor NOR1 (temp3, x, y);
//-------Multiplexador---------
not NOT1 (nchav... | 7.102384 |
module f4 (
output s,
input a,
input b,
input [1:0] key
);
wire temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8;
wire [1:0] keytemp;
//--entradas
or OR1 (temp0, a, b);
xor XOR1 (temp1, a, b);
//--multiplexador
not NOT1 (keytemp[0], key[1]);
not NOT2 (keytemp[1], key[0]);
... | 6.784298 |
module test_f4;
// ------------------------- definir dados
reg x;
reg y;
reg [1:0] v;
wire z;
f4 Teste (
z,
x,
y,
v
);
// ------------------------- parte principal
initial begin
$display("Exemplo0034 - Douglas Henrique Silva Corra - 466503");
$display("Test LU's mod... | 6.629466 |
module f4 (
output s,
input a,
input b,
input [2:0] key
);
wire temp0, temp1, temp2, temp3,temp4, temp5, temp6, temp7, temp8, temp9, temp10, temp11, temp12, temp13, temp14;
wire [2:0] keytemp;
//--portas
and AND0 (temp0, a, b);
or OR0 (temp1, a, b);
xor XOR0 (temp2, a, b);
not NOT0 (temp3,... | 6.784298 |
module test_f4;
// ------------------------- definir dados
reg x;
reg y;
reg [2:0] v;
wire z;
f4 Teste (
z,
x,
y,
v
);
// ------------------------- parte principal
initial begin
$display("Exemplo0035 - Douglas Henrique Silva Corra - 466503");
$display("Test LU's modu... | 6.629466 |
module f4 (
output [2:0] saida,
input [1:0] entr01,
input [1:0] entr02
);
input [0:0] saidaFinal;
input [2:0] saida_not;
//---NOT
not NOT1 (saida_not[0], entr02[0]);
//---NOT
not NOT2 (saida_not[1], entr02[1]);
//---NOT
not NOT3 (saida_not[2], entr02[1]);
//---AND
and AND1 (saida[0], s... | 6.784298 |
module test_f4;
// ------------------------- definir dados
reg [1:0] x;
reg [1:0] y;
wire [2:0] z;
f4 modulo (
z,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exemplo0031 - Fernando dos Santos Silva - 414506");
$display("Test LU's module \n");... | 6.629466 |
module halfAdder (
s0,
carry_out,
a,
b
);
input a, b;
output s0, carry_out;
xor XOR1 (s0, a, b);
and AND1 (carry_out, a, b);
endmodule
| 7.256462 |
module fullAdder4 (
output [3:0] s,
output carry_out,
input [3:0] a,
input [3:0] b
);
// descrever por portas
wire c_in;
wire c_in1;
wire c_in2;
wire carry_out;
halfAdder HA1 (
s[0],
c_in,
a[0],
b[0]
);
fullAdder FA1 (
s[1],
c_in1,
a[1],
... | 7.492542 |
module test_fullAdder4;
reg [3:0] x;
reg [3:0] y;
reg carry;
wire [3:0] soma;
initial begin
$display("Exemplo00038 - Nome: Roger Rubens Machado - 430533");
$display("Test ALU's full adder");
#1 x = 0000;
y = 0000;
$monitor("x = %3b \t y = %3b\t saida = %3b\n", x, y, soma);
#1 x = 0... | 7.258892 |
module halfAdder (
s0,
carry_out,
a,
b
);
input a, b;
output s0, carry_out;
xor XOR1 (s0, a, b);
and AND1 (carry_out, a, b);
endmodule
| 7.256462 |
module halfSub (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
xor XOR1 (s0, a, b);
and AND1 (s1, ~a, b);
endmodule
| 6.504659 |
module fullSub (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
wire f0, f1, f2;
halfAdder HA1 (
f0,
f1,
a,
b
);
halfAdder HA2 (
s0,
f2,
c,
f0
);
or OR1 (s1, f2, f1);
endmodule
| 6.562172 |
module fullSub4 (
output [3:0] s,
output carryOut,
input [3:0] a,
input [3:0] b
);
// descrever por portas
wire carry_in;
wire carry_in1;
wire carry_in2;
halfSub HS1 (
s[0],
carry_in,
a[0],
b[0]
);
fullSub FS1 (
s[1],
carry_in1,
a[1],
b[1]... | 7.71966 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo002 - Ailton Gomes - 440092");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d ... | 6.932753 |
module comparador (
output s,
input [3:0] a,
input [3:0] b
);
// descrever por portas
wire s0;
wire s1;
wire s2;
wire s3;
xnor XNOR1 (s0, a[0], b[0]);
xnor XNOR2 (s1, a[1], b[1]);
xnor XNOR3 (s2, a[2], b[2]);
xnor XNOR3 (s3, a[3], b[3]);
and AND1 (s, s0, s1, s2, s3);
// descrever... | 7.425908 |
module test_comparador;
// ------------------------- definir dados
reg [3:0] x;
reg [3:0] y;
wire comparado;
comparador modulo (
comparado,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exemplo00040 - Samuel Eusbio da Silva - 435055");
$display... | 8.348558 |
module Exemplo0042;
wire clock;
clock clk (clock);
reg p;
wire p1, t1;
pulse pulse1 (
p1,
clock
);
trigger trigger1 (
t1,
p,
clock
);
initial begin
p = 1'b0;
end
initial begin
$dumpfile("Exemplo0042.vcd");
$dumpvars(1, clock, p1, p, t1);
#060 p = 1'b1;... | 6.608834 |
module pulse2 (
signal,
clock
);
input clock;
output signal;
reg signal;
always @(posedge clock) begin
signal = 1'b1;
#5 signal = 1'b0;
end
endmodule
| 6.524618 |
module pulse3 (
signal,
clock
);
input clock;
output signal;
reg signal;
always @(negedge clock) begin
signal = 1'b1;
#15 signal = 1'b0;
#15 signal = 1'b1;
end
endmodule
| 6.545395 |
module Exemplo0043;
wire clock;
clock clk (clock);
wire p1, p2, p3, p4;
pulse1 pls1 (
p1,
clock
);
pulse2 pls2 (
p2,
clock
);
pulse3 pls3 (
p3,
clock
);
pulse4 pls4 (
p4,
clock
);
initial begin
$dumpfile(" Exemplo0043.vcd");
$dumpvars(1, cl... | 6.51954 |
module Exemplo0044;
wire clock;
clock clk (clock);
wire sinal;
pulse p1 (
sinal,
clock
);
initial begin
$dumpfile("Exemplo0044.vcd");
$dumpvars(1, clock, sinal);
#48 $finish;
end
endmodule
| 6.799566 |
module multiplexador (
output s,
input p,
input q,
input chave
);
wire tmp1, tmp2, tmp3;
not (tmp3, chave);
and (tmp1, p, tmp3);
and (tmp2, q, chave);
or (s, tmp1, tmp2);
endmodule
| 7.509045 |
module Exemplo0051;
reg clk, reset, x;
wire m1, m2;
mealy1101 mealy1 (
m1,
x,
clk,
reset
);
moore1101 moore1 (
m2,
x,
clk,
reset
);
initial begin
$display("Time X Mealy Moore");
// initial values
clk = 1;
reset = 0;
x = 0;
// input si... | 7.137628 |
module Exemplo0051;
reg clk, reset, x;
wire m1, m2;
Mealy1010 mealy1 (
m1,
x,
clk,
reset
);
initial begin
$display("Time X Mealy Moore");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 reset = 1;
#10 x = 1;
#10 x = 0;
#1... | 7.137628 |
module Exemplo0051;
reg clk, reset, x;
wire m1, m2;
Moore1010 moore1 (
m1,
x,
clk,
reset
);
initial begin
$display("Time X Moore");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 reset = 1;
#10 x = 1;
#10 x = 0;
#10 ... | 7.137628 |
module ram1x16 (
output [15:0] saida,
input [15:0] entrada,
input a,
input rw,
input clk
);
ram1x4 r1 (
saida[3:0],
entrada[3:0],
a,
rw,
clk
);
ram1x4 r2 (
saida[7:4],
entrada[7:4],
a,
rw,
clk
);
ram1x4 r3 (
saida[11:8],
... | 6.860417 |
module mux (
output [15:0] saida,
input [15:0] entrada0,
input [15:0] entrada1,
input [15:0] entrada2,
input [15:0] entrada3,
input [ 1:0] a
);
reg [7:0] aux;
parameter start = 2'b00, id01 = 2'b01, id10 = 2'b10, id11 = 2'b11;
always @(a or entrada0 or entrada1 or entrada2 or entrada... | 7.812393 |
module demux (
output [3:0] saida,
input entrada,
input [1:0] a
);
reg [3:0] aux;
parameter start = 2'b00, id01 = 2'b01, id10 = 2'b10, id11 = 2'b11;
always @(a) begin
case (a)
start: aux = 4'b1000;
id01: aux = 4'b0100;
id10: aux = 4'b0010;
id11: aux = 4'b0001;
defaul... | 6.725201 |
module ram1x8 (
output [7:0] saida,
input [7:0] entrada,
input a,
input rw,
input clk
);
wire aux;
wire aux2[7:0];
and a1 (aux, a, rw, clk);
jkff ff1 (
aux2[0],
entrada[0],
~entrada[0],
aux
);
jkff ff2 (
aux2[1],
entrada[1],
~entrada[1],
... | 6.890243 |
module buffer (
output s,
input p
);
assign s = p; // criar vinculo permanente
// (dependencia)
endmodule
| 6.861394 |
module testbuffer;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
buffer BF1 (
s,
a
);
// ------------------------- preparacao
i... | 7.153545 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - Lucas Siqueira Chagas - 380783");
$display("Test number system");
a = 5;
b = 10;
c = ... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0012 - Yousef - 441714");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d = 20;
... | 6.932753 |
module notgate (
output s,
input p
);
assign s = ~p;
endmodule
| 7.575943 |
module testnotgate;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
notgate NOT1 (
s,
a
);
// ------------------------- preparacao
... | 7.480879 |
module test_fullAdder;
// ------------------------- definir dados
reg [3:0] x;
reg [3:0] y;
reg carry;
wire [16:0] soma;
fullAdder full (
soma,
x,
y,
carry
);
// ------------------------- parte principal
initial begin
$display("Exemplo0021 - Fernando Silva - 414506");
... | 7.258892 |
module test_subtractor;
// ------------------------- definir dados
reg [2:0] x;
reg [2:0] y;
reg carry;
wire [16:0] soma;
subtractor Sub (
soma,
x,
y,
carry
);
// ------------------------- parte principal
initial begin
$display("Exemplo0022 - Fernando dos Santos Silva -... | 6.55589 |
module circuit_difference (
output [4:0] s,
input [3:0] a,
input [3:0] b
);
xnor X1 (s[0], a[0], b[0]);
xnor X2 (s[1], a[1], b[1]);
xnor X3 (s[2], a[2], b[2]);
xnor x4 (s[3], a[3], b[3]);
and A1 (s[4], s[0], s[1], s[2], s[3]);
endmodule
| 6.741088 |
module circuit_additionOf2 (
output [2:0] s,
input [2:0] a
);
reg carry = 1'b0;
wire [16:0] soma;
fullAdder full (
soma,
~a,
1'b1,
carry
); //negacao da entrada e soma 1 >> complemento de 2
assign s[0] = soma[11];
assign s[1] = soma[10];
assign s[2] = soma[9];
endmod... | 6.758651 |
module testandgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
... | 6.553783 |
module f4 (
output [3:0] s,
input [3:0] a,
input [3:0] b
);
// descrever por portas
endmodule
| 6.784298 |
module test_f4;
// ------------------------- definir dados
reg [3:0] x;
reg [3:0] y;
wire [3:0] z;
f4 modulo (
z,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exemplo0031 - xxx yyy zzz - 999999");
$display("Test LU's module");
x = 4'b0011;
... | 6.629466 |
module multiplexador (
output s,
input p,
input q,
input r
);
wire temp1, temp2, temp3;
not (temp3, r);
and (temp1, p, temp3);
and (temp2, q, r);
or (s, temp1, temp2);
endmodule
| 7.509045 |
module exemplo0032 (
output s,
input p,
input q,
input chave
);
wire temp1, temp2;
and (temp1, p, q);
or (temp2, p, q);
multiplexador MULT (
s,
temp1,
temp2,
chave
);
endmodule
| 6.913235 |
module testexemplo0032;
reg a, b, c;
wire s;
exemplo0032 Q02(s, a, b, c);
initial begin
a = 'b0;
b = 'b0;
c = 'b0;
#1$monitor("%3b %3b %3b = %3b", a, b, c, s);
#1a= 'b0;b= 'b0;c= 'b1;
#1a= 'b0;b= 'b1;c= 'b0;
#1a= 'b0;b= 'b1;c= 'b1;
#1a= 'b1;b= 'b0;c= 'b0;
#1a= 'b1;b= 'b0;c= 'b1;
#1a= 'b1;b= 'b1;c= 'b0;
#1a= 'b1;b= ... | 6.75191 |
module multiplexador (
output s,
input p,
input q,
input r
);
wire temp1, temp2, temp3;
not (temp3, r);
and (temp1, p, temp3);
and (temp2, q, r);
or (s, temp1, temp2);
endmodule
| 7.509045 |
module exemplo0033 (
output s,
output s1,
input p,
input q,
input chave
);
wire temp1, temp2, temp3, temp4;
and (temp1, p, q);
nand (temp2, p, q);
or (temp3, p, q);
nor (temp4, p, q);
multiplexador MULT (
s,
temp1,
temp2,
chave
);
multiplexador MULT2 (
... | 6.677852 |
module testexemplo0033;
reg a, b, c;
wire s, s1;
exemplo0033 Q03(s, s1, a, b, c);
initial begin
a = 'b0;
b = 'b0;
c = 'b0;
#1$monitor("%3b %3b %3b = %3b %3b", a, b, c, s, s1);
#1a= 'b0;b= 'b0;c= 'b1;
#1a= 'b0;b= 'b1;c= 'b0;
#1a= 'b0;b= 'b1;c= 'b1;
#1a= 'b1;b= 'b0;c= 'b0;
#1a= 'b1;b= 'b0;c= 'b1;
#1a= 'b1;b= 'b1;c= '... | 6.75191 |
module multiplexador (
output s,
input p,
input q,
input r
);
wire temp1, temp2, temp3;
not (temp3, r);
and (temp1, p, temp3);
and (temp2, q, r);
or (s, temp1, temp2);
endmodule
| 7.509045 |
module exemplo0034 (
output s,
input p,
input q,
input [1:0] chave
);
wire temp1, temp2, temp3, temp4, tem5, temp6;
xor (temp1, p, q);
or (temp2, p, q);
xnor (temp3, p, q);
nor (temp4, p, q);
multiplexador MULT (
temp5,
temp1,
temp2,
chave[0]
);
multiplexador M... | 6.589381 |
module testexemplo0034;
reg a, b;
reg [1:0]c;
wire s;
exemplo0034 Q04(s, a, b, c);
initial begin
a= 'b0;
b= 'b0;
c= 'b00;
#1 $monitor("%3b %3b %3b = %3b", a, b, c, s);
#1a= 'b0;b= 'b0;c= 'b01;
#1a= 'b0;b= 'b0;c= 'b10;
#1a= 'b0;b= 'b0;c= 'b11;
#1a= 'b0;b= 'b1;c= 'b00;
#1a= 'b0;b= 'b1;c= 'b01;
#1a= 'b0;b= 'b1;c= 'b10... | 6.75191 |
module multiplexador (
output s,
input p,
input q,
input r
);
wire temp1, temp2, temp3;
not (temp3, r);
and (temp1, p, temp3);
and (temp2, q, r);
or (s, temp1, temp2);
endmodule
| 7.509045 |
module testexemplo0035;
reg [0:0] a;
reg [0:0] b;
reg [4:0] count;
reg [2:0] c;
wire [0:0] s;
exemplo0035 Q05 (
s,
a,
b,
c
);
initial begin
a = 1'b0;
b = 1'b0;
c = 3'b000;
#1 $monitor("%3b %3b %3b = %3b", a, b, c, s);
count = 0;
repeat (31) begin
... | 6.75191 |
module Exemplo0042;
wire clock;
clock clk (clock);
reg p;
wire p1, t1;
pulse pulse1 (
p1,
clock
);
trigger trigger1 (
t1,
p,
clock
);
initial begin
p = 1'b0;
end
initial begin
$dumpfile("Exemplo0042.vcd");
$dumpvars(1, clock, p1, p, t1);
#060 p = 1'b1;... | 6.608834 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = p ^ q;
endmodule
| 7.421731 |
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