code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module MUX4Bits (
s,
data0,
data1,
address
);
output [3:0] s;
input [3:0] data0;
input [3:0] data1;
input address;
reg [3:0] s;
always @(address or data1 or data0) begin
if (~address) begin
s = data0;
end else begin
s = data1;
end
end
endmodule
| 7.471602 |
module MUX8Bits3op (
s,
data0,
data1,
data2,
data3,
data4,
data5,
data6,
data7,
addr
);
output [7:0] s;
input [7:0] data0;
input [7:0] data1;
input [7:0] data2;
input [7:0] data3;
input [7:0] data4;
input [7:0] data5;
input [7:0] data6;
input [7:0] data7;
inpu... | 6.509488 |
module MUX8Bits (
s,
data0,
data1,
address
);
output [7:0] s;
input [7:0] data0;
input [7:0] data1;
input address;
reg [7:0] s;
always @(address or data1 or data0) begin
if (~address) begin
s = data0;
end else begin
s = data1;
end
end
endmodule
| 6.955345 |
module RAM1X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire [3:0] q;
wire [3:0] qnot;
wire [3:0] n;
wire w;
not N0 (n[0], data[3]);
not N1 (n[1], data[2]);
not N2 (n[2], data[1]);
not N3 (n[... | 6.842395 |
module RAM2X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire add0;
wire add1;
wire [3:0] r1;
wire [3:0] r2;
DMUX1Bit SA (
add0,
add1,
address,
1
);
RAM1X4 R1 (
r1... | 6.765373 |
module RAM1X8 (
o,
data,
address,
rw,
clk,
clr
);
output [7:0] o;
input [7:0] data;
input address;
input rw;
input clk;
input clr;
RAM1X4 R1 (
o[3:0],
data[3:0],
address,
rw,
clk,
clr
);
RAM1X4 R2 (
o[7:4],
data[7:4],
addre... | 7.029692 |
module RAM2X8alternativo (
o,
data,
address,
rw,
clk,
clr
);
output [7:0] o;
input [7:0] data;
input address;
input rw;
input clk;
input clr;
wire add0;
wire add1;
wire [7:0] r1;
wire [7:0] r2;
DMUX1Bit SA (
add0,
add1,
address,
1
);
RAM1X8 R1... | 7.032084 |
module RAM4X8 (
o,
data,
address,
rw,
clk,
clr
);
output [7:0] o;
input [7:0] data;
input [1:0] address;
input rw;
input clk;
input clr;
wire [3:0] add;
wire [7:0] r1, r2, r3, r4;
DMUX2Bit SA (
add,
address,
1
);
RAM1X8 R1 (
r1,
data,
... | 6.753934 |
module RAM1X16 (
o,
data,
address,
rw,
clk,
clr
);
output [15:0] o;
input [15:0] data;
input address;
input rw;
input clk;
input clr;
RAM1X8 R1 (
o[7:0],
data[7:0],
address,
rw,
clk,
clr
);
RAM1X8 R2 (
o[15:8],
data[15:8],
... | 7.038405 |
module exercise1_tb ();
reg a, b, c, d;
//Input
wire f;
//Output
exercise1 ex1 (
a,
b,
c,
d,
f
); //Instantiation of the module
initial begin
$dumpfile("exercise1_tb.vcd");
$dumpvars(0, exercise1_tb);
a = 1'b0;
b = 1'b0;
c = 1'b0;
d = 1'b0;
... | 6.526884 |
module exercise2_tb ();
reg a, b, c, d; //Input
wire f, g; //Output
exercise2 ex2 (
a,
b,
c,
d,
f,
g
); //Instantiation of the module
initial begin
$dumpfile("exercise2_tb.vcd");
$dumpvars(0, exercise2_tb);
a = 1'b0;
b = 1'b0;
c = 1'b0;
d = 1'... | 6.549559 |
module nandgate (
s,
p,
q
);
output s;
input p, q;
assign s = ~(p & q);
endmodule
| 7.298658 |
module
// --------------------------------
// -- OR_NAND
// --------------------------------
module orgate (s, p, q);
output s;
input p, q;
wire temp1,temp2;
nandgate nand1(temp1, p, p);
nandgate nand2(temp2, q, q);
nandgate nand3(s, temp1, temp2);
endmodule
| 7.103827 |
module
// ---------------------
// -- TEST OR_NAND
// ---------------------
module testOR_NAND;
reg a, b;
wire s;
// instancia
orgate OR1(s, a, b);
initial begin
a = 0; b = 0;
end
// parte principal
initial begin
$display("Guia 02 - Exercicio 1");
$display("\nMarco Antonio M. Belo - 410796")... | 7.103827 |
module
// --------------------------------
// -- AND_NOR
// --------------------------------
module andgate (s, p, q);
output s;
input p, q;
wire temp1,temp2;
norgate nor1(temp1, p, p);
norgate nor2(temp2, q, q);
norgate nor3(s, temp1, temp2);
endmodule
| 7.103827 |
module
// ---------------------
// -- TEST AND_NOR
// ---------------------
module testAND_NOR;
reg a, b;
wire s;
// instancia
andgate AND1(s, a, b);
initial begin
a = 0; b = 0;
end
// parte principal
initial begin
$display("Guia 02 - Exercicio 2");
$display("\nMarco Antonio M. Belo - 410796... | 7.103827 |
module nandgate (
s,
p
);
output s;
input p;
assign s = ~(p | p);
endmodule
| 7.298658 |
module
// --------------------------------
// -- NOT_NAND
// --------------------------------
module notgate (s, p);
output s;
input p;
nandgate not1(s, p);
endmodule
| 7.103827 |
module
// ---------------------
// -- TEST NOT_NAND
// ---------------------
module testNOT_NAND;
reg a;
wire s;
// instancia
notgate NOT1(s, a);
initial begin
a = 0;
end
// parte principal
initial begin
$display("Guia 02 - Exercicio 3");
$display("\nMarco Antonio M. Belo - 410796");
... | 7.103827 |
module nandgate (
s,
p,
q
);
output s;
input p, q;
assign s = ~(p & q);
endmodule
| 7.298658 |
module testnorgate;
reg a, b;
wire s;
// instancia
norgate NOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Guia 02 Exercicio 4");
$display("Marco Antonio M. Belo - 410796");
$display("Test NOR_NAND gate... | 6.695863 |
module nandgate (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3;
norgate NOR1 (
temp1,
a,
a
);
norgate NOR2 (
temp2,
b,
b
);
norgate NOR3 (
temp3,
temp1,
temp2
);
norgate NOR4 (
s,
temp3,
temp3
);
end... | 7.298658 |
module exercicio01 (
qL,
q,
s,
r
);
output q, qL;
input s, r;
nor NOR1 (qL, s, q);
nor NOR2 (q, r, qL);
endmodule
| 6.619421 |
module exercicio02 (
qL,
q,
s,
r
);
output q, qL;
input s, r;
nand NAND1 (q, s, qL);
nand NAND2 (qL, r, q);
endmodule
| 6.784138 |
module nandgate (
output s,
input a,
b
);
assign s = (~(a & b));
endmodule
| 7.298658 |
module testNORgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
NORgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
end... | 7.487819 |
module XNORgate (
output s,
input p,
q
);
assign s = (~(p ^ q));
endmodule
| 6.59064 |
module testXNORgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
XNORgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
... | 8.437605 |
module AND_Morgangate (
output s,
input p,
q,
r
);
assign s = (~((~p) | (~q) | (~r)));
endmodule
| 6.722316 |
module testAND_Morgangate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
AND_Morgangate AND_Morgan1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : ... | 8.34076 |
module testOR_Morgangate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
OR_Morgangate OR_Morgan1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : sta... | 8.572315 |
module nandgate (
output s,
input p,
input q
);
assign s = (~(p & q));
endmodule
| 7.298658 |
module exnandgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
nandgate NAND1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
end
... | 7.98972 |
module exnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
end
... | 6.681986 |
module xnorgate (
output s,
input p,
input q
);
assign s = (~(p ^ q));
endmodule
| 6.74222 |
module exxnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
end
... | 7.420891 |
module exandgate;
// ------------------------- dados locais
reg a, b, c; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = ... | 8.292104 |
module exorgate;
// ------------------------- dados locais
reg a, b, c; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
orgate OR1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
... | 7.522394 |
module orG2 (
output s,
input x,
input y
);
assign s = x | y;
endmodule
| 7.504938 |
module orG3 (
output s,
input p,
input q,
input r
);
wire s1;
orG2 OR1 (
s1,
p,
q
);
orG2 OR2 (
s,
r,
s1
);
endmodule
| 7.765809 |
module testorG3;
reg a, b, c;
wire s;
orG3 OR3 (
s,
a,
b,
c
);
initial begin : start
a = 0;
end
initial begin : main
$display("Lucas Ranieri - 451594");
$display("Test AND 3 entradas versao 2");
a = 0;
b = 0;
c = 0;
$monitor("%b & %b & %b = %b", a, b,... | 6.574971 |
module testNorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
Norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
... | 7.013841 |
module XNorgate (
output s,
input p,
q
);
assign s = (~(p ^ q));
endmodule
| 6.956177 |
module testXNorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
XNorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = ... | 7.367493 |
module exercicio01 (
s,
a,
b,
c,
d
);
input a, b, c, d;
output s;
wire st1, st2, st3, st4, st5, st6, st7;
not N1 (st1, d);
and A1 (st2, a, b, st1);
not N2 (st4, b);
and A3 (st5, st4, c);
not N3 (st6, a);
and A4 (st7, st6, c);
or O1 (s, st2, st5, st7);
endmodule
| 6.619421 |
module exercicio02 (
s,
a,
b,
c,
d
);
input a, b, c, d;
output s;
wire st1, st2, st3, st4, st5, st6, st7, st8, st9;
not N1 (st1, a);
not N2 (st2, b);
not N3 (st3, c);
not N4 (st4, d);
and A1 (st5, st1, st2, c, st4);
and A2 (st6, st1, b, st3, st4);
and A3 (st7, a, st2, st3);
... | 6.784138 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q = d;
qnot = ~q;
end
endmodule
| 7.02102 |
module teste;
wire [4:0] saida;
reg d;
wire clock;
clock clk (clock);
leftRegister l1 (
saida,
d,
clock
);
initial begin
$display("D CLOCK SAIDA");
d = 1;
$monitor("%1b %1b %5b", d, clock, saida);
#25 d = 0;
#120 $finish;
end
endmodule
| 7.490834 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q = d;
qnot = ~q;
end
endmodule
| 7.02102 |
module teste;
wire [4:0] saida;
reg d;
wire clock;
clock clk (clock);
leftRegister l1 (
saida,
d,
clock
);
initial begin
$display("D CLOCK SAIDA");
d = 1;
$monitor("%1b %1b %5b", d, clock, saida);
#25 d = 0;
#120 $finish;
end
endmodule
| 7.490834 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q = d;
qnot = ~q;
end
endmodule
| 7.02102 |
module teste;
wire [4:0] saida;
reg d;
wire clock;
clock clk (clock);
rightrotateRegister r1 (
saida,
d,
clock
);
initial begin
$display("D CLOCK SAIDA");
d = 1;
$monitor("%1b %1b %5b", d, clock, saida);
#25 d = 0;
#120 $finish;
end
endmodule
| 7.490834 |
module dff (
output q,
output qnot,
input d,
input clk,
input clear,
input preset
);
reg q, qnot;
always @(posedge clk)
if (clear) begin
q <= 0;
qnot <= ~q;
end else if (preset) begin
q <= 1;
qnot <= ~q;
end else begin
q <= d;
qnot <= ~q;
... | 7.02102 |
module
module m6116_ram(
input[7:0] data,
input clk,
input cen,
input[10:0] addr,
input nWE,
output reg [7:0] q
);
reg[7:0] ram[2047:0];
reg[10:0] addr_reg;
always @ (posedge clk)
begin
if (!nWE && cen) ram[addr] <= data;
if (cen) q <=ram[addr];
end
endmodule
| 6.803339 |
module m6116_ramDP (
input [7:0] data,
input [7:0] data_b,
input clk,
input cen,
input [10:0] addr,
input [10:0] addr_b,
input nWE,
nWE_b,
output reg [7:0] q,
q_b
);
reg [7:0] ram[2047:0];
reg [10:0] addr_reg;
always @(posedge clk) begin
if (!nWE && cen) ram[addr] <= d... | 7.08048 |
module m2114_ram (
input [7:0] data,
input clk,
input [6:0] addr,
input nWE,
output reg [7:0] q
);
reg [7:0] ram[127:0];
reg [6:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
q <= ram[addr];
end
endmodule
| 7.31464 |
module m2511_ram_4 (
input [3:0] data,
input clk,
input [8:0] addr,
input nWE,
output reg [3:0] q
);
reg [3:0] ram[511:0];
reg [8:0] addr_reg;
always @(posedge clk) begin
if (!nWE) ram[addr] <= data;
if (nWE) q <= ram[addr];
end
endmodule
| 7.139377 |
module prom6301_L8 (
input [7:0] addr,
input clk,
n_cs,
output reg [3:0] q
);
reg [3:0] rom[255:0];
initial begin
$readmemh("roms/promL8.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.888658 |
module prom6331_E1 (
input [4:0] addr,
input clk,
n_cs,
output reg [7:0] q
);
reg [7:0] rom[31:0];
initial begin
$readmemh("roms/promE1.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.590665 |
module prom6301_3L (
input [7:0] addr,
input clk,
n_cs,
output reg [3:0] q
);
reg [3:0] rom[255:0];
initial begin
$readmemh("roms/prom3L.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.859485 |
module prom6301_4KJ (
input [7:0] addr,
input clk,
n_cs,
output reg [3:0] q
);
reg [3:0] rom[255:0];
initial begin
$readmemh("roms/prom4KJ.txt", rom);
end
always @(posedge clk) begin
if (!n_cs) begin
q <= rom[addr];
end
end
endmodule
| 6.623277 |
module EXEStage (
clk,
EXE_CMD,
val1_sel,
val2_sel,
ST_val_sel,
val1,
val2,
ALU_res_MEM,
result_WB,
ST_value_in,
ALUResult,
ST_value_out
);
input clk;
input [`FORW_SEL_LEN-1:0] val1_sel, val2_sel, ST_val_sel;
input [`EXE_CMD_LEN-1:0] EXE_CMD;
input [`WORD_LEN-1:0]... | 6.67962 |
module EXEStageReg (
rst,
clk,
freeze,
WB_en_in,
MEM_R_EN_in,
MEM_W_EN_in,
ALU_result_in,
ST_val_in,
Dest_in,
WB_en,
MEM_R_EN,
MEM_W_EN,
ALU_result,
ST_val,
Dest
);
input rst, clk, freeze, WB_en_in, MEM_R_EN_in, MEM_W_EN_in;
input [31:0] ALU_result_in, ST... | 7.060844 |
module EXEStageRegTB ();
reg rst = 1, clk = 0, WB_en_in = 0, MEM_R_EN_in = 0, MEM_W_EN_in = 0;
reg [31:0] ALU_result_in = 32'b0, ST_val_in = 32'b0;
reg [3:0] Dest_in = 4'b0;
wire WB_en, MEM_R_EN, MEM_W_EN;
wire [31:0] ALU_result, ST_val;
wire [3:0] Dest;
EXEStageReg UUT (
rst,
clk,
WB_e... | 6.848489 |
module exe01;
reg clk, reset, x;
wire m1;
exe_01 M1 (
m1,
x,
clk,
reset
);
initial begin
$display("Guia 10 EX_01 - Alvaro Rungue");
$display("\nTime\tX Seq 010");
//-- initial values
clk = 1;
reset = 0;
x = 0;
//-- input signal changing
#10... | 6.91556 |
module exe02;
reg clk, reset, x;
wire m1;
exe_02 M1 (
m1,
x,
clk,
reset
);
initial begin
$display("Guia 10 EX_02 - Alvaro Rungue");
$display("\nTime\tX Seq 0110");
//-- initial values
clk = 1;
reset = 0;
x = 0;
//-- input signal changing
#1... | 6.708459 |
module exe03;
reg clk, reset, x;
wire m1;
exe_03 M3 (
m1,
x,
clk,
reset
);
initial begin
$display("Guia 10 EX_03 - Alvaro Rungue");
$display("\nTime\tX Seq 1010");
//-- initial values
clk = 1;
reset = 0;
x = 0;
//-- input signal changing
#1... | 6.955627 |
module exe_04 (
y,
x,
clk,
reset
);
output y;
input x;
input clk;
input reset;
reg y;
parameter //-- state identifiers
start = 3'b000, id1 = 3'b001, id0 = 3'b110, id11 = 3'b010, id00 = 3'b101;
reg [2:0] E1; //-- current state variables
reg [2:0] E2; //-- next state logic output... | 6.660221 |
module exe04;
reg clk, reset, x;
wire m1;
exe_04 M4 (
m1,
x,
clk,
reset
);
initial begin
$display("Guia 10 EX_04 - Alvaro Rungue");
$display("\nTime\tX Seq 111|000");
//-- initial values
clk = 1;
reset = 0;
x = 0;
//-- input signal changing
... | 6.884603 |
module exe05;
reg clk, reset, x;
wire m1;
exe_05 M5 (
m1,
x,
clk,
reset
);
initial begin
$display("Guia 10 EX_05 - Alvaro Rungue");
$display("\nTime\tX Seq 101|010");
//-- initial values
clk = 1;
reset = 0;
x = 0;
//-- input signal changing
... | 6.871288 |
module exe_main (
input clk,
input [63:0] e_read_data1_de,
input [63:0] e_read_data2_de,
input [63:0] e_read_data1_mw,
input [63:0] e_read_data2_mw,
input [63:0] e_read_data1_em,
input [63:0] e_read_data2_em,
input [1:0] e_s1,
input [1:0] e_s2,
input e_alusrc,
input [63:0] e_... | 6.865946 |
module EXE_MEM (
input [31:0] instruction,
input [14:0] ctrl_msg,
input [31:0] alu,
input [31:0] A,
input [31:0] B,
input go,
input clear,
input clk,
output reg [31:0] instruction_out,
output reg [14:0] ctrl_msg_out,
output reg [31:0] alu_out,
output reg [31:0] A_out,
... | 7.469788 |
module EX_MEM_REG (
input Clk,
input Rst,
input MemRead_in,
input MemWrite_in,
input [31:0] ReadData1_in,
input [31:0] ReadData2_in,
input RegWrite_in,
input RegDst_in,
input MemToReg_in,
input [31:0] ALUResult_in,
input Zero_in,
input [31:0] NextInstruct_in,
input [3... | 8.156486 |
module exe_mem_register (
clk,
clrn,
exe_wreg,
exe_m2reg,
exe_wmem,
exe_alu,
exe_b,
exe_rn,
mem_wreg,
mem_m2reg,
mem_wmem,
mem_alu,
mem_b,
mem_rn
);
input [31:0] exe_alu, exe_b; //
input [4:0] exe_rn;
input exe_wreg, exe_m2reg, exe_wmem;
input clk, clrn;
... | 7.107365 |
module exe_mem_register_withWZ (
exe_z,
exe_wz,
clk,
clrn,
exe_wreg,
exe_m2reg,
exe_wmem,
exe_alu,
exe_b,
exe_rn,
mem_wreg,
mem_m2reg,
mem_wmem,
mem_alu,
mem_b,
mem_rn,
mem_z
);
input exe_z, exe_wz;
input clk, clrn;
input exe_wreg, exe_m2reg, exe... | 7.107365 |
module EXE_MEM_stage (
input clk,
input rst,
input [`DSIZE-1:0] aluout_in,
input [`DSIZE-1:0] rdata2_in,
input [`ASIZE-1:0] waddr_in,
input memread_in,
input memwrite_in,
input memtoreg_in,
input wen_in,
input jal_in,
input [`ISIZE-1:0] nPC_in,
output reg [`DSIZE-1:0] a... | 6.540195 |
module exe_mux (
input [63:0] read_data1_de,
input [63:0] read_data2_de,
input [63:0] read_data1_mw,
input [63:0] read_data2_mw,
input [63:0] read_data1_em,
input [63:0] read_data2_em,
input [ 1:0] s1,
input [ 1:0] s2,
output [63:0] read_data1,
output [63:0] read_data2
);... | 7.636662 |
module EXE_Reg (
input clk,
input rst,
input [ `WORD_WIDTH-1:0] pc_in,
input [ `WORD_WIDTH-1:0] instruction_in,
input [`REG_FILE_DEPTH-1:0] dst_in,
input mem_read_in,
mem_write_in,
WB_en... | 7.975131 |
module EXE_register (
clk_i,
rst_i,
instr_i,
WB_i,
Mem_i,
Exe_i,
data1_i,
data2_i,
immgen_i,
alu_ctrl_instr,
WBreg_i,
pc_add4_i,
pc_add4_i,
instr_o,
WB_o,
Mem_o,
Exe_o,
data1_o,
data2_o,
immgen_o,
alu_ctrl_input,
WBreg_o,
pc_add... | 6.856046 |
module exe_stage (
input wire rst,
input wire [4 : 0] inst_type_i,
input wire [7 : 0] inst_opcode,
input wire [`REG_BUS] op1,
input wire [`REG_BUS] op2,
output wire [4 : 0] inst_type_o,
output reg [`REG_BUS] rd_data
);
assign inst_type_o = inst_type_i;
always @(*) begin
if (rst ==... | 7.032438 |
module exe_stage_reg (
clk,
reset,
i_Flush,
i_Freeze,
i_Pc,
i_Sig_Write_Back_Enable,
i_Sig_Memory_Read_Enable,
i_Sig_Memory_Write_Enable,
i_ALU_Result,
i_Value_Rm,
i_Destination,
o_Pc,
o_Sig_Write_Back_Enable,
o_Sig_Memory_Read_Enable,
o_Sig_Memory_Write_Enabl... | 7.268102 |
module: EXE_STAGE
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module EXE_tb;
// Inputs
reg [2:0] ealuc;
reg ealuimm;
reg [31:0] ea;
reg [31:0] eb;
reg [31:0] eimm;
reg eshift;
... | 7.148238 |
module EXE_WB_stage (
input clk,
input [`DSIZE-1:0] alu_in,
input [`ASIZE-1:0] waddr_in,
output reg [`DSIZE-1:0] alu_out,
output reg [`ASIZE-1:0] waddr_out
);
//here we have not taken write enable (wen) as it is always 1 for R and I type instructions.
//ID_EXE register to save the values.
... | 6.750918 |
module branch (
input [ 0:0] br_en_in,
input [31:0] pc,
input [31:0] pc_next,
input [ 3:0] branch_op,
input [ 4:0] br_rd_addr_in,
input [31:0] branch_sr0,
input [31:0] branch_sr1,
input [31:0] branch_imm,
output [31:0] br_rd_data,
output [ 4:0] br_rd_addr_out,
output... | 7.872514 |
module mem0 (
//从exe0段输入
input [ 4:0] mem_rd_in,
input [31:0] mem_data_in,
input [ 0:0] mem_en_in,
input [31:0] mem_sr,
input [31:0] mem_imm,
input [ 0:0] mem_write,
input [ 1:0] mem_width_in,
input [ 6:0] mem_exp_in,
input [ 0:0] mem_... | 6.981436 |
module mem1 (
//从exe0段后输入
input [ 6:0] mem_exp_in,
input [ 4:0] mem_rd_in,
input [ 0:0] mem_en_in,
//从cache输入
//input addr_valid, // read: addr has been accepted; write: addr and data have been accepted
input [ 0:0] data_valid, // read: data has returned; wri... | 7.648224 |
module EXForwardUnit (
clk,
reset_n,
RegWrite_EX_MEM_out,
RegWrite_MEM_WB_out,
rd_EX_MEM_out,
rd_MEM_WB_out,
rs_ID_EX_out,
rt_ID_EX_out,
forwardA,
forwardB
);
input clk, reset_n;
input [1:0] rd_EX_MEM_out;
input [1:0] rd_MEM_WB_out;
input [1:0] rs_ID_EX_out;
input [1:0... | 7.315294 |
module ExistTerminalCase (
input wire `INDEX_DEF f,
input wire `VAR_DEF top,
input wire `VAR_DEF cubeLastVar,
output wire hit,
output wire `INDEX_DEF result
);
wire topBigger, equal_f_zero, equal_f_one;
assign topBigger = (top > cubeLastVar);
assign equal_f_zero = (f == `BDD_ZERO);
as... | 7.231624 |
module ExistTerminalCaseNoVar (
input wire `INDEX_DEF f,
output wire hit,
output wire `INDEX_DEF result
);
wire equal_f_zero, equal_f_one;
assign equal_f_zero = (f == `BDD_ZERO);
assign equal_f_one = (f == `BDD_ONE);
assign hit = (equal_f_zero | equal_f_one);
assign result = f;
endmodule
| 7.231624 |
module EXMEM (
input clk,
input [31:0] alu_out,
input [31:0] IDEXrf_rd1,
input [ 4:0] IDEXRd,
input [31:0] IDEXpc,
input IDEXrf_wr_en,
input [2:0] IDEXdm_rd_ctrl,
input [1:0] IDEXdm_wr_ctrl,
input [1:0] IDEXrf_wr_sel,
output reg [31:0] EXMEMalu_out,
output reg [31:0] EXMEM... | 6.633817 |
module ExMemBuffer (
input RegWrite,
MemOrReg,
DestOrPrivate,
MemWrite,
MemRead,
clk,
SPOrALUres,
iamBubble,
input [3:0] regDestAddress,
input [15:0] ALUResult,
RegSrc,
input [1:0] SPOpeartion,
output reg oRegWrite,
oMemOrReg,
oMemWrite,
oMemRead,
oDes... | 6.774149 |
module EXMEMReg (
input clk,
input rst,
input EXMEMStall,
input EXMEMFlush,
input [31:0] IDEXInstruction,
output reg [31:0] EXMEMInstruction,
input [31:0] IDEXPCPlus4,
output reg [31:0] EXMEMPCPlus4,
input [31:0] IDEXMemWriteData,
output reg [31:0] EXMEMMemWriteData,
input [3... | 6.84571 |
module ExMemRegisters (
input clock,
input reset,
input [31:0] ex_instruction,
input ex_shouldWriteRegister,
input [4:0] ex_registerWriteAddress,
input ex_shouldWriteMemoryElseAluOutputToRegister,
input [31:0] ex_aluOutput,
input ex_shouldWriteMemory,
input [31:0] ex_registerRtOr... | 8.101913 |
module EXMEMRegs (
input clk,
input rst,
input en,
//Inputs
input [31:0] writePC,
//input writeZero,
input [31:0] writeALUOutput,
input [31:0] writeReadData2Forw,
input [ 4:0] writeRd,
input writeRegWrite,
input [ 1:0] writeWriteDataSrc,
... | 7.606139 |
module is the EX/MEM stage pipeline registers.
* It takes EX stage outputs and passes to the MEM stage
*/
module exmem_reg #(
parameter DATA_WIDTH = 32
)(
input clk,
input exmem_bubble,
//////////////////////////////////////
// output of ex stage
//////////////////////////////////////
input [DATA_WIDTH... | 8.305381 |
module EXMEM_Register (
output reg [1:0] Size_Out,
output reg Enable_Out,
output reg rw_Out,
output reg Load_Out,
output reg rf_Out,
output reg [31:0] RegFile_PortC_Out,
output reg [31:0] ALU_Out,
output reg [3:0] Rd_Out,
input [1:0] Size_In,
input Enable_In,
input rw_In,
... | 6.865284 |
module inc_8_0 (
cin,
a,
d,
cout
);
input cin;
input [7:0] a;
output [7:0] d;
output cout;
wire nx8479z3, nx8473z3, nx8473z1, nx8474z3, nx8474z1, nx8475z3, nx8475z1,
nx8476z3, nx8476z1, nx8477z3, nx8477z1, nx8478z3, nx8478z1, nx8479z4,
nx8479z1, nx51681z2;
GND ps_gnd... | 6.96137 |
module exm_write_back_buffer (
input i_clk,
input i_reset,
input [15:0] i_ex_result,
input [15:0] i_memory_data,
input [15:0] i_immediate,
input [15:0] i_port,
input [1:0] i_wb_selector,
input i_write_back,
input [2:0] i_write_addr,
output reg [2:0] o_write_addr,
output reg [... | 7.253073 |
module ExNumber (
input [15:0] IR, //Imm,Offset
input Ex_top,
input [2:0] ALU_SrcB,
input [31:0] Rt_out,
output [31:0] B_in
);
wire [31:0] Ex_offset, Imm_ex, addroffset_ex;
assign Ex_offset = {((Ex_top == 1) ? {16{IR[15]}} : 16'b0), IR[15:0]}; //2,Imm
assign Imm_ex = {IR, 16'b0}; //4,Lui
... | 6.731752 |
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