code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module exoor (
in1,
in2,
out
);
input in1, in2;
output out;
`SR(s38, assign out = in1 ^ in2;, assign out = 'b0;)
endmodule
| 8.036115 |
module exor4 (
input [3:0] a,
input [3:0] b,
output [3:0] out
);
xor xor0 (out[0], a[0], b[0]);
xor xor1 (out[1], a[1], b[1]);
xor xor2 (out[2], a[2], b[2]);
xor xor3 (out[3], a[3], b[3]);
endmodule
| 7.489275 |
module ALU_1 (
result,
sum,
Cout,
Cin,
a,
b,
less,
m
);
output result, sum, Cout;
input Cin, a, b, less;
input [2:0] m;
wire wOR, wAND, wXOR, wXORm, wNOR, wNAND;
OR or1 (
wOR,
a,
b
);
AND and1 (
wAND,
a,
b
);
XOR xor1 (
wXOR,
... | 6.679398 |
module ALU_8 (
result,
sum,
Cout,
Cin,
a,
b,
less,
m
);
output [7:0] result, sum;
output Cout;
input Cin;
input [7:0] a, b, less;
input [2:0] m;
wire wCout0, wCout1, wCout2, wCout3, wCout4, wCout5, wCout6;
ALU_1 alu8_0 (
result[0],
sum[0],
wCout0,
C... | 6.514836 |
module FullAdder (
Cout,
sum,
a,
b,
Cin
);
output sum, Cout;
input Cin, a, b;
wire w1, w2, w3;
XOR3 x0 (
sum,
a,
b,
Cin
);
AND a0 (
w1,
a,
b
);
AND a1 (
w2,
a,
Cin
);
AND a2 (
w3,
b,
Cin
);
OR3 o0 ... | 7.610141 |
module Mux_8_to_1 (
result,
s,
in
);
output result;
input [2:0] s;
input [7:0] in;
wire n0, n1, n2, w0, w1, w2, w3, w4, w5, w6, w7;
INV i0 (
n0,
s[0]
);
INV i1 (
n1,
s[1]
);
INV i2 (
n2,
s[2]
);
AND4 a0 (
w0,
in[0],
n2,
n1,
... | 6.676712 |
module Decoder2to4 (
out,
in,
enable
);
input enable;
input [1:0] in;
output [3:0] out;
wire w1, w2;
INV inv1 (
w1,
in[0]
);
INV inv2 (
w2,
in[1]
);
AND3 and0 (
out[0],
w1,
w2,
enable
);
AND3 and1 (
out[1],
w2,
in[0],
... | 6.905676 |
module Decoder3to8 (
out,
in,
enable
);
input enable;
input [2:0] in;
output [7:0] out;
wire w1, w2, w3;
INV inv1 (
w1,
in[0]
);
INV inv2 (
w2,
in[1]
);
INV inv3 (
w3,
in[2]
);
AND4 and0 (
out[0],
w3,
w2,
w1,
enable
... | 6.943696 |
module Decoder5to32 (
out,
in,
enable
);
input enable;
input [4:0] in;
output [31:0] out;
wire [3:0] w;
Decoder2to4 dec0 (
w,
in[4:3],
enable
);
Decoder3to8 dec00 (
out[7:0],
in[2:0],
w[0]
);
Decoder3to8 dec01 (
out[15:8],
in[2:0],
w... | 6.51432 |
module Mux_32_to_1_32bit (
out,
s,
in
);
input [1023:0] in;
input [4:0] s;
output [31:0] out;
reg [31:0] out;
always @(in or s)
#6
case (s)
5'd0: out = in[31:0];
5'd1: out = in[63:32];
5'd2: out = in[95:64];
5'd3: out = in[127:96];
5'd4: out ... | 6.850438 |
module Main ();
reg A1, A0, B1, B0;
wire nA1, nA0, nB1, nB0, x, AG, BG, E, t1, t2, t3, t4, t5, t6;
initial begin
$dumpfile("Exp02.vcd");
$dumpvars;
A1 = 1'b0;
$display("------------------------------------------------------------");
$display(" Comparator");
$display... | 7.23232 |
module Main ();
reg A, B, Cin;
wire FSum, Fcout, HSum, Hcout, t1, t2, t3, t4;
initial begin
$dumpfile("Exp03.vcd");
$dumpvars;
A = 1'b0;
$display(
"---------------------------------------------------------------------------------------------------");
$display(" ... | 7.23232 |
module exp03_3_1 (
//////////// SW //////////
input [8:0] SW,
//////////// LED //////////
output [6:0] LEDR
// SW[3:0] : A
// SW[7:4] : B
// SW[8] : Cin
// LEDR[3:0] : result
// LEDR[4] : CF
// LEDR[5] : OF
// LEDR[6] : ZF
);
//=========================... | 6.730718 |
module exp03_3_2 (
//////////// KEY //////////
input [2:0] KEY,
//////////// SW //////////
input [7:0] SW,
//////////// LED //////////
output [6:0] LEDR
);
//=======================================================
// REG/WIRE declarations
//==========================================... | 7.390146 |
module Main ();
reg A, B, Bin;
wire FSub, Fbout, HSub, Hbout, t1, t2, t3, t4, nA;
initial begin
$dumpfile("Exp04.vcd");
$dumpvars;
A = 1'b0;
$display(
"-------------------------------------------------------------------------------------------------------------------------");
$displa... | 7.23232 |
module exp04_3_block (
//////////// KEY //////////
input [0:0] KEY,
//////////// SW //////////
input [1:0] SW,
//////////// LED //////////
output [1:0] LEDR
);
//=======================================================
// REG/WIRE declarations
//======================================... | 6.900984 |
module exp04_3_nonblock (
//////////// KEY //////////
input [0:0] KEY,
//////////// SW //////////
input [1:0] SW,
//////////// LED //////////
output [1:0] LEDR
);
//=======================================================
// REG/WIRE declarations
//===================================... | 6.906454 |
module FA (
v1,
v2,
vci,
vsum,
vco
);
input v1, v2, vci;
output vsum, vco;
wire t1, t2, t3, t4;
xor x1 (t1, v1, v2);
xor x2 (vsum, t1, vci);
and a1 (t2, v2, vci);
and a2 (t3, v1, vci);
and a3 (t4, v1, v2);
or o1 (vco, t2, t3, t4);
endmodule
| 7.053605 |
module FourBit_Adder (
num1,
num2,
carryIn,
sum,
carryOut
);
input [3:0] num1, num2;
input carryIn;
output [3:0] sum;
output carryOut;
wire btc1, btc2, btc3;
FA m5 (
num1[0],
num2[0],
carryIn,
sum[0],
btc1
);
FA m6 (
num1[1],
num2[1],
b... | 7.980763 |
module BCD_Adder (
No1,
No2,
BCDSum,
Overflow
);
input [3:0] No1, No2;
output [3:0] BCDSum;
output Overflow;
wire [3:0] tmp, tmp2;
wire bt1, bt2, bt3, bt4;
FourBit_Adder BCDA1 (
No1,
No2,
1'b0,
tmp,
bt1
);
or bo1 (bt2, tmp[2], tmp[1]);
and ba1 (bt3, tmp[3]... | 7.619207 |
module Main ();
reg [3:0] A, B, A_bcd, B_bcd;
reg mod;
wire [3:0] Bvalue, Ans, Ans_bcd;
wire tc1, tc2, tc3, tcout, tcout_bcd;
integer i, j;
initial begin
$dumpfile("Exp05.vcd");
$dumpvars;
mod = 1'b0;
A = 4'b0000;
B = 4'b0000;
A_bcd = 4'b0000;
B_bcd = 4'b0000;
$display("----... | 7.23232 |
module exp05_4_2 (
//////////// CLOCK //////////
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [0:0] LEDR,
//////////// Seg7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
... | 7.348016 |
module SRFlipFlop (
sin,
rin,
clkin,
qout,
qnout
);
input sin, rin, clkin;
output qout, qnout;
wire t1, t2;
nand n1 (t1, sin, clkin);
nand n2 (t2, rin, clkin);
nand n3 (qout, t1, qnout);
nand n4 (qnout, t2, qout);
endmodule
| 6.626768 |
module DFlipFlop (
Din,
clkin,
qout,
qnout
);
input Din, clkin;
output qout, qnout;
SRFlipFlop sr1 (
Din,
~Din,
clkin,
qout,
qnout
);
endmodule
| 7.170064 |
module MasterSlaveJK (
jin,
kin,
clkin,
qout,
qnout
);
input jin, kin, clkin;
output qout, qnout;
wire t1, t2;
JKFlipFlop jk1 (
jin,
kin,
clkin,
t1,
t2
);
JKFlipFlop jk2 (
t1,
t2,
~clkin,
qout,
qnout
);
endmodule
| 7.394512 |
module exp06_3_2 (
//////////// KEY //////////
input [0:0] KEY,
//////////// Seg7 //////////
output [6:0] HEX0,
output [6:0] HEX1
);
//=======================================================
// REG/WIRE declarations
//=======================================================
random_gene... | 7.961822 |
module exp07-demo(
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
o... | 7.242257 |
module exp07 (
//////////// CLOCK //////////
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
outp... | 7.06294 |
module exp07_4 (
//////////// CLOCK //////////
input CLOCK_50,
//////////// KEY //////////
input [1:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [1:0] LEDR,
//////////// Seg7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
ou... | 7.440549 |
module MUX (
s1,
s0,
Datain,
DataOut
);
input s1, s0;
input [3:0] Datain;
output DataOut;
assign DataOut=(s1==1'b1)?((s0==1'b1)?Datain[3]:Datain[2]):((s0==1'b1)?Datain[1]:Datain[0]);
endmodule
| 6.859117 |
module DEMUX (
s1,
s0,
DataIn,
d0,
d1,
d2,
d3
);
input s1, s0, DataIn;
output d0, d1, d2, d3;
assign d0 = (s1 == 1'b0) ? ((s0 == 1'b0) ? DataIn : 1'b0) : 1'b0;
assign d1 = (s1 == 1'b0) ? ((s0 == 1'b1) ? DataIn : 1'b0) : 1'b0;
assign d2 = (s1 == 1'b1) ? ((s0 == 1'b0) ? DataIn : 1'b0... | 6.697026 |
module Main ();
reg s1, s0, Dip;
reg [3:0] Dvin;
wire Dout, da0, da1, da2, da3;
integer i, j, k;
initial begin
$dumpfile("Exp08.vcd");
$dumpvars;
Dvin = 4'b0000;
s1 = 1'b1;
s0 = 1'b1;
Dip = 1'b0;
$display("------------------------------------------");
$display(" Mu... | 7.23232 |
module exp08_4 (
//////////// CLOCK //////////
// input CLOCK2_50,
// input CLOCK3_50,
// input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [0:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 /... | 7.438124 |
module exp09 (
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 //... | 6.792151 |
module exp09staticimg (
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// SW //////////
input [9:0] SW,
//////////// VGA //////////
output VGA_BLANK_N,
output [7:0] VGA_B,
output VGA_CLK,
output [7... | 6.549534 |
module exp09_3_1 (
//////////// CLOCK //////////
//input CLOCK2_50,
//input CLOCK3_50,
//input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [1:0] KEY,
//////////// VGA //////////
output reg VGA_BLANK_N,
output reg... | 6.766749 |
module exp09_3_2 (
//////////// CLOCK //////////
//input CLOCK2_50,
//input CLOCK3_50,
//input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [0:0] KEY,
//////////// VGA //////////
output VGA_BLANK_N,
output [7:0] V... | 6.864975 |
module exp10 (
//////////// CLOCK //////////
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
outp... | 7.988244 |
module exp10_test (
//////////// CLOCK //////////
//input CLOCK2_50,
//input CLOCK3_50,
//input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [0:0] KEY,
//////////// LED //////////
output [7:0] LEDR,
//////////// Seg7 /... | 7.491752 |
module exp11 (
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 //... | 7.123319 |
module exp11ch (
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 ... | 7.868621 |
module exp11_3 (
//////////// CLOCK //////////
//input CLOCK2_50,
//input CLOCK3_50,
//input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [0:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 ////... | 8.018931 |
module exp12 (
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 //... | 7.932492 |
module exp1_2bit_mux41 (
X0,
X1,
X2,
X3,
Y,
F
);
input [1:0] X0;
input [1:0] X1;
input [1:0] X2;
input [1:0] X3; //数据的输入端
input [1:0] Y; //选择输入
output reg [1:0] F; //作为输出
always @(X0 or X1 or X2 or X3 or Y)
case (Y)
0: begin
F[0] = X0[0];
F[1] = X0[1];... | 7.095002 |
module exp1_5 (
input clk,
input rst_n,
output [7:0] sq_c1,
output [7:0] sq_x,
output [1:0] sq_i,
output [7:0] sq_act
);
reg [7:0] c1;
reg [7:0] x;
reg [1:0] i;
reg [7:0] act;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
c1 <= 8'd0;
x <= 8'd0;
... | 6.743395 |
module exp1_6b (
input clk,
input rst_n,
output reg [7:0] c1,
output reg [7:0] x,
output reg [7:0] act1,
output reg [7:0] act2,
output reg [1:0] i
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
c1 <= 8'd0;
x <= 8'd0;
act1 <= 8'd0;
act2 <= 8'... | 7.026774 |
module exp1_6c (
input clk,
input rst_n,
output reg [7:0] c1,
output reg [7:0] x,
output reg [7:0] y,
output reg [7:0] act1,
output reg [7:0] act2,
output reg [1:0] i
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
c1 <= 8'd0;
x <= 8'd0;
y <= 8... | 6.737647 |
module exp1_7a (
input clk,
input rst_n,
output reg [7:0] c1,
output reg [7:0] x,
output reg [7:0] y,
output reg [7:0] act1,
output reg [7:0] act2,
output reg [1:0] i
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
c1 <= 8'd0;
x <= 8'd0;
y <= 8... | 6.673098 |
module exp1_7b (
input clk,
input rst_n,
output reg [7:0] c1,
output reg [7:0] x,
output reg [7:0] y,
output reg [7:0] act1,
output reg [7:0] act2,
output reg [1:0] i
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
c1 <= 8'd0;
x <= 8'd0;
y <= 8... | 6.726914 |
module exp1_8a (
input clk,
input rst_n,
output reg [7:0] c1, //完全使用步骤i,时钟计数c1没有用到
output reg [7:0] x,
output reg [7:0] y,
output reg [7:0] act1,
output reg [7:0] act2,
output reg [3:0] i
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
c1 <= 8'd0;
... | 7.048679 |
module exp1_8b (
input clk,
input rst_n,
output reg [7:0] c1,
output reg [7:0] x,
output reg [7:0] y,
output reg [7:0] act1,
output reg [7:0] act2,
output reg [3:0] i
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
c1 <= 8'd0;
x <= 8'd0;
y <= 8... | 6.587278 |
module exp1_8c (
input clk,
input rst_n,
output reg [7:0] c1,
output reg [7:0] x,
output reg [7:0] y,
output reg [7:0] act1,
output reg [7:0] act2,
output reg [3:0] i
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
c1 <= 8'd0;
x <= 8'd0;
y <= 8... | 6.710149 |
module exp20_top (
input clk,
input rst_n,
input write_req,
input [15:0] fifo_write_data,
output [4:0] a_left_sig,
output done_sig,
output [15:0] product
);
wire [15:0] u1_product;
wire u1_done_sig;
wire [4:0] u2_left_sig;
divider_interface i1 (
.clk(clk),
.rst_n(r... | 6.998659 |
module exp20_top_tb;
reg clk;
reg rst_n;
reg write_req;
reg [15:0] fifo_write_data;
wire [4:0] left_sig;
wire done_sig;
wire [15:0] product;
exp20_top t1 (
.clk(clk),
.rst_n(rst_n),
.write_req(write_req),
.fifo_write_data(fifo_write_data),
.a_left_sig(left_sig),
.do... | 6.532942 |
module exp22_top (
input clk,
input rst_n,
input key_in,
output pin_out
);
wire u1_q;
vir_key_module u1 (
.clk(clk),
.rst_n(rst_n),
.in_sig(key_in),
.q_sig(u1_q)
);
debounce_module u2 (
.CLK(clk),
.RST_n(rst_n),
.Pin_In(u1_q),
.Pin_Out(pin_... | 7.1603 |
module exp22_top_tb;
reg clk;
reg rst_n;
reg in_sig;
wire pin_out;
exp22_top u1 (
.clk(clk),
.rst_n(rst_n),
.key_in(in_sig),
.pin_out(pin_out)
);
initial begin
rst_n = 0;
#1000;
rst_n = 1;
clk = 0;
forever #25 clk = ~clk;
end
/*******************... | 6.515111 |
module exp2msTB ();
wire TFF_out;
wire [15:0] duration;
wire [7:0] cnt;
reg JKReset, enable, clk_regulator;
reg [7:0] fset_max, fset_min, fset_ref;
wire clk_divider, inc, dec;
wire [7:0] adjustedLoad;
wire [7:0] set_period;
reg rst;
ring_oscillator RNGO (
rst,
clk_divider
); //20MH... | 7.637567 |
module exp3_adder (
A,
B,
CIN,
RESULT,
CARRY,
OVERFLOW,
ZERO
);
input [3:0] A;
input [3:0] B;
input CIN;
output reg [3:0] RESULT;
output reg CARRY, OVERFLOW, ZERO;
reg [3:0] BC;
parameter n = 4;
always @(*) begin
BC = ({n{CIN}} ^ B);
{CARRY, RESULT} = A + BC + CIN;
... | 7.140561 |
module sipo (
in,
out,
clk
);
input in, clk;
output [3:0] out;
dff i1 (
in,
clk,
out[0]
);
dff i2 (
out[0],
clk,
out[1]
);
dff i3 (
out[1],
clk,
out[2]
);
dff i4 (
out[2],
clk,
out[3]
);
endmodule
| 6.535782 |
module EXP4_1 (
input clk,
input in_data,
input en,
output out_u1,
output out_u2,
output out_1,
output out_2
);
Block b1 (
.clk(clk),
.in_data(in_data),
.en(en),
.out_1(out_1),
.out_2(out_2)
);
UnBlock ub1 (
.clk(clk),
.in_data(in_data),
... | 6.780562 |
module exp5 (
a,
b,
c,
x
);
input a, b, c;
output x;
wire w1, w2;
not n1 (w1, a);
or o1 (w2, b, c);
nand n2 (x, w1, w2);
endmodule
| 6.871871 |
module exp5_4_1 (
input CLK,
input pause,
input en,
input clr,
output [6:0] HEX0,
output [6:0] HEX1,
output ending
);
wire CLK_div;
div_N A (
CLK,
CLK_div
);
counter B (
CLK_div,
en,
pause,
clr,
HEX0,
HEX1,
ending
);
endmodule
| 6.737377 |
module exp5_4_2 (
input CLK,
input start,
input clr,
input adj_sec,
input adj_min,
input adj_hou,
input pause,
input set,
output timing,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5
);
wire ... | 6.678559 |
module exp5_env (
input clk,
input rst_n,
input start_sig,
output done_sig,
output write_en,
output [3:0] ram_addr,
output [7:0] rom_data
);
wire [3:0] rom_addr;
control_module u1 (
.clk(clk),
.rst_n(rst_n),
.start_sig(start_sig),
.done_sig(done_sig),
.... | 6.695221 |
module exp5_env_tb ();
reg clk;
reg rst_n;
initial begin
clk = 1;
forever #5 clk = ~clk;
end
initial begin
rst_n = 0;
#1000 rst_n = 1;
end
/*************************/
reg start_sig;
wire done_sig;
wire write_en;
wire [3:0] ram_addr;
wire [7:0] rom_data;
exp5_env u1 (
... | 6.539693 |
module Adder32bit (
out,
a,
b
);
input [31:0] a, b;
output [31:0] out;
assign #50 out = a + b;
// implementation details are left to the student
endmodule
| 8.498695 |
module SignExtend (
out,
in
);
input [15:0] in;
output [31:0] out;
assign out = {{16{in[15]}}, in};
// implementation details are left to the student
endmodule
| 7.619369 |
module Comparator32bit (
equal,
a,
b
);
input [31:0] a, b;
output equal;
reg equal;
always @(a or b)
#10
if (a == b) equal = 1'b1;
else equal = 1'b0;
// implementation details are left to the student
endmodule
| 6.533766 |
module ShiftLeft26_by2 (
out,
in
);
input [25:0] in;
output [27:0] out;
assign out = in << 2;
// implementation details are left to the student
endmodule
| 7.324568 |
module ShiftLeft32_by2 (
out,
in
);
input [31:0] in;
output [31:0] out;
assign out = in << 2;
// implementation details are left to the student
endmodule
| 8.132664 |
module Mux_3_to_1_5bit (
out,
s,
i2,
i1,
i0
);
input [4:0] i2, i1, i0;
input [1:0] s;
output [4:0] out;
reg [4:0] out;
always @(s or i0 or i1 or i2)
#6
case (s)
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
endcase
/*assign #6 out=(i0[4:0]& ~... | 7.282825 |
module Mux_3_to_1_32bit (
out,
s,
i2,
i1,
i0
);
input [31:0] i2, i1, i0;
input [1:0] s;
output [31:0] out;
reg [31:0] out;
always @(s or i0 or i1 or i2)
#6
case (s)
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
endcase
/*assign #6 out= ... | 7.771723 |
module Mux_2_to_1_32bit (
out,
s,
i1,
i0
);
input [31:0] i1, i0;
input s;
output [31:0] out;
reg [31:0] out;
always @(s or i0 or i1)
#6
case (s)
1'b0: out = i0;
1'b1: out = i1;
endcase
//assign #6 out=(i0[31:0]& ~s)|(i1[31:0]& s);
// implementation details... | 7.846533 |
module exp6_2 (
clk,
HEX0,
HEX1
);
input clk;
output reg [6:0] HEX0;
output reg [6:0] HEX1;
reg [7:0] data_out = 8'b00000000;
integer i;
always @(posedge clk) begin
if (data_out == 8'b00000000) data_out = 8'b10000000;
else data_out = {data_out[4] ^ data_out[3] ^ data_out[2] ^ data_out[0]... | 6.551744 |
module exp6_env (
input clk,
input rst_n,
input start_sig,
output done_sig,
output write_en,
output [3:0] ram_addr,
output [7:0] rom_data
);
wire [3:0] rom_addr;
wire u1_write_en;
wire [3:0] u1_ram_addr;
control_module u1 (
.clk(clk),
.rst_n(rst_n),
.start_sig(... | 7.017359 |
module IFID (
Q,
D,
clk,
reset,
enable
);
input clk, reset, enable;
input [63:0] D;
output [63:0] Q;
ProgramCounter IFIDREG1 (
Q[31:0],
D[31:0],
clk,
reset,
enable
);
ProgramCounter IFIDREG2 (
Q[63:32],
D[63:32],
clk,
reset,
en... | 6.557134 |
module Comparator5bit (
equal,
a,
b
);
input [4:0] a, b;
output equal;
wire w0, w1, w2, w3, w4, w5;
XNOR x0 (
w0,
a[0],
b[0]
);
XNOR x1 (
w1,
a[1],
b[1]
);
XNOR x2 (
w2,
a[2],
b[2]
);
XNOR x3 (
w3,
a[3],
b[3]
);
... | 7.065065 |
module exp8 (
clk,
clrn,
ps2_clk,
ps2_data,
ready,
overflow,
ctrl_flag,
capslock_flag,
shift_flag,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input clk, clrn, ps2_clk, ps2_data;
output overflow; // fifo overflow
output [6:0] HEX0;
output [6:0] HEX1;
out... | 6.54238 |
module HazardDetectionUnit (
Flush,
pcsrc,
takenbranch
);
output Flush;
input pcsrc, takenbranch;
OR o1 (
Flush,
pcsrc,
takenbranch
);
// implementation details are left to the student
endmodule
| 6.580064 |
module Exp9_Timing (
tb_trigger,
tb_status
);
// Port Declarations
input [1:0] tb_trigger;
output [1:0] tb_status;
// Begin Process Infrastructure Declaration
reg [1:0] tb_status;
integer tb_transaction_run_count;
// Update Status Loop
always @(tb_trigger)
if ((tb_trigger === `TB_ONCE) || ... | 7.127519 |
module ExpAccTB ();
reg start, read, clk, rst;
wire done, ready;
wire [17:0] q;
wire [ 2:0] usedw;
ExpAcc acc (
.done(done),
.start(start),
.clk(clk),
.rst(rst),
.read(read),
.ready(ready),
.q(q),
.usedw(usedw)
);
always #5 clk = ~clk;
initial begin
... | 6.725636 |
module expaddtoresult_mux (
output reg [7:0] mux_out,
input wire [7:0] in_result,
//select lines
input wire underflow,
input wire overflow
);
always @(*) begin
case ({
underflow, overflow
})
// neither overflow nor underflow has occured.
00: mux_out = in_result;
... | 6.752439 |
module expand3x3_ram (
address,
clock,
data,
wren,
q);
input [8:0] address;
input clock;
input [39:0] data;
input wren;
output [39:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [39:0] sub_wire0;
wir... | 6.616045 |
module expand8bit_tb;
reg [32 * 32 - 1:0] data_in;
reg [2:0] addr;
wire [128 * 8 - 1:0] data_out;
expand_to_8bit inst (
.data_in(data_in),
.addr(addr),
.data_out(data_out)
);
initial begin
data_in = {64{8'b00110011, 8'b10101010}};
addr = 0;
#5 addr = 4;
#5 addr = 5;
... | 6.583729 |
module expanded_ifft_top (
pf_re,
pf_im,
pf_index,
pf_en,
ifft_oaddr,
ifft_ore,
ifft_oim,
ifft_oen,
iclk,
rst_n
);
`include "FFT.h"
input [OREAL_WIDTH-1:0] pf_re;
input [OIMGN_WIDTH-1:0] pf_im;
input [IFFT_STAGE-1:0] pf_index;
input pf_en;
output [OREAL_WIDTH-1:0] ... | 6.552646 |
module expandWidth #(
parameter IWIDTH = 8,
parameter OWIDTH = 12
) (
input wire [IWIDTH-1:0] I,
output wire [OWIDTH-1:0] O
);
wire signBit;
assign signBit = I[IWIDTH-1];
assign O = {{OWIDTH - IWIDTH{signBit}}, I};
endmodule
| 8.060731 |
module expand_add (
clk_i,
rst_n_i,
expand_1_i,
expand_2_i,
expand_sum_o,
add_en_i
);
//----------------------------------------------------------------------------------------------------------------------
// Global constant and function headers
//-------------------------------------... | 7.397139 |
module expand_key ();
s_box key_s1 ();
function [32:1] g_func(input [32:1] word, input [8:1] rcon);
reg [32:1] tf;
reg [32:1] sub;
reg [32:1] temp;
//byte subsitution
begin
temp = 32'h00000000;
tf[24:1] = word[32:9];
tf[32:25] = word[8:1];
sub[32-:8] = key_s1.s_box_fu... | 7.430304 |
module expand_to_8bit (
input wire [32 * 32 - 1:0] data_in,
input wire [2:0] addr,
output reg [128 * 8 - 1:0] data_out
);
reg [7:0] i;
always @(*) begin
for (i = 0; i <= 127; i = i + 1) begin
data_out[8*(addr*128+i)+7-:8] <= {data_in[addr*128+i], 7'b0000000};
end
end
endmodule
| 6.974681 |
module expansion_gpio
module ExpansionGPIO(
input wire clk_12MHz,
inout wire [31:0] databus,
output tri [2:0] reg_size, /* Register size (in bytes), to set command reply size. */
input wire [7:0] register_addr,
input wire rw, /* 0 = write, 1 = read. */
input wire select, /* Rising edge writes or hold high to rea... | 9.297253 |
module ExpansionBox (
DataIn,
DataOut
);
input [31:0] DataIn;
output [47:0] DataOut;
assign DataOut[0] = DataIn[31];
assign DataOut[1] = DataIn[0];
assign DataOut[2] = DataIn[1];
assign DataOut[3] = DataIn[2];
assign DataOut[4] = DataIn[3];
assign DataOut[5] = DataIn[4];
assign DataOut[... | 7.335937 |
module performs the expansion D-Box logic
module Expansion_D_Box(
input [31:0] i_data,
output [47:0] o_expanded_data
);
// 1st byte
assign o_expanded_data[0] = i_data[31];
assign o_expanded_data[1] = i_data[0];
assign o_expanded_data[2] = i_data[1];
assign o_expanded_data[3] = i_data[2];
assign o_expanded_d... | 7.634754 |
module expansion_function (
in_block,
out_block
);
input [31:0] in_block;
output [47:0] out_block;
assign out_block[0] = in_block[31];
assign out_block[1] = in_block[0];
assign out_block[2] = in_block[1];
assign out_block[3] = in_block[2];
assign out_block[4] = in_block[3];
assign out_blo... | 6.998452 |
module expD (
input [ 6:2] ExcCodeF,
input [31:0] IRD,
output [ 6:2] ExcCodeE
);
`include "header.v"
`include "expint.v"
wire RI_exp;
assign ExcCodeE = (RI_exp) ? `ExcCode_ri : ExcCodeF;
ctrl riD (
.instr (IRD),
.RI_exp(RI_exp)
);
endmodule
| 6.596596 |
module ExpEngTB ();
reg start, clk, rst;
reg [15:0] inp;
wire done;
wire [1:0] intpart;
wire [15:0] fracpart;
exponential exp (
.x(inp),
.start(start),
.clk(clk),
.rst(rst),
.done(done),
.intpart(intpart),
.fracpart(fracpart)
);
always #5 clk = ~clk;
initi... | 6.714199 |
module mux(input [3:0]i, [1:0]s, output y);
assign y = s[1]?(s[0]?i[3]:i[2]):(s[0]?i[1]:i[0]);
endmodule
| 7.218794 |
module mux_tb;
reg [3:0] i; // Input of mux
reg [1:0] s; //select line of mux
wire y; // output of mux
integer x = 0; // integer to count error
mux uut (
i,
s,
y
); //instantiation
initial begin
repeat (10) begin //test 10 times
i = $random; // random input (4 bits)
... | 7.046438 |
module fa (
input a,
b,
c,
output s,
cy
);
assign s = a ^ b ^ c;
assign cy = a & b | b & c | a & c;
endmodule
| 7.001699 |
module tb ();
reg a, b, c; //inputs
wire s, cy; //outputs
integer x = 0; //error counter
fa dut (
a,
b,
c,
s,
cy
); // instantiation
initial begin
repeat (100) begin //100 tests
{a, b, c} = $random; //random input stimuli
#1; //delay to see dut output
... | 7.002324 |
module bcd_to_binary (
input [7:0] in,
output [7:0] out
);
assign out = in[7:4] * 10 + in[3:0];
endmodule
| 7.167517 |
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