code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module testNORgate;
// ------------------------- dados locais
reg [0:7] a; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
NORgate NOR1 (
s,
a[0:7]
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultanea... | 7.487819 |
module orgate4 (
output s,
input p,
input q,
input r,
input t
);
wire s1, s2;
orgate OR1 (
s1,
p,
q
);
orgate OR2 (
s2,
r,
t
);
orgate OR3 (
s,
s1,
s2
);
endmodule
| 6.963319 |
module testnorgateByte;
// ------------------------- dados locais
reg [7:0] count;
wire s; // definir conexao (fio)
// ------------------------- instancia
norgateByte OR7 (
s,
count
);
// ------------------------- preparacao
initial begin : start
// valores iniciais
count = 0... | 6.991246 |
module orgate4 (
output s,
input p,
input q,
input r,
input t
);
wire s1, s2;
orgate OR1 (
s1,
p,
q
);
orgate OR2 (
s2,
r,
t
);
orgate OR3 (
s,
s1,
s2
);
endmodule
| 6.963319 |
module testorgateByte;
// ------------------------- dados locais
reg [7:0] count;
wire s; // definir conexao (fio)
// ------------------------- instancia
orgateByte OR7 (
s,
count
);
// ------------------------- preparacao
initial begin : start
// valores iniciais
count = 0;
... | 7.198089 |
module men4b (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
bitMen bM1 (
saida[0],
addr,
rw,
clk,
clr,
dt[0]
);
bitMen bM2 (
saida[1],
addr,
rw,
clk,
clr,
dt[1]
);
bitMen bM3 (
... | 6.732558 |
module testnorgate;
reg a, b;
wire s;
norgate NOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0; // valor inicial
end
initial begin : main
$display("Exercicio 2 - Silvino Henrique Santos de Souza - 412773");
$display("Test NOR Gate:");
$display("\n ~(a | b) = s... | 6.695863 |
module men4b (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
bitMen bM1 (
saida[0],
addr,
rw,
clk,
clr,
dt[0]
);
bitMen bM2 (
saida[1],
addr,
rw,
clk,
clr,
dt[1]
);
bitMen bM3 (
... | 6.732558 |
module menRam (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
wire addr2;
wire [3:0] saida1;
wire [3:0] saida2;
not N2 (addr2, addr);
men4b m4b1 (
saida1,
addr2,
rw,
clk,
clr,
dt
);
men4b m4b2 (
saida2,
... | 6.997874 |
module mux4b (
output [3:0] saida,
input [3:0] p,
input [3:0] q,
input select
);
mux Mx2 (
saida[0],
p[0],
q[0],
select
);
mux Mx3 (
saida[1],
p[1],
q[1],
select
);
mux Mx4 (
saida[2],
p[2],
q[2],
select
);
mux Mx5 (
... | 6.939919 |
module mux (
output saida,
input p,
input q,
input select
);
wire selectN;
wire s1, s2;
not N3 (selectN, select);
and A3 (s1, p, selectN);
and A4 (s2, q, select);
or O1 (saida, s1, s2);
endmodule
| 7.812393 |
module latch_SR_NAND (
q,
q_bar,
pr,
cl,
r,
s
);
input r, s, pr, cl;
output q, q_bar;
nand NAND1 (q, pr, s, q_bar);
nand NAND2 (q_bar, cl, r, q);
endmodule
| 6.893422 |
module Exercicio2;
wire q, q_bar;
reg s, r, pr, cl;
latch_SR_NAND LSR_NAND (
q,
q_bar,
cl,
pr,
s,
r
);
initial begin : start
s = 0;
r = 0;
cl = 0;
pr = 0;
end
initial begin : main
$display("Guia 10_02 - Marcia Cibele Martins Carneiro - 404591");... | 6.832607 |
module xnorgate (
output s,
input p,
input q
);
assign s = ~(p ^ q);
endmodule
| 6.74222 |
module testxnorgate;
reg a, b;
wire s;
xnorgate XNOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0; // valor inicial
end
initial begin : main
$display("Exercicio 3 - Silvino Henrique Santos de Souza - 412773");
$display("Test XNOR Gate:");
$display("\n ~(a ^ b)... | 7.028584 |
module EXERCICIO6;
// ------------------------- definir dados
reg [7:0] a;
wire [7:0] ac;
wire [7:0] ac2;
assign ac = ~a;
assign ac2 = ac + 1;
// ------------------------- parte principal
initial begin
$display("\nExercicio0036 - Jose Ferreira Reis Fonseca - 405808");
$display("Test number s... | 7.232675 |
module men4b (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
bitMen bM1 (
saida[0],
addr,
rw,
clk,
clr,
dt[0]
);
bitMen bM2 (
saida[1],
addr,
rw,
clk,
clr,
dt[1]
);
bitMen bM3 (
... | 6.732558 |
module men8b (
output [7:0] saida,
input addr,
input rw,
input clk,
input clr,
input [7:0] dt
);
men4b m4b1 (
saida[3:0],
addr,
rw,
clk,
clr,
dt[3:0]
);
men4b m4b2 (
saida[7:4],
addr,
rw,
clk,
clr,
dt[7:4]
);
endmodu... | 6.933512 |
module nandgate (
output s,
input p,
input q
);
assign s = ~p | ~q;
endmodule
| 7.298658 |
module men4b (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
bitMen bM1 (
saida[0],
addr,
rw,
clk,
clr,
dt[0]
);
bitMen bM2 (
saida[1],
addr,
rw,
clk,
clr,
dt[1]
);
bitMen bM3 (
... | 6.732558 |
module men4b2a (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
wire addr2;
wire [3:0] saida1;
wire [3:0] saida2;
not N2 (addr2, addr);
men4b m4b1 (
saida1,
addr2,
rw,
clk,
clr,
dt
);
men4b m4b2 (
saida2,
... | 7.13395 |
module mux4b (
output [3:0] saida,
input [3:0] p,
input [3:0] q,
input select
);
mux Mx2 (
saida[0],
p[0],
q[0],
select
);
mux Mx3 (
saida[1],
p[1],
q[1],
select
);
mux Mx4 (
saida[2],
p[2],
q[2],
select
);
mux Mx5 (
... | 6.939919 |
module mux (
output saida,
input p,
input q,
input select
);
wire selectN;
wire s1, s2;
not N3 (selectN, select);
and A3 (s1, p, selectN);
and A4 (s2, q, select);
or O1 (saida, s1, s2);
endmodule
| 7.812393 |
module demux (
output s1,
output s2,
input in,
input select
);
wire selectN;
not N4 (selectN, select);
and A5 (s1, in, selectN);
and A6 (s2, in, select);
endmodule
| 6.725201 |
module testnorgate;
reg a, b;
wire s;
norgate NOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0; // valor inicial
end
initial begin : main
$display("Exercicio 5 - Silvino Henrique Santos de Souza - 412773");
$display("Test NOR de Morgan Gate:");
$display("\n ~a... | 6.695863 |
module men4b (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
bitMen bM1 (
saida[0],
addr,
rw,
clk,
clr,
dt[0]
);
bitMen bM2 (
saida[1],
addr,
rw,
clk,
clr,
dt[1]
);
bitMen bM3 (
... | 6.732558 |
module men4b2a (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
wire addr2;
wire [3:0] saida1;
wire [3:0] saida2;
not N2 (addr2, addr);
men4b m4b1 (
saida1,
addr2,
rw,
clk,
clr,
dt
);
men4b m4b2 (
saida2,
... | 7.13395 |
module mux8b (
output [7:0] saida,
input [7:0] p,
input [7:0] q,
input select
);
mux4b Mx41 (
saida[3:0],
p[3:0],
q[3:0],
select
);
mux4b Mx42 (
saida[7:4],
p[7:4],
q[7:4],
select
);
endmodule
| 7.301408 |
module mux4b (
output [3:0] saida,
input [3:0] p,
input [3:0] q,
input select
);
mux Mx2 (
saida[0],
p[0],
q[0],
select
);
mux Mx3 (
saida[1],
p[1],
q[1],
select
);
mux Mx4 (
saida[2],
p[2],
q[2],
select
);
mux Mx5 (
... | 6.939919 |
module mux (
output saida,
input p,
input q,
input select
);
wire selectN;
wire s1, s2;
not N3 (selectN, select);
and A3 (s1, p, selectN);
and A4 (s2, q, select);
or O1 (saida, s1, s2);
endmodule
| 7.812393 |
module demux (
output s1,
output s2,
input in,
input select
);
wire selectN;
not N4 (selectN, select);
and A5 (s1, in, selectN);
and A6 (s2, in, select);
endmodule
| 6.725201 |
module xorgate (
output s,
input p,
input q
);
assign s = (~p) & q | p & (~q);
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0; // valor inicial
end
initial begin : main
$display("Exercicio 6 - Silvino Henrique Santos de Souza - 412773");
$display("Test XOR Gate:");
$display("\na ~| b = s\n"... | 6.716539 |
module men4b (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
bitMen bM1 (
saida[0],
addr,
rw,
clk,
clr,
dt[0]
);
bitMen bM2 (
saida[1],
addr,
rw,
clk,
clr,
dt[1]
);
bitMen bM3 (
... | 6.732558 |
module men8b (
output [7:0] saida,
input addr,
input rw,
input clk,
input clr,
input [7:0] dt
);
men4b m4b1 (
saida[3:0],
addr,
rw,
clk,
clr,
dt[3:0]
);
men4b m4b2 (
saida[7:4],
addr,
rw,
clk,
clr,
dt[7:4]
);
endmodu... | 6.933512 |
module men16b (
output [15:0] saida,
input addr,
input rw,
input clk,
input clr,
input [15:0] dt
);
men8b m8b1 (
saida[7:0],
addr,
rw,
clk,
clr,
dt[7:0]
);
men8b m8b2 (
saida[15:8],
addr,
rw,
clk,
clr,
dt[15:8]
);
en... | 6.893017 |
module xnorgate (
output s,
input p,
input q
);
assign s = p & q | (~p) & (~q);
endmodule
| 6.74222 |
module testxnorgate;
reg a, b;
wire s;
xnorgate XNOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0; // valor inicial
end
initial begin : main
$display("Exercicio 7 - Silvino Henrique Santos de Souza - 412773");
$display("Test XNOR Gate:");
$display("\na ~^ b = ... | 7.028584 |
module mux8b (
output [7:0] saida,
input [7:0] p,
input [7:0] q,
input select
);
mux4b Mx41 (
saida[3:0],
p[3:0],
q[3:0],
select
);
mux4b Mx42 (
saida[7:4],
p[7:4],
q[7:4],
select
);
endmodule
| 7.301408 |
module mux4b (
output [3:0] saida,
input [3:0] p,
input [3:0] q,
input select
);
mux Mx2 (
saida[0],
p[0],
q[0],
select
);
mux Mx3 (
saida[1],
p[1],
q[1],
select
);
mux Mx4 (
saida[2],
p[2],
q[2],
select
);
mux Mx5 (
... | 6.939919 |
module mux (
output saida,
input p,
input q,
input select
);
wire selectN;
wire s1, s2;
not N3 (selectN, select);
and A3 (s1, p, selectN);
and A4 (s2, q, select);
or O1 (saida, s1, s2);
endmodule
| 7.812393 |
module demux (
output s1,
output s2,
output s3,
output s4,
input in,
input [1:0] select
);
wire [1:0] selectN;
not N4 (selectN[0], select[0]);
not N5 (selectN[1], select[1]);
and A5 (s1, in, selectN[1], selectN[0]);
and A6 (s2, in, selectN[1], select[0]);
and A7 (s3, in, select[1], s... | 6.725201 |
module men4b (
output [3:0] saida,
input addr,
input rw,
input clk,
input clr,
input [3:0] dt
);
bitMen bM1 (
saida[0],
addr,
rw,
clk,
clr,
dt[0]
);
bitMen bM2 (
saida[1],
addr,
rw,
clk,
clr,
dt[1]
);
bitMen bM3 (
... | 6.732558 |
module men8b (
output [7:0] saida,
input addr,
input rw,
input clk,
input clr,
input [7:0] dt
);
men4b m4b1 (
saida[3:0],
addr,
rw,
clk,
clr,
dt[3:0]
);
men4b m4b2 (
saida[7:4],
addr,
rw,
clk,
clr,
dt[7:4]
);
endmodu... | 6.933512 |
module testandgate;
reg a, b, c;
wire s;
andgate AND1 (
s,
a,
b,
c
);
initial begin : start
a = 0;
b = 0;
c = 0; // valor inicial
end
initial begin : main
$display("Exercicio 8 - Silvino Henrique Santos de Souza - 412773");
$display("Test AND Gate com 3 entr... | 6.553783 |
module simpleandgate (
output s,
input p,
input q
);
assign s = p & q;
endmodule
| 7.447048 |
module testandgate;
reg a, b, c;
wire s;
andgate AND2 (
s,
a,
b,
c
);
initial begin : start
a = 0;
b = 0;
c = 0; // valor inicial
end
initial begin : main
$display("Exercicio 9 - Silvino Henrique Santos de Souza - 412773");
$display("Test AND Gate com 3 entr... | 6.553783 |
module notgate (
output s,
input p,
input r
);
assign s = ~p & ~r; // criar vinculo permanente
// (dependencia)
endmodule
| 7.575943 |
module testnotgate;
// ------------------------- dados locais
reg a;
reg b; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
notgate NOT1 (
s,
a,
b
);
// --------------------... | 7.480879 |
module complemento1;
// definir dados
reg [7:0] a;
reg [7:0] sa;
// ------------------------- parte principal
initial begin
$display("Exercicio Extra 1 - Ana Carolina - 449517");
$display("Exercicio 4 - Complemento 1 ");
a = 8'b00100101;
sa = ~a;
$display("se = %d = %5b", sa, sa);
... | 6.675635 |
module testzero;
//------------------ dados locais
reg [7:0] a;
wire s;
//------------ instancia
zero ZERO (
s,
a
);
initial begin : start
a = 8'b0000_0000;
end
//------- parte principal
initial begin : main
$display("Exercicio 11 - Ana Carolina - 449517");
$display("Test... | 7.449597 |
module testum;
//------------------ dados locais
reg [7:0] a;
wire s;
//------------ instancia
um UM (
s,
a
);
initial begin : start
a = 8'b0000_0000;
end
//------- parte principal
initial begin : main
$display("Exercicio 12 - Ana Carolina - 449517");
$display("Test Zero"... | 7.146202 |
module xnorgate (
a,
b,
c,
d,
s1
);
output s1;
input a0, a1, b0, b1;
assign s1 = ~(a0 | a1 | b0 | b1); // E' SO' UMA PORTA nor
endmodule
| 6.74222 |
module xorgate (
s1,
a,
b,
c
);
output s1;
input a, b, c;
assign s1 = (a | b | c);
endmodule
| 7.421731 |
module segundaparte;
reg a, b, c;
wire s0, s1;
xorgate XOR1 (
s1,
a,
b,
c
);
//usando o display
initial begin
$display("exerciciogia_04");
$display("xorgate");
$display("\na |b =s1 \n");
a = 0;
b = 0;
c = 0;
#1 $display("%b |%b|%b=%b ", a, b, c, s1);
a... | 6.59414 |
module xorgate (
s0,
a,
b
);
output s0;
input a, b;
assign s0 = (a | b);
endmodule
| 7.421731 |
module segundaparte;
reg a, b;
wire s1;
andgate AND1 (
s1,
a,
b
);
//usando display
initial begin
$display("exercicioguia_04_02");
$display("andgate");
$display("\na & b=s1 \n ");
a = 0;
b = 0;
#1 $display("%b & %b =%b ", a, b, s1);
a = 0;
b = 1;
#1 $di... | 6.59414 |
module notgate (
s1,
b
);
output s1;
input b;
assign s1 = ~(&b);
endmodule
| 7.575943 |
module terceiraparte;
reg b;
wire s1;
notgate NOT1 (
s1,
b
);
//usando o display
initial begin
$display("exercicioguia_04_02");
$display("notgate");
$display("\na ~ b=s1\n");
b = 0;
#1 $display("%b~ =%b", b, s1);
b = 1;
#1 $display("%b~ =%b", b, s1);
end
endmodule
... | 7.040416 |
module xorgate (
s0,
a,
b
);
output s0;
input a, b;
assign s0 = (a | b);
endmodule
| 7.421731 |
module terceiro;
reg a, b;
wire s0;
xorgate XOR3 (
s0,
a,
b
);
//usando display
initial begin
$display("exercicio_05_03");
$display("xorgate");
$display("\na | b=s0 \n");
a = 0;
b = 0;
#1 $display("%b |%b=%b", a, b, s0);
a = 0;
b = 1;
#1 $display("%b |%... | 7.312557 |
module test_and
module test_and;
reg[0:0]a;
reg[1:0]b;
//parte principal
//iniciando os testes
initial begin
$display("exercicioguia_04_03");
$display ("module test_and ");
a=1;
b=1;
$display ("\nPositive value ");
$display ("a=%b =1b",a,a);
$display ("a=%b =1b",b,b);
$display ("\nNegative value ");
$d... | 7.615071 |
module xorgate (
s,
a,
b,
c,
d
); // DESNECESSARIO, PODE TIRAR
output s;
input a, b, c, d;
assign s = ~(a | b | c | d);
endmodule
| 7.421731 |
module primparte;
reg q, p;
wire s1;
norgate nor1 (
s1,
q,
p
); // O FLIP-FLOP PRECISARA' DE MAIS QUE ISSO
initial begin
$display("primparte");
$display("norgate");
$display("\na |b=s1\n");
q = 0;
p = 0;
$display("%b|%b=%b", q, p, s1);
q = 0;
p = 1;
#1 $d... | 6.965372 |
module norgate_2 (
s2,
q,
p
);
output s2;
input q, p;
assign s2 = ~(q | p);
endmodule
| 6.813728 |
module segparte;
reg q, p;
wire s2;
norgate_2 nor2 (
s2,
q,
p
);
initial begin
$display("segparte");
$display("norgate_2");
$display("\na |b=s2\n");
q = 0;
p = 0;
$display("%b|%b=%b", q, p, s2);
q = 0;
p = 1;
#1 $display("%b|%b=%b", q, p, s2);
q = 1;
... | 6.798597 |
module test_base_01;
// ------------------------- definir dados
reg [4:0] a;
reg [4:0] b;
reg [2:0] c;
reg [3:0] d;
reg [4:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicios - Miguel Sousa - 463985");
$display("Test number system");
a = 3 + 14;
b = 3 ... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [4:0] a;
reg [4:0] b;
reg [4:0] c;
reg [4:0] d;
reg [3:0] e;
reg [5:0] f;
// ------------------------- parte principal
initial begin
$display("Exercicios01 - Milton costa teles da silva - 002751");
$display("Test number syst... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [6:0] a;
reg [5:0] b;
reg [3:0] c;
reg [6:0] d;
reg [9:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicios02 - Milton costa teles da silva - 002751");
$display("Test number system");
a = 6... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [5:0] a;
reg [4:0] b;
reg [4:0] c;
reg [5:0] d;
reg [4:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicios03 - Milton costa teles da silva - 002751");
$display("Test number system");
a = 6... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [7:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicios04 - Milton costa teles da silva - 002751");
$display("Test number system");
a = 6... | 6.932753 |
module exercicio01 (
signal,
clock
);
input clock;
output signal;
reg signal;
initial begin
signal = 1'b0;
end
always begin
#6 signal = ~signal;
end
endmodule
| 6.619421 |
module exercicio02 (
signal,
clock
);
input clock;
output signal;
reg signal;
initial begin
signal = 1'b0;
end
always begin
#48 signal = ~signal;
end
endmodule
| 6.784138 |
module halfAdder (
s1,
s0,
a,
b
);
output s1, s0;
input a, b;
wire x, y;
or OR1 (x, a, b);
and AND1 (s1, a, b);
not NOT1 (y, s1);
and AND2 (s0, x, y);
endmodule
| 7.256462 |
module halfAdder (
s1,
s0,
a,
b
);
output s1, s0;
input a, b;
wire x, y, k, z, w, q;
nand NAND1 (y, a, a);
nand NAND2 (z, b, b);
nand NAND3 (k, y, z); // porta or
nand NAND4 (x, a, b);
nand NAND5 (s1, x, x); // porta and
nand NAND6 (w, s1, s1); // porta not
nand NAND7 (q, k, w... | 7.256462 |
module meiaDiferenca (
s1,
s0,
a,
b
);
output s1, s0;
input a, b;
wire x;
not NOT1 (x, a);
and AND1 (s1, b, x);
xor XOR1 (s0, a, b);
endmodule
| 8.132121 |
module exercicio01 (
signal,
clock
);
input clock;
output signal;
reg signal;
initial begin
signal = 1'b0;
end
always begin
#6 signal = ~signal;
end
endmodule
| 6.619421 |
module exercicio02 (
signal,
clock
);
input clock;
output signal;
reg signal;
initial begin
signal = 1'b0;
end
always begin
#48 signal = ~signal;
end
endmodule
| 6.784138 |
module soma_completa (
s0,
s1,
p,
q,
t
);
output s0, s1;
input p, q, t;
wire temp1, temp2, temp3;
meia_soma MS1 (
temp1,
temp2,
p,
q
);
meia_soma MS2 (
s0,
temp3,
temp1,
t
);
or OR1 (s1, temp2, temp3);
endmodule
| 7.237842 |
module andgate ( output s,
input p,
input q
imput r
imput j);
assign s =(p & q)&(r&j);
endmodule
| 7.581227 |
module testandgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultane... | 6.553783 |
module RAM1X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire [3:0] q;
wire [3:0] qnot;
wire [3:0] n;
wire w;
not N0 (n[0], data[3]);
not N1 (n[1], data[2]);
not N2 (n[2], data[1]);
not N3 (n[... | 6.842395 |
module DMUX3Bit (
s,
address,
data
);
output [7:0] s;
input [2:0] address;
input data;
reg [7:0] s;
initial begin
s = 3'b000;
end
always @(address or data or s) begin
if (address == 3'b000) s = 8'b00000001;
else if (address == 3'b001) s = 8'b00000010;
else if (address == 3'b... | 6.576075 |
module MUX4Bits (
s,
data0,
data1,
address
);
output [3:0] s;
input [3:0] data0;
input [3:0] data1;
input address;
reg [3:0] s;
always @(address or data1 or data0) begin
if (~address) begin
s = data0;
end else begin
s = data1;
end
end
endmodule
| 7.471602 |
module MUX8Bits3op (
s,
data0,
data1,
data2,
data3,
data4,
data5,
data6,
data7,
addr
);
output [7:0] s;
input [7:0] data0;
input [7:0] data1;
input [7:0] data2;
input [7:0] data3;
input [7:0] data4;
input [7:0] data5;
input [7:0] data6;
input [7:0] data7;
inpu... | 6.509488 |
module RAM2X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire add0;
wire add1;
wire [3:0] r1;
wire [3:0] r2;
DMUX1Bit SA (
add0,
add1,
address,
1
);
RAM1X4 R1 (
r1... | 6.765373 |
module RAM1X8 (
o,
data,
address,
rw,
clk,
clr
);
output [7:0] o;
input [7:0] data;
input address;
input rw;
input clk;
input clr;
RAM1X4 R1 (
o[3:0],
data[3:0],
address,
rw,
clk,
clr
);
RAM1X4 R2 (
o[7:4],
data[7:4],
addre... | 7.029692 |
module MUX8Bits (
s,
data0,
data1,
address
);
output [7:0] s;
input [7:0] data0;
input [7:0] data1;
input address;
reg [7:0] s;
always @(address or data1 or data0) begin
if (~address) begin
s = data0;
end else begin
s = data1;
end
end
endmodule
| 6.955345 |
module RAM2X8alternativo (
o,
data,
address,
rw,
clk,
clr
);
output [7:0] o;
input [7:0] data;
input address;
input rw;
input clk;
input clr;
wire add0;
wire add1;
wire [7:0] r1;
wire [7:0] r2;
DMUX1Bit SA (
add0,
add1,
address,
1
);
RAM1X8 R1... | 7.032084 |
module RAM1X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire [3:0] q;
wire [3:0] qnot;
wire [3:0] n;
wire w;
not N0 (n[0], data[3]);
not N1 (n[1], data[2]);
not N2 (n[2], data[1]);
not N3 (n[... | 6.842395 |
module DMUX3Bit (
s,
address,
data
);
output [7:0] s;
input [2:0] address;
input data;
reg [7:0] s;
initial begin
s = 3'b000;
end
always @(address or data or s) begin
if (address == 3'b000) s = 8'b00000001;
else if (address == 3'b001) s = 8'b00000010;
else if (address == 3'b... | 6.576075 |
module MUX4Bits (
s,
data0,
data1,
address
);
output [3:0] s;
input [3:0] data0;
input [3:0] data1;
input address;
reg [3:0] s;
always @(address or data1 or data0) begin
if (~address) begin
s = data0;
end else begin
s = data1;
end
end
endmodule
| 7.471602 |
module MUX8Bits3op (
s,
data0,
data1,
data2,
data3,
data4,
data5,
data6,
data7,
addr
);
output [7:0] s;
input [7:0] data0;
input [7:0] data1;
input [7:0] data2;
input [7:0] data3;
input [7:0] data4;
input [7:0] data5;
input [7:0] data6;
input [7:0] data7;
inpu... | 6.509488 |
module RAM2X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire add0;
wire add1;
wire [3:0] r1;
wire [3:0] r2;
DMUX1Bit SA (
add0,
add1,
address,
1
);
RAM1X4 R1 (
r1... | 6.765373 |
module RAM1X8 (
o,
data,
address,
rw,
clk,
clr
);
output [7:0] o;
input [7:0] data;
input address;
input rw;
input clk;
input clr;
RAM1X4 R1 (
o[3:0],
data[3:0],
address,
rw,
clk,
clr
);
RAM1X4 R2 (
o[7:4],
data[7:4],
addre... | 7.029692 |
module MUX8Bits (
s,
data0,
data1,
address
);
output [7:0] s;
input [7:0] data0;
input [7:0] data1;
input address;
reg [7:0] s;
always @(address or data1 or data0) begin
if (~address) begin
s = data0;
end else begin
s = data1;
end
end
endmodule
| 6.955345 |
module RAM2X8alternativo (
o,
data,
address,
rw,
clk,
clr
);
output [7:0] o;
input [7:0] data;
input address;
input rw;
input clk;
input clr;
wire add0;
wire add1;
wire [7:0] r1;
wire [7:0] r2;
DMUX1Bit SA (
add0,
add1,
address,
1
);
RAM1X8 R1... | 7.032084 |
module RAM1X16 (
o,
data,
address,
rw,
clk,
clr
);
output [15:0] o;
input [15:0] data;
input address;
input rw;
input clk;
input clr;
RAM1X8 R1 (
o[7:0],
data[7:0],
address,
rw,
clk,
clr
);
RAM1X8 R2 (
o[15:8],
data[15:8],
... | 7.038405 |
module DMUX2Bit (
s,
address,
data
);
output [3:0] s;
input [1:0] address;
input data;
reg [3:0] s;
initial begin
s = 4'b0000;
end
always @(address or data or s) begin
if (address == 3'b00) s = 4'b0001;
else if (address == 3'b01) s = 4'b0010;
else if (address == 3'b10) s = 4... | 6.552217 |
module DMUX3Bit (
s,
address,
data
);
output [7:0] s;
input [2:0] address;
input data;
reg [7:0] s;
initial begin
s = 3'b000;
end
always @(address or data or s) begin
if (address == 3'b000) s = 8'b00000001;
else if (address == 3'b001) s = 8'b00000010;
else if (address == 3'b... | 6.576075 |
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